@@ -431,6 +431,51 @@ static int qspi_set_memorymap(const struct device *dev)
431431
432432 return 0 ;
433433}
434+ #if 0
435+ /* Function send a Write Enable and wait it is effective. */
436+ static int qspi_set_we_memorymap (const struct device * dev )
437+ {
438+ struct flash_stm32_qspi_data * dev_data = dev -> data ;
439+ QSPI_AutoPollingTypeDef we_config ;
440+ QSPI_CommandTypeDef we_command = {
441+ .Instruction = SPI_NOR_CMD_WREN ,
442+ .InstructionMode = QSPI_INSTRUCTION_1_LINE ,
443+ .AddressMode = QSPI_ADDRESS_NONE ,
444+ .DataMode = QSPI_DATA_1_LINE ,
445+ .AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE ,
446+ .DummyCycles = 0 ,
447+ .DdrMode = QSPI_DDR_MODE_DISABLE ,
448+ .DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY ,
449+ .SIOOMode = QSPI_SIOO_INST_EVERY_CMD ,
450+ };
451+ we_command .NbData = 2 ;
452+
453+ /* Enable write operations */
454+ if (HAL_QSPI_Command (& dev_data -> hqspi , & we_command , HAL_QPSI_TIMEOUT_DEFAULT_VALUE ) != HAL_OK )
455+ {
456+ LOG_ERR ("Write Enable Failed to set memory map" );
457+ return - EIO ;
458+ }
459+ /* Configure automatic polling mode to wait for write enabling */
460+ we_config .Match = 0x0202 ;
461+ we_config .Mask = 0x0202 ;
462+ we_config .MatchMode = QSPI_MATCH_MODE_AND ;
463+ we_config .StatusBytesSize = 2 ;
464+ we_config .Interval = 0x10 ;
465+ we_config .AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE ;
466+
467+ we_command .Instruction = SPI_NOR_CMD_RDSR ;
468+ we_command .DataMode = QSPI_DATA_1_LINE ;
469+
470+ if (HAL_QSPI_AutoPolling (& dev_data -> hqspi , & we_command , & we_config , HAL_QPSI_TIMEOUT_DEFAULT_VALUE ) != HAL_OK )
471+ {
472+ LOG_ERR ("Write Enable Failed to set memory map" );
473+ return - EIO ;
474+ }
475+
476+ return 0 ;
477+ }
478+ #endif
434479#endif /* CONFIG_STM32_MEMMAP */
435480
436481static int flash_stm32_qspi_read (const struct device * dev , off_t addr ,
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