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drivers: pwm: Add a support for TI MSPM0 Timer PWM
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers with Compare block which is used to generate time expiry and output waveform like PWM. Add driver support for MSPM0 PWM output. Signed-off-by: Saravanan Sekar <[email protected]>
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‎drivers/pwm/CMakeLists.txt

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@@ -46,6 +46,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_INTEL_BLINKY pwm_intel_blinky.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XMC4XXX_CCU4 pwm_xmc4xxx_ccu4.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XMC4XXX_CCU8 pwm_xmc4xxx_ccu8.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_CTIMER pwm_mcux_ctimer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MSPM0 pwm_mspm0.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NUMAKER pwm_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NXP_FLEXIO pwm_nxp_flexio.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NXP_S32_EMIOS pwm_nxp_s32_emios.c)

‎drivers/pwm/Kconfig

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@@ -110,6 +110,8 @@ source "drivers/pwm/Kconfig.xmc4xxx_ccu8"
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source "drivers/pwm/Kconfig.mcux_ctimer"
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source "drivers/pwm/Kconfig.mspm0"
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source "drivers/pwm/Kconfig.numaker"
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source "drivers/pwm/Kconfig.nxp_s32_emios"

‎drivers/pwm/Kconfig.mspm0

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# Copyright (c) 2024 Linumiz GmbH
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# SPDX-License-Identifier: Apache-2.0
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config PWM_MSPM0
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bool "TI MSPM0 MCU family PWM driver"
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default y
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depends on DT_HAS_TI_MSPM0_TIMER_PWM_ENABLED
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select PINCTRL
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select USE_MSPM0_DL_TIMER
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help
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Enable TI MSPM0 MCU family PWM driver.

‎drivers/pwm/pwm_mspm0.c

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/*
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* Copyright (c) 2025, Linumiz GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_mspm0_timer_pwm
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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/* Driverlib includes */
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#include <ti/driverlib/dl_timera.h>
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#include <ti/driverlib/dl_timerg.h>
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#include <ti/driverlib/dl_timer.h>
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LOG_MODULE_REGISTER(pwm_mspm0, CONFIG_PWM_LOG_LEVEL);
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/* capture and compare block count per timer */
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#define MSPM0_TIMER_CC_COUNT 2
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#define MSPM0_TIMER_CC_MAX 4
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struct pwm_mspm0_config {
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const struct mspm0_sys_clock clock_subsys;
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const struct pinctrl_dev_config *pincfg;
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const struct device *clock_dev;
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GPTIMER_Regs *base;
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DL_Timer_ClockConfig clk_config;
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uint8_t cc_idx[MSPM0_TIMER_CC_MAX];
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uint8_t cc_idx_cnt;
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};
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struct pwm_mspm0_data {
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uint32_t pulse_cycle[MSPM0_TIMER_CC_MAX];
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uint32_t period;
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struct k_mutex lock;
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DL_TIMER_PWM_MODE out_mode;
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};
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static void mspm0_setup_pwm_out(const struct pwm_mspm0_config *config,
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struct pwm_mspm0_data *data)
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{
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int i;
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DL_Timer_PWMConfig pwmcfg = { 0 };
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uint8_t ccdir_mask = 0;
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pwmcfg.period = data->period;
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pwmcfg.pwmMode = data->out_mode;
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for (i = 0; i < config->cc_idx_cnt; i++) {
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if (config->cc_idx[i] >= MSPM0_TIMER_CC_COUNT) {
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pwmcfg.isTimerWithFourCC = true;
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break;
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}
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}
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DL_Timer_initPWMMode(config->base, &pwmcfg);
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for (i = 0; i < config->cc_idx_cnt; i++) {
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DL_Timer_setCaptureCompareValue(config->base,
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data->pulse_cycle[i],
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config->cc_idx[i]);
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ccdir_mask |= 1 << config->cc_idx[i];
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}
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DL_Timer_enableClock(config->base);
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DL_Timer_setCCPDirection(config->base, ccdir_mask);
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DL_Timer_startCounter(config->base);
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}
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static int mspm0_pwm_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_mspm0_config *config = dev->config;
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struct pwm_mspm0_data *data = dev->data;
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if (channel >= MSPM0_TIMER_CC_MAX) {
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LOG_ERR("Invalid channel");
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return -EINVAL;
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}
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if (period_cycles > UINT16_MAX) {
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LOG_ERR("period cycles exceeds 16-bit timer limit");
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return -ENOTSUP;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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data->pulse_cycle[channel] = pulse_cycles;
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data->period = period_cycles;
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if (data->out_mode == DL_TIMER_PWM_MODE_CENTER_ALIGN) {
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data->period = period_cycles >> 1;
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}
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DL_Timer_setLoadValue(config->base, data->period);
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DL_Timer_setCaptureCompareValue(config->base,
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data->pulse_cycle[channel],
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config->cc_idx[channel]);
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k_mutex_unlock(&data->lock);
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return 0;
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}
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static int mspm0_pwm_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_mspm0_config *config = dev->config;
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DL_Timer_ClockConfig clkcfg;
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uint32_t clock_rate;
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int ret;
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if (cycles == NULL) {
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return -EINVAL;
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}
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ret = clock_control_get_rate(config->clock_dev,
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(clock_control_subsys_t)&config->clock_subsys,
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&clock_rate);
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if (ret != 0) {
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LOG_ERR("clk get rate err %d", ret);
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return ret;
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}
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DL_Timer_getClockConfig(config->base, &clkcfg);
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*cycles = clock_rate /
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((clkcfg.divideRatio + 1) * (clkcfg.prescale + 1));
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return 0;
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}
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static int pwm_mspm0_init(const struct device *dev)
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{
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const struct pwm_mspm0_config *config = dev->config;
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struct pwm_mspm0_data *data = dev->data;
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int err;
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k_mutex_init(&data->lock);
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
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if (err < 0) {
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return err;
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}
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DL_Timer_reset(config->base);
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if (!DL_Timer_isPowerEnabled(config->base)) {
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DL_Timer_enablePower(config->base);
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}
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delay_cycles(CONFIG_MSPM0_PERIPH_STARTUP_DELAY);
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DL_Timer_setClockConfig(config->base,
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(DL_Timer_ClockConfig *)&config->clk_config);
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mspm0_setup_pwm_out(config, data);
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return 0;
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}
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static const struct pwm_driver_api pwm_mspm0_driver_api = {
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.set_cycles = mspm0_pwm_set_cycles,
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.get_cycles_per_sec = mspm0_pwm_get_cycles_per_sec,
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};
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#define MSPM0_PWM_MODE(mode) DT_CAT(DL_TIMER_PWM_MODE_, mode)
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#define MSPM0_CLK_DIV(div) DT_CAT(DL_TIMER_CLOCK_DIVIDE_, div)
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#define MSPM0_CC_IDX_ARRAY(node_id, prop, idx) \
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DT_PROP_BY_IDX(node_id, prop, idx),
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#define MSPM0_PWM_DATA(n) \
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.out_mode = MSPM0_PWM_MODE(DT_STRING_TOKEN(DT_DRV_INST(n), \
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ti_pwm_mode)),
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#define PWM_DEVICE_INIT_MSPM0(n) \
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static struct pwm_mspm0_data pwm_mspm0_data_ ## n = { \
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.period = DT_PROP(DT_DRV_INST(n), ti_period), \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(n), ti_pwm_mode), \
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(MSPM0_PWM_DATA(n)), ()) \
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}; \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct pwm_mspm0_config pwm_mspm0_config_ ## n = { \
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.base = (GPTIMER_Regs *)DT_REG_ADDR(DT_INST_PARENT(n)), \
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_IDX( \
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DT_INST_PARENT(n), 0)), \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.clock_subsys = { \
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.clk = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, clk),\
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}, \
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.cc_idx = { \
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DT_INST_FOREACH_PROP_ELEM(n, ti_cc_index, \
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MSPM0_CC_IDX_ARRAY) \
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}, \
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.cc_idx_cnt = DT_INST_PROP_LEN(n, ti_cc_index), \
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.clk_config = { \
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.clockSel = MSPM0_CLOCK_PERIPH_REG_MASK( \
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DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), \
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0, clk)), \
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.divideRatio = MSPM0_CLK_DIV(DT_PROP(DT_INST_PARENT(n), \
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ti_clk_div)), \
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.prescale = DT_PROP(DT_INST_PARENT(n), ti_clk_prescaler),\
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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pwm_mspm0_init, \
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NULL, \
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&pwm_mspm0_data_ ## n, \
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&pwm_mspm0_config_ ## n, \
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_mspm0_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT_MSPM0)

‎dts/bindings/pwm/ti,mspm0-pwm.yaml

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# Copyright 2025 Linumiz GmbH
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI MSPM0 PWM node for MSPM0 SoCs. Each channel in MSPM0 can be configured
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to use for PWM operation. There are three PWM modes supported by hardware.
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timer0: timer {
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pwm0: pwm {
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compatible = "ti,mspm0g-timer-pwm";
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#pwm-cells = <3>;
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ti,cc-index = <0>;
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ti,pwm-mode = "PULSE_WIDTH";
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ti,period = <1000>;
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};
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};
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compatible: "ti,mspm0-timer-pwm"
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include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
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properties:
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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ti,cc-index:
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type: array
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required: true
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description: |
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Capture input/Compare output index, should match with the pin function.
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ti,pwm-mode:
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type: string
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description: |
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Select PWM OUT mode:
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- EDGE_ALIGN: generate pulses with edge aligned down counting mode.
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- EDGE_ALIGN_UP: generate pulses with edge aligned up counting mode.
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- CENTER_ALIGN: generates pulses center aligned up and down counting mode.
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enum:
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- "EDGE_ALIGN"
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- "EDGE_ALIGN_UP"
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- "CENTER_ALIGN"
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ti,period:
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type: int
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required: true
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description: |
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Time period in TIMCLK cycle for Capture mode or PWM output.
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pwm-cells:
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- channel
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- period
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- flags

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