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tests/drivers/clock_control: stm32u5: Add tests on clock configs
Add a test suite to check various clocks configurations. Test is based on HAL functions that read clock configuration from registers. One test is build only, as there is no available hw to test it today. Others can be tested on target. More configurations and test points could be added in future. Signed-off-by: Erwan Gouriou <[email protected]>
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‎tests/drivers/clock_control/stm32_clock_configuration/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(stm32_clock_configuration)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})

‎tests/drivers/clock_control/stm32_clock_configuration/boards/b_u585i_iot02a_msis_24.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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&clk_lse {
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status = "okay";
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};
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&clk_msis {
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status = "okay";
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msi-range = <1>; /* Range 1: 24MHz */
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msi-pll-mode;
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};
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&pll1 { /* PLL disabled */
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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clocks = <&clk_msis>; /* clck src MSIS */
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clock-frequency = <DT_FREQ_M(24)>; /* clck freq 24MHz */
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/boards/b_u585i_iot02a_msis_48.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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&clk_lse {
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status = "okay";
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};
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&clk_msis {
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status = "okay";
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msi-range = <0>; /* Range 0: 48MHz */
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msi-pll-mode;
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};
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&pll1 { /* PLL disabled */
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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clocks = <&clk_msis>; /* clck src MSIS */
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clock-frequency = <DT_FREQ_M(48)>; /* clck freq 48MHz */
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/boards/b_u585i_iot02a_pll_hsi_160.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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&clk_lse {
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status = "disabled"; /* LSE disabled */
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};
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&clk_msis { /* MSI disabled */
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status = "disabled";
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/delete-property/ msi-range;
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/delete-property/ msi-pll-mode;
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};
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&clk_hsi { /* HSI enabled */
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status = "okay";
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};
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&pll1 {
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div-m = <4>; /* Update PLL config */
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mul-n = <40>;
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div-q = <2>;
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div-r = <1>;
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clocks = <&clk_hsi>; /* PLL src HSI */
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status = "okay";
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};
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&rcc {
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clocks = <&pll1>;
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clock-frequency = <DT_FREQ_M(160)>; /* clck freq 40MHz */
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/boards/b_u585i_iot02a_pll_hsi_40.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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&clk_lse {
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status = "disabled"; /* LSE disabled */
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};
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&clk_msis { /* MSI disabled */
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status = "disabled";
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/delete-property/ msi-range;
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/delete-property/ msi-pll-mode;
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};
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&clk_hsi { /* HSI enabled */
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status = "okay";
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};
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&pll1 {
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div-m = <4>; /* Update PLL config */
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mul-n = <10>;
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div-q = <2>;
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div-r = <1>;
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clocks = <&clk_hsi>; /* PLL src HSI */
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status = "okay";
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};
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&rcc {
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clocks = <&pll1>;
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clock-frequency = <DT_FREQ_M(40)>; /* clck freq 40MHz */
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/boards/b_u585i_iot02a_pll_msi_80.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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&clk_lse {
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status = "okay";
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};
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&clk_msis {
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status = "okay";
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msi-range = <4>;
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msi-pll-mode;
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};
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&pll1 {
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div-m = <2>; /* Update PLL config */
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mul-n = <40>;
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div-q = <2>;
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div-r = <1>;
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clocks = <&clk_msis>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll1>;
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clock-frequency = <DT_FREQ_M(80)>; /* clck freq 80MHz */
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/boards/nucleo_u575zi_q_pll_hse_160.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay relies on initial board configuration.
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* For clarity, nodes are over written instead of deleted.
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* Any change to board configuration has impact on this file.
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*/
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/*
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* Warning: HSE is not implmeneed on the board, hence:
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* This configuration is only available for build
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*/
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&clk_lse {
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status = "disabled"; /* LSE disabled */
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};
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&clk_msis { /* MSI disabled */
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status = "disabled";
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/delete-property/ msi-range;
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/delete-property/ msi-pll-mode;
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};
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&clk_hse { /* HSE enabled */
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status = "okay";
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clock-frequency = <DT_FREQ_M(16)>; /* HSE clk freq 16MHz */
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hse-bypass;
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};
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&pll1 {
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div-m = <4>; /* Update PLL config */
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mul-n = <40>;
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div-q = <2>;
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div-r = <1>;
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clocks = <&clk_hse>; /* PLL src HSE */
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(160)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/prj.conf‎

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CONFIG_ZTEST=y

‎tests/drivers/clock_control/stm32_clock_configuration/src/test_stm32_clock_configuration.c‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ztest.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(test);
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static void test_sysclk_freq(void)
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{
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uint32_t soc_sys_clk_freq;
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soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
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zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
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"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
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}
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static void test_sysclk_src(void)
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{
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int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
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#if STM32_SYSCLK_SRC_PLL
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zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
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"Expected sysclk src: PLL1. Actual sysclk src: %d",
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sys_clk_src);
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#elif STM32_SYSCLK_SRC_HSE
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zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
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"Expected sysclk src: HSE. Actual sysclk src: %d",
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sys_clk_src);
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#elif STM32_SYSCLK_SRC_HSI
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zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
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"Expected sysclk src: HSI. Actual sysclk src: %d",
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sys_clk_src);
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#elif STM32_SYSCLK_SRC_MSIS
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zassert_equal(RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src,
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"Expected sysclk src: MSI. Actual sysclk src: %d",
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sys_clk_src);
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#else
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/* Case not expected */
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zassert_true((STM32_SYSCLK_SRC_PLL ||
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STM32_SYSCLK_SRC_HSE ||
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STM32_SYSCLK_SRC_HSI ||
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STM32_SYSCLK_SRC_MSIS),
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"Not expected. sys_clk_src: %d\n", sys_clk_src);
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#endif
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}
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static void test_pll_src(void)
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{
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uint32_t pll_src = __HAL_RCC_GET_PLL_OSCSOURCE();
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#if STM32_PLL_SRC_HSE
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zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
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"Expected PLL src: HSE. Actual PLL src: %d",
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pll_src);
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#elif STM32_PLL_SRC_HSI
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zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
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"Expected PLL src: HSI. Actual PLL src: %d",
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pll_src);
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#elif STM32_PLL_SRC_MSIS
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zassert_equal(RCC_PLLSOURCE_MSI, pll_src,
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"Expected PLL src: MSI. Actual PLL src: %d",
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pll_src);
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#else
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zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
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"Expected PLL src: None. Actual PLL src: %d",
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pll_src);
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#endif
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}
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void test_main(void)
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{
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ztest_test_suite(test_stm32_syclck_config,
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ztest_unit_test(test_sysclk_freq),
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ztest_unit_test(test_sysclk_src),
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ztest_unit_test(test_pll_src)
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);
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ztest_run_test_suite(test_stm32_syclck_config);
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}

‎tests/drivers/clock_control/stm32_clock_configuration/testcase.yaml‎

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tests:
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drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
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timeout: 5
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platform_allow: b_u585i_iot02a
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drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_80:
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extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_msi_80.overlay
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timeout: 5
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platform_allow: b_u585i_iot02a
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drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
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extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_hsi_160.overlay
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platform_allow: b_u585i_iot02a
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timeout: 5
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drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40:
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extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_hsi_40.overlay
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platform_allow: b_u585i_iot02a
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timeout: 5
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drivers.stm32_clock_configuration.u5.sysclksrc_msis_48:
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extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_msis_48.overlay
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platform_allow: b_u585i_iot02a
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timeout: 5
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drivers.stm32_clock_configuration.u5.sysclksrc_msis_24:
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extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_msis_24.overlay
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platform_allow: b_u585i_iot02a
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timeout: 5
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drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_160:
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extra_args: DTC_OVERLAY_FILE=boards/nucleo_u575zi_q_pll_hse_160.overlay
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timeout: 5
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platform_allow: nucleo_u575zi_q
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build_only: true # Build only as HSE not implemened on the board

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