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drivers: clock control: Add Clock Control support for RZ/A3UL, V2L
Add Clock Control driver support for Renesas RZ/A3UL, V2L Signed-off-by: Quang Le <[email protected]> Signed-off-by: Tien Nguyen <[email protected]>
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7 files changed

+319
-33
lines changed

7 files changed

+319
-33
lines changed

‎drivers/clock_control/clock_control_renesas_rz_cpg.c‎

Lines changed: 65 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,22 @@
55
*/
66

77
#include <zephyr/drivers/clock_control.h>
8-
#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
98
#include <zephyr/kernel.h>
9+
#include <zephyr/sys/util.h>
10+
#include <bsp_api.h>
11+
12+
#if defined(CONFIG_SOC_SERIES_RZG3S)
13+
#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
14+
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
15+
#include <zephyr/dt-bindings/clock/renesas_rza_clock.h>
16+
#elif defined(CONFIG_SOC_SERIES_RZV2L)
17+
#include <zephyr/dt-bindings/clock/renesas_rzv_clock.h>
18+
#endif
19+
20+
#define RZ_CLOCK_DIV(clock_id) ((clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT)
21+
#define RZ_CLOCK_IP(clock_id) ((clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT)
22+
#define RZ_CLOCK_IP_CHANNEL(clock_id) ((clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT)
23+
#define RZ_CLOCK_SRC(clock_id) ((clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT)
1024

1125
#define DT_DRV_COMPAT renesas_rz_cpg
1226

@@ -18,15 +32,15 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s
1832

1933
uint32_t *clock_id = (uint32_t *)sys;
2034

21-
uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
22-
uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
35+
uint32_t ip = RZ_CLOCK_IP(*clock_id);
36+
uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id);
2337

2438
switch (ip) {
2539
case RZ_IP_GTM:
2640
R_BSP_MODULE_START(FSP_IP_GTM, ch);
2741
break;
28-
case RZ_IP_GPT:
29-
R_BSP_MODULE_START(FSP_IP_GPT, ch);
42+
case RZ_IP_SCI:
43+
R_BSP_MODULE_START(FSP_IP_SCI, ch);
3044
break;
3145
case RZ_IP_SCIF:
3246
R_BSP_MODULE_START(FSP_IP_SCIF, ch);
@@ -37,18 +51,32 @@ static int clock_control_renesas_rz_on(const struct device *dev, clock_control_s
3751
case RZ_IP_RSPI:
3852
R_BSP_MODULE_START(FSP_IP_RSPI, ch);
3953
break;
54+
case RZ_IP_CANFD:
55+
R_BSP_MODULE_START(FSP_IP_CANFD, ch);
56+
break;
57+
#if !defined(CONFIG_SOC_SERIES_RZV2L)
58+
case RZ_IP_ADC:
59+
R_BSP_MODULE_START(FSP_IP_ADC, ch);
60+
break;
61+
case RZ_IP_WDT:
62+
R_BSP_MODULE_START(FSP_IP_WDT, ch);
63+
break;
64+
#endif
65+
#if !defined(CONFIG_SOC_SERIES_RZA3UL)
66+
case RZ_IP_GPT:
67+
R_BSP_MODULE_START(FSP_IP_GPT, ch);
68+
break;
4069
case RZ_IP_MHU:
4170
R_BSP_MODULE_START(FSP_IP_MHU, ch);
4271
break;
4372
case RZ_IP_DMAC:
4473
R_BSP_MODULE_START(FSP_IP_DMAC, ch);
4574
break;
46-
case RZ_IP_CANFD:
47-
R_BSP_MODULE_START(FSP_IP_CANFD, ch);
48-
break;
49-
case RZ_IP_ADC:
50-
R_BSP_MODULE_START(FSP_IP_ADC, ch);
75+
#else
76+
case RZ_IP_DMAC:
77+
R_BSP_MODULE_START(FSP_IP_DMAC_NS, ch);
5178
break;
79+
#endif
5280
default:
5381
return -EINVAL; /* Invalid FSP IP Module */
5482
}
@@ -64,15 +92,15 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_
6492

6593
uint32_t *clock_id = (uint32_t *)sys;
6694

67-
uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
68-
uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
95+
uint32_t ip = RZ_CLOCK_IP(*clock_id);
96+
uint32_t ch = RZ_CLOCK_IP_CHANNEL(*clock_id);
6997

7098
switch (ip) {
7199
case RZ_IP_GTM:
72100
R_BSP_MODULE_STOP(FSP_IP_GTM, ch);
73101
break;
74-
case RZ_IP_GPT:
75-
R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
102+
case RZ_IP_SCI:
103+
R_BSP_MODULE_STOP(FSP_IP_SCI, ch);
76104
break;
77105
case RZ_IP_SCIF:
78106
R_BSP_MODULE_STOP(FSP_IP_SCIF, ch);
@@ -83,21 +111,36 @@ static int clock_control_renesas_rz_off(const struct device *dev, clock_control_
83111
case RZ_IP_RSPI:
84112
R_BSP_MODULE_STOP(FSP_IP_RSPI, ch);
85113
break;
114+
case RZ_IP_CANFD:
115+
R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
116+
break;
117+
#if !defined(CONFIG_SOC_SERIES_RZV2L)
118+
case RZ_IP_ADC:
119+
R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
120+
break;
121+
case RZ_IP_WDT:
122+
R_BSP_MODULE_STOP(FSP_IP_WDT, ch);
123+
break;
124+
#endif
125+
#if !defined(CONFIG_SOC_SERIES_RZA3UL)
126+
case RZ_IP_GPT:
127+
R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
128+
break;
86129
case RZ_IP_MHU:
87130
R_BSP_MODULE_STOP(FSP_IP_MHU, ch);
88131
break;
89132
case RZ_IP_DMAC:
90133
R_BSP_MODULE_STOP(FSP_IP_DMAC, ch);
91134
break;
92-
case RZ_IP_CANFD:
93-
R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
94-
break;
95-
case RZ_IP_ADC:
96-
R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
135+
#else
136+
case RZ_IP_DMAC:
137+
R_BSP_MODULE_STOP(FSP_IP_DMAC_NS, ch);
97138
break;
139+
#endif
98140
default:
99-
return -EINVAL; /* Invalid */
141+
return -EINVAL; /* Invalid FSP IP Module */
100142
}
143+
101144
return 0;
102145
}
103146

@@ -110,8 +153,8 @@ static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_con
110153

111154
uint32_t *clock_id = (uint32_t *)sys;
112155

113-
fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
114-
uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT;
156+
fsp_priv_clock_t clk_src = RZ_CLOCK_SRC(*clock_id);
157+
uint32_t clk_div = RZ_CLOCK_DIV(*clock_id);
115158

116159
uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
117160
*rate = clk_hz / clk_div;

‎dts/bindings/clock/renesas,rz-cpg-clock.yaml‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
# Copyright (c) 2025 Renesas Electronics Corporation
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: Renesas RZ Clock Pulse Generator Clock Output
5+
6+
compatible: "renesas,rz-cpg-clock"
7+
8+
include: [base.yaml, clock-controller.yaml]
9+
10+
properties:
11+
clocks:
12+
required: true
13+
14+
div:
15+
type: int
16+
17+
"#clock-cells":
18+
const: 0

‎dts/bindings/clock/renesas,rz-cpg-pll.yaml‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
# Copyright (c) 2025 Renesas Electronics Corporation
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: Renesas RZ Clock Pulse Generator PLL Output
5+
6+
compatible: "renesas,rz-cpg-pll"
7+
8+
include: [clock-controller.yaml]
9+
10+
properties:
11+
clock-frequency:
12+
type: int
13+
description: PLL output clock frequency (Hz)
14+
required: true
15+
16+
"#clock-cells":
17+
const: 1
18+
19+
clock-cells:
20+
- postscaler

‎dts/bindings/clock/renesas,rz-cpg.yaml‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,21 @@
1-
# Copyright (c) 2024 Renesas Electronics Corporation24
1+
# Copyright (c) 2024-2025 Renesas Electronics Corporation
22
# SPDX-License-Identifier: Apache-2.0
33

4-
description: RZ Clock Pulse Generator
4+
description: |
5+
Renesas RZ Clock Pulse Generator
6+
7+
Usage example:
8+
9+
#include <zephyr/dt-bindings/clock/renesas_rz[agv]_clock.h>
10+
11+
scif0: serial@xxx {
12+
...
13+
channel = <0>;
14+
/* Cell encodes HWIP, channel, clock source and division */
15+
clocks = <&cpg RZ_CLOCK_SCIF(0)>;
16+
...
17+
}
18+
519
compatible: "renesas,rz-cpg"
620

721
include: [base.yaml, clock-controller.yaml]

‎include/zephyr/dt-bindings/clock/renesas_rza_clock.h‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
/*
2+
* Copyright (c) 2025 Renesas Electronics Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_
8+
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_
9+
10+
/* RZ/A clock configuration values */
11+
#define RZ_IP_MASK 0xFF000000UL
12+
#define RZ_IP_SHIFT 24UL
13+
#define RZ_IP_CH_MASK 0xFF0000UL
14+
#define RZ_IP_CH_SHIFT 16UL
15+
#define RZ_CLOCK_MASK 0xFF00UL
16+
#define RZ_CLOCK_SHIFT 8UL
17+
#define RZ_CLOCK_DIV_MASK 0xFFUL
18+
#define RZ_CLOCK_DIV_SHIFT 0UL
19+
20+
#define RZ_IP_GTM 0UL /* General Timer */
21+
#define RZ_IP_SCI 1UL /* Serial Communications Interface */
22+
#define RZ_IP_SCIF 2UL /* Serial Communications Interface with FIFO */
23+
#define RZ_IP_RIIC 3UL /* I2C Bus Interface */
24+
#define RZ_IP_RSPI 4UL /* Renesas Serial Peripheral Interface */
25+
#define RZ_IP_DMAC 5UL /* Direct Memory Access Controller */
26+
#define RZ_IP_CANFD 6UL /* CANFD Interface (RS-CANFD) */
27+
#define RZ_IP_ADC 7UL /* A/D Converter */
28+
#define RZ_IP_WDT 8UL /* Watchdog Timer */
29+
30+
#define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */
31+
#define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */
32+
#define RZ_CLOCK_S0CLK 2UL /* DDR-PHY Clock */
33+
#define RZ_CLOCK_SPI0CLK 3UL /* SPI0 Clock */
34+
#define RZ_CLOCK_SPI1CLK 4UL /* SPI1 Clock */
35+
#define RZ_CLOCK_OC0CLK 5UL /* Octa0 Clock */
36+
#define RZ_CLOCK_OC1CLK 6UL /* Octa1 Clock */
37+
#define RZ_CLOCK_SD0CLK 7UL /* SDH0 Clock */
38+
#define RZ_CLOCK_SD1CLK 8UL /* SDH1 Clock */
39+
#define RZ_CLOCK_M0CLK 9UL /* VCP, LCDC Clock */
40+
#define RZ_CLOCK_M2CLK 10UL /* CRU, MIPI-DSI Clock */
41+
#define RZ_CLOCK_M3CLK 11UL /* MIPI-DSI, LCDC Clock */
42+
#define RZ_CLOCK_HPCLK 12UL /* Ethernet Clock */
43+
#define RZ_CLOCK_TSUCLK 13UL /* TSU Clock */
44+
#define RZ_CLOCK_ZTCLK 14UL /* JAUTH Clock */
45+
#define RZ_CLOCK_P0CLK 15UL /* APB-BUS Clock */
46+
#define RZ_CLOCK_P1CLK 16UL /* AXI-BUS Clock */
47+
#define RZ_CLOCK_P2CLK 17UL /* P2CLK */
48+
#define RZ_CLOCK_ATCLK 18UL /* ATCLK */
49+
#define RZ_CLOCK_OSCCLK 19UL /* OSC Clock */
50+
51+
#define RZ_CLOCK(IP, ch, clk, div) \
52+
((RZ_IP_##IP << RZ_IP_SHIFT) | ((ch) << RZ_IP_CH_SHIFT) | ((clk) << RZ_CLOCK_SHIFT) | \
53+
((div) << RZ_CLOCK_DIV_SHIFT))
54+
55+
/**
56+
* Pack clock configurations in a 32-bit value
57+
* as expected for the Device Tree `clocks` property on Renesas RZ/A.
58+
*
59+
* @param ch Peripheral channel/unit
60+
*/
61+
62+
/* GTM */
63+
#define RZ_CLOCK_GTM(ch) RZ_CLOCK(GTM, ch, RZ_CLOCK_P0CLK, 1)
64+
65+
/* SCI */
66+
#define RZ_CLOCK_SCI(ch) RZ_CLOCK(SCI, ch, RZ_CLOCK_P0CLK, 1)
67+
68+
/* SCIF */
69+
#define RZ_CLOCK_SCIF(ch) RZ_CLOCK(SCIF, ch, RZ_CLOCK_P0CLK, 1)
70+
71+
/* RIIC */
72+
#define RZ_CLOCK_RIIC(ch) RZ_CLOCK(RIIC, ch, RZ_CLOCK_P0CLK, 1)
73+
74+
/* RSPI */
75+
#define RZ_CLOCK_RSPI(ch) RZ_CLOCK(RSPI, ch, RZ_CLOCK_P0CLK, 1)
76+
77+
/* DMAC */
78+
#define RZ_CLOCK_DMAC_NS(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P1CLK, 1)
79+
80+
/* CAN */
81+
#define RZ_CLOCK_CANFD(ch) RZ_CLOCK(CANFD, ch, RZ_CLOCK_P0CLK, 1)
82+
83+
/* ADC */
84+
#define RZ_CLOCK_ADC(ch) RZ_CLOCK(ADC, ch, RZ_CLOCK_P0CLK, 1)
85+
86+
/* WDT */
87+
#define RZ_CLOCK_WDT(ch) RZ_CLOCK(WDT, ch, RZ_CLOCK_P0CLK, 1)
88+
89+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/renesas_rzg_clock.h‎

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -17,15 +17,17 @@
1717
#define RZ_CLOCK_DIV_MASK 0xFFUL
1818
#define RZ_CLOCK_DIV_SHIFT 0UL
1919

20-
#define RZ_IP_GTM 0UL /* General Timer */
21-
#define RZ_IP_GPT 1UL /* General PWM Timer */
22-
#define RZ_IP_SCIF 2UL /* Serial Communications Interface with FIFO */
23-
#define RZ_IP_RIIC 3UL /* I2C Bus Interface */
24-
#define RZ_IP_RSPI 4UL /* Renesas Serial Peripheral Interface */
25-
#define RZ_IP_MHU 5UL /* Message Handling Unit */
26-
#define RZ_IP_DMAC 6UL /* Direct Memory Access Controller */
27-
#define RZ_IP_CANFD 7UL /* CANFD Interface (RS-CANFD) */
28-
#define RZ_IP_ADC 8UL /* A/D Converter */
20+
#define RZ_IP_GTM 0UL /* General Timer */
21+
#define RZ_IP_GPT 1UL /* General PWM Timer */
22+
#define RZ_IP_SCI 2UL /* Serial Communications Interface */
23+
#define RZ_IP_SCIF 3UL /* Serial Communications Interface with FIFO */
24+
#define RZ_IP_RIIC 4UL /* I2C Bus Interface */
25+
#define RZ_IP_RSPI 5UL /* Renesas Serial Peripheral Interface */
26+
#define RZ_IP_MHU 6UL /* Message Handling Unit */
27+
#define RZ_IP_DMAC 7UL /* Direct Memory Access Controller */
28+
#define RZ_IP_CANFD 8UL /* CANFD Interface (RS-CANFD) */
29+
#define RZ_IP_ADC 9UL /* A/D Converter */
30+
#define RZ_IP_WDT 10UL /* Watchdog Timer */
2931

3032
#define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */
3133
#define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */
@@ -90,4 +92,10 @@
9092
/* DMAC */
9193
#define RZ_CLOCK_DMAC(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P3CLK, 1)
9294

95+
/* SCI */
96+
#define RZ_CLOCK_SCI(ch) RZ_CLOCK(SCI, ch, RZ_CLOCK_P0CLK, 1)
97+
98+
/* WDT */
99+
#define RZ_CLOCK_WDT(ch) RZ_CLOCK(WDT, ch, RZ_CLOCK_OSCCLK, 1)
100+
93101
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_ */

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