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JiafeiPancarlescufi
JiafeiPan
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carlescufi
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board: imx8mm_evk: enable ENET ethernet on Cortex-A Core
Enabled ENET ethernet port on Cortex-A Core for imx8mm EVK board. Updated suported featues in board document. Signed-off-by: Jiafei Pan <[email protected]>
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‎boards/nxp/imx8mm_evk/Kconfig.defconfig‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_IMX8MM_EVK
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if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
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if NETWORKING
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config NET_L2_ETHERNET
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default y
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config NET_TX_STACK_SIZE
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default 8192
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config NET_RX_STACK_SIZE
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default 8192
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if NET_TCP
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config NET_TCP_WORKQ_STACK_SIZE
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default 8192
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endif # NET_TCP
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if NET_MGMT_EVENT
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config NET_MGMT_EVENT_STACK_SIZE
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default 8192
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endif # NET_MGMT_EVENT
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if NET_SOCKETS_SERVICE
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config NET_SOCKETS_SERVICE_STACK_SIZE
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default 8192
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endif # NET_SOCKETS_SERVICE
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endif # NETWORKING
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endif # BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
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endif # BOARD_IMX8MM_EVK

‎boards/nxp/imx8mm_evk/doc/index.rst‎

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+-----------+------------+-------------------------------------+
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| ARM TIMER | on-chip | system clock |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| RDC | on-chip | Resource Domain Controller |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+-----------+------------+-------------------------------------+
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| GPT | on-chip | timer |
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+-----------+------------+-------------------------------------+
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| ENET | on-chip | ethernet port |
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+-----------+------------+-------------------------------------+
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The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware
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features:

‎boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi‎

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};
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};
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pinmux_enet: pinmux_enet {
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group0 {
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pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
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<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
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<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
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<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
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<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
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<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
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slew-rate = "fast";
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drive-strength = "x6";
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};
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group1 {
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pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
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<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
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<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
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<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
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<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
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<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
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slew-rate = "fast";
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drive-strength = "x1";
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};
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group2 {
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pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
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slew-rate = "fast";
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drive-strength = "x1";
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};
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};
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pinmux_mdio: pinmux_mdio {
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group0 {
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pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
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<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
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slew-rate = "slow";
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drive-strength = "x6";
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};
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};
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};

‎boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts‎

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/*
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* Copyright 2020-2022 NXP
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* Copyright 2020-2022,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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};
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};
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&enet {
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status = "okay";
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};
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&enet_mac {
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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phy-handle = <&phy>;
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zephyr,random-mac-address;
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phy-connection-type = "rgmii";
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status = "okay";
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};
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&enet_mdio {
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pinctrl-0 = <&pinmux_mdio>;
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pinctrl-names = "default";
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status = "okay";
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phy: phy@0 {
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compatible = "qca,ar8031";
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reg = <0>;
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status = "okay";
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};
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};
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&uart4 {
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current-speed = <115200>;
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pinctrl-0 = <&uart4_default>;

‎boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig‎

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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# Serial Drivers
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CONFIG_SERIAL=y

‎boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts‎

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/*
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* Copyright 2021-2022 NXP
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* Copyright 2021-2022,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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};
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};
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&enet {
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status = "okay";
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};
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&enet_mac {
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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phy-handle = <&phy>;
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zephyr,random-mac-address;
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phy-connection-type = "rgmii";
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status = "okay";
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};
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&enet_mdio {
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pinctrl-0 = <&pinmux_mdio>;
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pinctrl-names = "default";
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status = "okay";
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phy: phy@0 {
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compatible = "qca,ar8031";
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reg = <0>;
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status = "okay";
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};
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};
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&uart4 {
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current-speed = <115200>;
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pinctrl-0 = <&uart4_default>;

‎boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig‎

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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# SMP
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CONFIG_SMP=y

‎dts/arm64/nxp/nxp_mimx8mm_a53.dtsi‎

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compatible = "nxp,rdc";
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reg = <0x303d0000 DT_SIZE_K(64)>;
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};
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enet: enet@30be0000 {
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compatible = "nxp,enet1g";
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reg = <0x30be0000 DT_SIZE_K(64)>;
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clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
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rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
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status = "disabled";
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enet_mac: ethernet {
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compatible = "nxp,enet-mac";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "COMMON";
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interrupt-parent = <&gic>;
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nxp,mdio = <&enet_mdio>;
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nxp,ptp-clock = <&enet_ptp_clock>;
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status = "disabled";
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};
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enet_mdio: mdio {
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compatible = "nxp,enet-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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enet_ptp_clock: ptp_clock {
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compatible = "nxp,enet-ptp-clock";
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
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status = "disabled";
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};
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};
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};

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