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mariopajamariopaja
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dt-bindings: clock: add stm32l5_clock
This change introduces stm32l5xx clock definitions and separates it from L4xx series. This change comes because of CCIPR missmatch of SAI between L4xx and L5xx series. Signed-off-by: Mario Paja <[email protected]>
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‎dts/arm/st/l5/stm32l5.dtsi‎

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* Copyright (c) 2021 The Chromium OS Authors
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* Copyright (c) 2020 Linaro Limited
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* Copyright (c) 2024 STMicroelectronics
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* Copyright (c) 2025 Mario Paja
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>

‎include/zephyr/dt-bindings/clock/stm32l4_clock.h‎

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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
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/** Domain clocks */
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/* RM0351/RM0432/RM0438, § Clock configuration register (RCC_CCIPRx) */
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/* RM0351/RM0432, § Clock configuration register (RCC_CCIPRx) */
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/** System clock */
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/* defined in stm32_common_clocks.h */

‎include/zephyr/dt-bindings/clock/stm32l5_clock.h‎

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/*
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* Copyright (c) 2025 Mario Paja
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_
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#include "stm32_common_clocks.h"
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/** Bus clocks */
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#define STM32_CLOCK_BUS_AHB1 0x048
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#define STM32_CLOCK_BUS_AHB2 0x04c
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#define STM32_CLOCK_BUS_AHB3 0x050
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#define STM32_CLOCK_BUS_APB1 0x058
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#define STM32_CLOCK_BUS_APB1_2 0x05c
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#define STM32_CLOCK_BUS_APB2 0x060
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
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/** Domain clocks */
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/* RM0438, § Clock configuration register (RCC_CCIPRx) */
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/** System clock */
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/* defined in stm32_common_clocks.h */
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/** Fixed clocks */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
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#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
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/** Bus clock */
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#define STM32_SRC_PCLK (STM32_SRC_MSI + 1)
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#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1)
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#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
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/** PLL clock outputs */
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#define STM32_SRC_PLL_P (STM32_SRC_TIMPCLK2 + 1)
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#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
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#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
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/* PLLSAI1 clocks */
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#define STM32_SRC_PLLSAI1_P (STM32_SRC_PLL_R + 1)
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#define STM32_SRC_PLLSAI1_Q (STM32_SRC_PLLSAI1_P + 1)
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#define STM32_SRC_PLLSAI1_R (STM32_SRC_PLLSAI1_Q + 1)
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/* PLLSAI2 clocks */
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#define STM32_SRC_PLLSAI2_P (STM32_SRC_PLLSAI1_R + 1)
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#define STM32_SRC_PLLSAI2_Q (STM32_SRC_PLLSAI2_P + 1)
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#define STM32_SRC_PLLSAI2_R (STM32_SRC_PLLSAI2_Q + 1)
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#define STM32_SRC_PLLSAI2_DIVR (STM32_SRC_PLLSAI2_R + 1)
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/** @brief RCC_CCIPR register offset */
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#define CCIPR_REG 0x88
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#define CCIPR2_REG 0x9C
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/** @brief RCC_BDCR register offset */
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#define BDCR_REG 0x90
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/** @brief RCC_CFGRx register offset */
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#define CFGR_REG 0x08
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/** @brief Device domain clocks selection helpers */
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/** CCIPR devices */
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
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#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
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#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
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#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
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#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG)
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#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
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#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
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/** CCIPR2 devices */
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#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
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#define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG)
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#define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 5, CCIPR2_REG)
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#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
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#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
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#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
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/** BDCR devices */
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
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/** CFGR devices */
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L5_CLOCK_H_ */

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