soc: renesas: Maintain the minimal support of Renesas RZ/T2M

Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices

- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas

Signed-off-by: Hieu Nguyen <[email protected]>
Signed-off-by: Nhut Nguyen <[email protected]>
Signed-off-by: Binh Nguyen <[email protected]>

Author: Hieu Nguyen

dts/arm/renesas/rz/rzt/r9a07g075.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a07g075";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <1>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+				<0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		cpu0_atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(512)>;
+		};
+
+		cpu0_btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(64)>;
+		};
+
+		sram: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 DT_SIZE_M(2)>;
+		};
+
+		xspi0_cs0: memory@60000000 {
+			compatible = "mmio-sram";
+			reg = <0x60000000 DT_SIZE_M(64)>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				loader_param: partition@0 {
+					label = "loader-param";
+					reg = <0x00000000 0x4C>;
+					read-only;
+				};
+
+				loader_program: partition@4C {
+					label = "loader-program";
+					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
+					read-only;
+				};
+
+				slot0_partition: partition@E000 {
+					label = "image-0";
+					reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+					read-only;
+				};
+			};
+		};
+	};
+};

dts/arm/renesas/rz/rzt2m.dtsi

@@ -1,8 +1,15 @@
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(soc.c)
+zephyr_sources(
+  soc.c
+  loader_param.c
+  ../common/loader_program.S
+)
 
 zephyr_include_directories(.)
 
+zephyr_linker_sources(SECTIONS sections.ld)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/rzt2m/CMakeLists.txt renamed to soc/renesas/rz/rzt2m/CMakeLists.txt

@@ -1,11 +1,14 @@
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_RENESAS_RZT2M
+config SOC_SERIES_RZT2M
 	select ARM
 	select CPU_CORTEX_R52
 	select CPU_HAS_ARM_MPU
 	select GIC_SINGLE_SECURITY_STATE
 	select ARM_ARCH_TIMER
-	select SYSCON
+	select HAS_RENESAS_RZ_FSP
+	select SOC_RESET_HOOK
 	select SOC_EARLY_INIT_HOOK
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER

soc/renesas/rzt2m/Kconfig renamed to soc/renesas/rz/rzt2m/Kconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZT2M
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZT2M

soc/renesas/rz/rzt2m/Kconfig.defconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZT2M
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/T2M series
+
+config SOC_SERIES
+	default "rzt2m" if SOC_SERIES_RZT2M
+
+config SOC_R9A07G075M24GBG
+	bool
+	select SOC_SERIES_RZT2M
+	help
+	  R9A07G075M24GBG
+
+config SOC_R9A07G075M24GBG_CR520
+	bool
+	select SOC_R9A07G075M24GBG
+
+config SOC
+	default "r9a07g075m24gbg" if SOC_R9A07G075M24GBG