soc:arm:nxp_s32ze: Create MPU regions for separated code and data

The NXP s32ze board configs and mpu regions associate all code and data
with the SRAM 0/1/ext of the architecture. There are 7 MBs of SRAMs
per RTU which are dedicated to code use. Using them for the Zephyr
flash target trips the MPU regions which assume a RODATA/TEXT endpoint
as the beginning of the DATA/BSS section. Update to use the Code SRAMs
for code and associate the MPU region with the data image start
location.

Signed-off-by: Matthew Christian <[email protected]>

Author: mcc-terraline

boards/nxp/s32z2xxdc2/Kconfig.defconfig

@@ -6,6 +6,9 @@ if BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
 config BUILD_OUTPUT_BIN
 	default n
 
+config XIP
+	default y
+
 if SERIAL
 
 config UART_INTERRUPT_DRIVEN

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts

@@ -14,6 +14,7 @@
 
 	chosen {
 		zephyr,sram = &sram0;
+		zephyr,flash = &sram_code0;
 		zephyr,canbus = &canxl0;
 	};
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig

@@ -1,7 +1,7 @@
 # Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_XIP=n
+CONFIG_XIP=y
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts

@@ -14,6 +14,7 @@
 
 	chosen {
 		zephyr,sram = &sram1;
+		zephyr,flash = &sram_code1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,canbus = &flexcan0;

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig

@@ -1,7 +1,7 @@
 # Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_XIP=n
+CONFIG_XIP=y
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -120,6 +120,16 @@
 			reg = <0x35780000 DT_SIZE_M(1)>;
 		};
 
+		sram_code0: memory@32100000 {
+			compatible = "mmio-sram";
+			reg = <0x32100000 DT_SIZE_M(7)>;
+		};
+
+		sram_code1: memory@36100000 {
+			compatible = "mmio-sram";
+			reg = <0x36100000 DT_SIZE_M(7)>;
+		};
+
 		uart0: uart@40170000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40170000 0x1000>;

soc/nxp/s32/s32ze/mpu_regions.c

@@ -24,7 +24,7 @@ static const struct arm_mpu_region mpu_regions[] = {
 			 REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
 
 	MPU_REGION_ENTRY("SRAM_DATA",
-			 (uintptr_t)__rom_region_end,
+			 (uintptr_t)_image_ram_start,
 			 REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
 
 	MPU_REGION_ENTRY("DEVICE",