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duynguyenxanashif
duynguyenxa
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nashif
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driver: gpio: Add initial gpio drirver support for RA8M1
This is the initial commit to support for gpio driver for RA8M1 MCU, the coding is base on renesas fsp hal Signed-off-by: Duy Nguyen <[email protected]>
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‎drivers/gpio/CMakeLists.txt

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@@ -66,6 +66,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCA95XX gpio_pca95xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL64XXA gpio_pcal64xxa.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RA8 gpio_renesas_ra8.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c)

‎drivers/gpio/Kconfig

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@@ -155,6 +155,7 @@ source "drivers/gpio/Kconfig.pcf857x"
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source "drivers/gpio/Kconfig.psoc6"
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source "drivers/gpio/Kconfig.rcar"
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source "drivers/gpio/Kconfig.renesas_ra"
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source "drivers/gpio/Kconfig.renesas_ra8"
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source "drivers/gpio/Kconfig.rpi_pico"
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source "drivers/gpio/Kconfig.rt1718s"
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source "drivers/gpio/Kconfig.rv32m1"

‎drivers/gpio/Kconfig.renesas_ra8

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_RA8
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bool "Renesas RA8 GPIO driver"
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default y
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depends on DT_HAS_RENESAS_RA8_GPIO_ENABLED
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help
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Enable the Renesas RA8 GPIO driver.

‎drivers/gpio/gpio_renesas_ra8.c

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra8_gpio
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/dt-bindings/gpio/renesas-ra8-gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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struct gpio_ra8_config {
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struct gpio_driver_config common;
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uint8_t port_num;
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R_PORT0_Type *port;
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gpio_pin_t vbatt_pins[];
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};
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struct gpio_ra8_data {
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struct gpio_driver_data common;
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};
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static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_ra8_config *config = dev->config;
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struct ra_pinctrl_soc_pin pincfg = {0};
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if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_PULL_DOWN) != 0U) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_INT_ENABLE) != 0) {
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return -ENOTSUP;
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}
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if (config->vbatt_pins[0] != 0xFF) {
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uint32_t clear = 0;
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for (int i = 0; config->vbatt_pins[i] != '\0'; i++) {
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if (config->vbatt_pins[i] == pin) {
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WRITE_BIT(clear, i, 1);
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}
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}
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
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R_SYSTEM->VBTICTLR &= (uint8_t)~clear;
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
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}
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pincfg.port_num = config->port_num;
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pincfg.pin_num = pin;
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/* Change mode to general IO mode and disable IRQ and Analog input */
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PMR_Pos, 0);
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ASEL_Pos, 0);
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0);
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if ((flags & GPIO_OUTPUT) != 0U) {
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/* Set output pin initial value */
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 0);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1);
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}
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1);
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} else {
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 0);
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}
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if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_NCODR_Pos, 1);
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}
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if ((flags & GPIO_PULL_UP) != 0) {
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WRITE_BIT(pincfg.cfg, R_PFS_PORT_PIN_PmnPFS_PCR_Pos, 1);
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}
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pincfg.cfg = pincfg.cfg |
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(((flags & RENESAS_GPIO_DS_MSK) >> 8) << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
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return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
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}
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static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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*value = port->PIDR;
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return 0;
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}
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static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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port->PODR = ((port->PODR & ~mask) | (value & mask));
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return 0;
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}
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static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
119+
const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR | pins);
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return 0;
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}
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static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
129+
const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR & ~pins);
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return 0;
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}
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static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
138+
{
139+
const struct gpio_ra8_config *config = dev->config;
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R_PORT0_Type *port = config->port;
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port->PODR = (port->PODR ^ pins);
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return 0;
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}
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static const struct gpio_driver_api gpio_ra8_drv_api_funcs = {
148+
.pin_configure = gpio_ra8_pin_configure,
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.port_get_raw = gpio_ra8_port_get_raw,
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.port_set_masked_raw = gpio_ra8_port_set_masked_raw,
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.port_set_bits_raw = gpio_ra8_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ra8_port_clear_bits_raw,
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.port_toggle_bits = gpio_ra8_port_toggle_bits,
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.pin_interrupt_configure = NULL,
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.manage_callback = NULL,
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};
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#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
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static const struct gpio_ra8_config gpio_ra8_config_##suffix = { \
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.common = \
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{ \
162+
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
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}, \
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.port_num = port_number, \
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.port = (R_PORT0_Type *)addr, \
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.vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \
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}; \
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static struct gpio_ra8_data gpio_ra8_data_##suffix; \
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DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra8_data_##suffix, \
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&gpio_ra8_config_##suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_ra8_drv_api_funcs)
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#define GPIO_DEVICE_INIT_RA8(suffix) \
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GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \
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DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \
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DT_REG_ADDR(DT_NODELABEL(ioport##suffix)))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay)
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GPIO_DEVICE_INIT_RA8(0);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay)
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GPIO_DEVICE_INIT_RA8(1);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay)
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GPIO_DEVICE_INIT_RA8(2);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay)
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GPIO_DEVICE_INIT_RA8(3);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay)
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GPIO_DEVICE_INIT_RA8(4);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay)
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GPIO_DEVICE_INIT_RA8(5);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay)
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GPIO_DEVICE_INIT_RA8(6);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay)
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GPIO_DEVICE_INIT_RA8(7);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay)
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GPIO_DEVICE_INIT_RA8(8);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay)
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GPIO_DEVICE_INIT_RA8(9);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay)
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GPIO_DEVICE_INIT_RA8(a);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay)
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GPIO_DEVICE_INIT_RA8(b);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) */

‎dts/arm/renesas/ra/ra8/ra8x1.dtsi

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@@ -68,6 +68,127 @@
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reg = <0x40400800 0x3c0>;
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status = "okay";
7070
};
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ioport0: gpio@40400000 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40400020 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40400040 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40400060 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40400080 {
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compatible = "renesas,ra8-gpio";
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reg = <0x40400080 0x20>;
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port = <4>;
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gpio-controller;
117+
#gpio-cells = <2>;
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ngpios = <16>;
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vbatts_pins = <2 3 4>;
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status = "disabled";
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};
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ioport5: gpio@404000a0 {
124+
compatible = "renesas,ra8-gpio";
125+
reg = <0x404000a0 0x20>;
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port = <5>;
127+
gpio-controller;
128+
#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport6: gpio@404000c0 {
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compatible = "renesas,ra8-gpio";
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reg = <0x404000c0 0x20>;
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port = <6>;
137+
gpio-controller;
138+
#gpio-cells = <2>;
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ngpios = <16>;
140+
status = "disabled";
141+
};
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ioport7: gpio@404000e0 {
144+
compatible = "renesas,ra8-gpio";
145+
reg = <0x404000e0 0x20>;
146+
port = <7>;
147+
gpio-controller;
148+
#gpio-cells = <2>;
149+
ngpios = <16>;
150+
status = "disabled";
151+
};
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153+
ioport8: gpio@40400100 {
154+
compatible = "renesas,ra8-gpio";
155+
reg = <0x40400100 0x20>;
156+
port = <8>;
157+
gpio-controller;
158+
#gpio-cells = <2>;
159+
ngpios = <16>;
160+
status = "disabled";
161+
};
162+
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ioport9: gpio@40400120 {
164+
compatible = "renesas,ra8-gpio";
165+
reg = <0x40400120 0x20>;
166+
port = <9>;
167+
gpio-controller;
168+
#gpio-cells = <2>;
169+
ngpios = <16>;
170+
status = "disabled";
171+
};
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173+
ioporta: gpio@40400140 {
174+
compatible = "renesas,ra8-gpio";
175+
reg = <0x40400140 0x20>;
176+
port = <10>;
177+
gpio-controller;
178+
#gpio-cells = <2>;
179+
ngpios = <16>;
180+
status = "disabled";
181+
};
182+
183+
ioportb: gpio@40400160 {
184+
compatible = "renesas,ra8-gpio";
185+
reg = <0x40400160 0x20>;
186+
port = <11>;
187+
gpio-controller;
188+
#gpio-cells = <2>;
189+
ngpios = <16>;
190+
status = "disabled";
191+
};
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};
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&nvic {

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