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soc: Add the MAX32657 SoC
MAX32657 is Cortex-M33 based Analog Devices MCU. It supports ARM TrustZone security model. There will be two boards of this MCU Secure and Non-Secure This commit defines Secure version of peripherals. Basic feature of MAX32657 device: - Core is Cortex-M33 - 50MHz IPO clock - There are 54 interrupt vectors - 1MB flash & 256 SRAM - MAX32657 has: - 1 x UART - 1 x I2C/I3C - 1 x SPI - 6 x TIMER - 1 x RTC - 1 x WDT - 1 x TRNG Signed-off-by: Sadik Ozer <[email protected]>
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‎dts/arm/adi/max32/max32657-pinctrl.dtsi‎

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/*
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* Copyright (c) 2024-2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
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&pinctrl {
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/omit-if-no-ref/ i3c_scl_p0_0: i3c_scl_p0_0 {
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pinmux = <MAX32_PINMUX(0, 0, AF1)>;
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};
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/omit-if-no-ref/ i3c_sda_p0_1: i3c_sda_p0_1 {
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pinmux = <MAX32_PINMUX(0, 1, AF1)>;
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};
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/omit-if-no-ref/ spi0_mosi_p0_2: spi0_mosi_p0_2 {
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pinmux = <MAX32_PINMUX(0, 2, AF1)>;
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};
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/omit-if-no-ref/ spi0_ss0_p0_3: spi0_ss0_p0_3 {
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pinmux = <MAX32_PINMUX(0, 3, AF1)>;
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};
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/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
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pinmux = <MAX32_PINMUX(0, 4, AF1)>;
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};
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/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
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pinmux = <MAX32_PINMUX(0, 5, AF1)>;
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};
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/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
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pinmux = <MAX32_PINMUX(0, 6, AF1)>;
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};
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/omit-if-no-ref/ spi0_ss1_p0_7: spi0_ss1_p0_7 {
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pinmux = <MAX32_PINMUX(0, 7, AF1)>;
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};
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/omit-if-no-ref/ spi0_ss2_p0_8: spi0_ss2_p0_8 {
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pinmux = <MAX32_PINMUX(0, 8, AF1)>;
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};
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/omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 {
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pinmux = <MAX32_PINMUX(0, 9, AF1)>;
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};
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/omit-if-no-ref/ sqwout_p0_13: sqwout_p0_13 {
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pinmux = <MAX32_PINMUX(0, 13, AF1)>;
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};
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/omit-if-no-ref/ tmr0a_p0_0: tmr0a_p0_0 {
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pinmux = <MAX32_PINMUX(0, 0, AF2)>;
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};
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/omit-if-no-ref/ tmr1a_p0_1: tmr1a_p0_1 {
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pinmux = <MAX32_PINMUX(0, 1, AF2)>;
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};
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/omit-if-no-ref/ tmr3a_p0_2: tmr3a_p0_2 {
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pinmux = <MAX32_PINMUX(0, 2, AF2)>;
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};
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/omit-if-no-ref/ tmr4a_p0_3: tmr4a_p0_3 {
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pinmux = <MAX32_PINMUX(0, 3, AF2)>;
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};
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/omit-if-no-ref/ tmr5a_p0_4: tmr5a_p0_4 {
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pinmux = <MAX32_PINMUX(0, 4, AF2)>;
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};
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/omit-if-no-ref/ tmr0b_p0_5: tmr0b_p0_5 {
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pinmux = <MAX32_PINMUX(0, 5, AF2)>;
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};
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/omit-if-no-ref/ tmr4b_p0_6: tmr4b_p0_6 {
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pinmux = <MAX32_PINMUX(0, 6, AF2)>;
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};
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/omit-if-no-ref/ tmr3b_p0_7: tmr3b_p0_7 {
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pinmux = <MAX32_PINMUX(0, 7, AF2)>;
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};
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/omit-if-no-ref/ i3c_pur_p0_8: i3c_pur_p0_8 {
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pinmux = <MAX32_PINMUX(0, 8, AF2)>;
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};
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/omit-if-no-ref/ tmr1b_p0_9: tmr1b_p0_9 {
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pinmux = <MAX32_PINMUX(0, 9, AF2)>;
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};
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/omit-if-no-ref/ tmr2a_p0_10: tmr2a_p0_10 {
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pinmux = <MAX32_PINMUX(0, 10, AF2)>;
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};
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/omit-if-no-ref/ tmr5b_p0_11: tmr5b_p0_11 {
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pinmux = <MAX32_PINMUX(0, 11, AF2)>;
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};
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};

‎dts/arm/adi/max32/max32657.dtsi‎

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/*
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* Copyright (c) 2024-2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/adi_max32_clock.h>
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/ {
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soc {
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sram: sram@30000000 {
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ranges = <0x0 0x30000000 0x40000>;
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};
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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pinctrl: pin-controller@8000 {
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ranges = <0x8000 0x50008000 0x1000>;
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};
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flc0: flash_controller@29000 {
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compatible = "adi,max32-flash-controller";
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reg = <0x29000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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flash0: flash@1000000 {
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compatible = "soc-nv-flash";
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reg = <0x01000000 DT_SIZE_K(1024)>;
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write-block-size = <16>;
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erase-block-size = <8192>;
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};
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};
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};
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};
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};
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#include "max32657_common.dtsi"

‎dts/arm/adi/max32/max32657_common.dtsi‎

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/*
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* Copyright (c) 2024-2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <mem.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flc0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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clocks {
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clk_ipo: clk_ipo {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(50)>;
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status = "disabled";
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};
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clk_inro: clk_inro {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = < DT_FREQ_K(8) >;
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status = "disabled";
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};
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clk_ibro: clk_ibro {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = < 7372800 >;
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status = "disabled";
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};
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clk_ertco: clk_ertco {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = < 32768 >;
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status = "disabled";
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};
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clk_erfo: clk_erfo {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(32)>;
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status = "disabled";
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};
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};
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};
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&sram {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0x0 DT_SIZE_K(32)>;
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};
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sram1: memory@8000 {
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compatible = "mmio-sram";
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reg = <0x8000 DT_SIZE_K(32)>;
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};
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sram2: memory@10000 {
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compatible = "mmio-sram";
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reg = <0x10000 DT_SIZE_K(64)>;
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};
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sram3: memory@20000 {
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compatible = "mmio-sram";
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reg = <0x20000 DT_SIZE_K(64)>;
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};
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sram4: memory@30000 {
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compatible = "mmio-sram";
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reg = <0x30000 DT_SIZE_K(64)>;
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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gcr: clock-controller@0 {
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reg = <0x0 0x400>;
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compatible = "adi,max32-gcr";
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#clock-cells = <2>;
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clocks = <&clk_ipo>;
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sysclk-prescaler = <1>;
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status = "okay";
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};
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pinctrl: pin-controller@8000 {
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compatible = "adi,max32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8000 0x1000>;
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gpio0: gpio@8000 {
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reg = <0x8000 0x1000>;
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compatible = "adi,max32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>;
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interrupts = <14 0>;
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status = "disabled";
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};
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};
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uart0: serial@42000 {
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compatible = "adi,max32-uart";
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reg = <0x42000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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interrupts = <11 0>;
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

‎soc/adi/max32/Kconfig‎

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select SOC_EARLY_INIT_HOOK
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
1111

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config SOC_FAMILY_MAX32_M33
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select ARM
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select CLOCK_CONTROL
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select CPU_CORTEX_M33
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select ARM_TRUSTZONE_M
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select CPU_HAS_ARM_SAU
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select ARMV8_M_DSP
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config SOC_FAMILY_MAX32_M4
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select ARM
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select CPU_CORTEX_M4

‎soc/adi/max32/Kconfig.defconfig.max32657‎

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# Analog Devices MAX32657 MCU
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# Copyright (c) 2024-2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MAX32657
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
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config NUM_IRQS
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default 54
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endif # SOC_MAX32657

‎soc/adi/max32/Kconfig.soc‎

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config SOC_FAMILY_MAX32
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bool
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config SOC_FAMILY_MAX32_M33
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bool
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select SOC_FAMILY_MAX32
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config SOC_FAMILY_MAX32_M4
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bool
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select SOC_FAMILY_MAX32
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select SOC_MAX32655
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select SOC_FAMILY_MAX32_M4
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config SOC_MAX32657
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bool
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select SOC_FAMILY_MAX32_M33
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config SOC_MAX32660
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bool
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select SOC_FAMILY_MAX32_M4
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config SOC
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default "max32650" if SOC_MAX32650
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default "max32655" if SOC_MAX32655
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default "max32657" if SOC_MAX32657
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default "max32660" if SOC_MAX32660
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default "max32662" if SOC_MAX32662
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default "max32666" if SOC_MAX32666

‎soc/adi/max32/soc.yml‎

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- name: max32655
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cpuclusters:
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- name: m4
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- name: max32657
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- name: max32660
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- name: max32662
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- name: max32666

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