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boards: renesas: Add minimal support for board RZ/A3M-EK
This adds minimal support for board RZ/A3M-EK Signed-off-by: Nhut Nguyen <[email protected]>
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‎boards/renesas/rza3m_ek/Kconfig.rza3m_ek

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_RZA3M_EK
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select SOC_R9A07G066M04GBG

‎boards/renesas/rza3m_ek/board.cmake

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=R9A07G066M04")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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if(CONFIG_BUILD_WITH_RZA_IPL)
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set(RZA_PLAT a3m)
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set(RZA_BOARD a3m_ek_nor)
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endif()

‎boards/renesas/rza3m_ek/board.yml

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board:
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name: rza3m_ek
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full_name: RZ/A3M Evaluation Kit
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vendor: renesas
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socs:
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- name: r9a07g066m04gbg

‎boards/renesas/rza3m_ek/doc/index.rst

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.. zephyr:board:: rza3m_ek
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Overview
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********
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The EK-RZ/A3M evaluation kit enables users to easily evaluate the features of the RZ/A3M MPU.
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This kit includes an EK-RZ/A3M board, 5-inch 720x1280 pixel LCD MIPI graphics expansion board, and
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USB cables, allowing the seamless evaluation of high-definition human machine interface (HMI), camera
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input through USB, and more features. Equipped with an on-board J-Link debugger, users can
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conveniently start debugging without additional debuggers.
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Additionally, it also has several expansion connectors such as SDIO, PMOD,and Arduino to connect
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sensors, Wi-Fi, and Bluetooth® Low Energy (LE), allowing users to add more features without
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expanding the board space.
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* Special Feature Access
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* MIPI DSI 4 lanes & parallel graphics expansion ports
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* 5-inch MIPI LCD panel (720x1280 pixels)
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* USB High-Speed Host & Device
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* 32MB External QSPI NOR Flash
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* 128MB External QSPI NAND Flash
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* External sound codec
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* External RTC
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* MPU Native Pin Access
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* R9A07G066M04GBG MPU
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* 1GHz, Arm Cortex®-A55 core w/NEON extension
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* Built-in 128MB DDR3L DRAM
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* 128KB SRAM w/ECC
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* 244 pins, BGA package
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* Native pin access
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* MPU & USB current measurement
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* Ecosystem & System Control Access
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* USB High-Speed Host & Device
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* 5V input through USB (Debug, HS, USB-PD) or external power supply
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* Debug on-board (Segger J-Link®)
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* Debug external (SWD & JTAG)
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* SCIF download (SWD)
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* 3 user LEDs & 2 user buttons
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* 2 SeeedGrove® system (I2C & analog)
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* 2 Digilent Pmod™ (I2C, SPI or UART selectable)
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* Arduino™ (Uno R3)
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* MikroElektronika™ mikroBUS
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* SparkFun® Qwiic® (I2C)
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* MPU boot configuration switch
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* Audio In/Out 4-pole
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* MicroSD card slot
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* Kit Contents
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* EK-RZ/A3M board
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* MIPI graphics expansion board
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* USB cable (USB C to USB C)
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* USB cable (USB A female to USB C)
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* USB cable (USB A male to USB C)
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* Screw and spacer for fixing the sub board
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Hardware
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********
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The Renesas RZ/A3M MPU documentation can be found at `RZ/A3M Group Website`_
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.. figure:: rza3m_block_diagram.webp
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:width: 600px
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:align: center
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:alt: RZ/A3M group feature
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RZ/A3M block diagram (Credit: Renesas Electronics Corporation)
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Detailed hardware features for the board can be found at `EK-RZ/A3M Website`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Programming and Debugging
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*************************
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EK-RZ/A3M uses Initial Program Loader (IPL) to perform initial settings and copy the Zephyr image from flash to DDR SRAM for execution.
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It only needs to be written to flash at lease once before running Zephyr.
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1. For the board setup and connections, follow "3.2 Board Setup" of `Getting Started with RZ/A Flexible Software Package`_.
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2. Enable the IPL build with ``-DCONFIG_BUILD_WITH_RZA_IPL=y``.
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The IPL image ``rza3m_ek_nor_ipl.bin`` is generated under zephyrproject/zephyr/build/rza_ipl/a3m/release
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: rza3m_ek
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:goals: build
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:gen-args: -DCONFIG_BUILD_WITH_RZA_IPL=y
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.. note::
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Currently, the IPL source code can built on Linux environment only.
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For Windows, please follow `Initial Program Loader Application Note`_
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3. Flash it onto the board at address 0x20000000 by Jlink command `Segger JLink Renesas R9A07G066`_
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.. code-block:: console
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$ JLinkExe
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J-Link> connect
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Device> R9A07G066M04
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TIF> s
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Speed> [Enter]
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J-Link> h
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J-Link> loadfile <ipl_bin_path> 0x20000000
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Where ``<ipl_bin_path>`` is the path to the ``rza3m_ek_nor_ipl.bin`` in the output directory.
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Applications for the ``rza3m_ek`` board can be built in the usual way as
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documented in :ref:`build_an_application`.
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Console
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=======
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The UART port is accessed by USB Debug connector (J10).
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Debugging
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=========
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It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core
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from the DDR SDRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
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Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: rza3m_ek
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:goals: build debug
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Flashing
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========
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Zephyr application can be flashed to Quad-SPI storage and then loaded by Initial Program Loader.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: rza3m_ek
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:goals: build flash
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References
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**********
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.. target-notes::
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.. _RZ/A3M Group Website:
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https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3m-powerful-1ghz-mpus-built-ddr3l-sdram-high-definition-hmi
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.. _EK-RZ/A3M Website:
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https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/ek-rza3m-evaluation-kit-rza3m-mpu
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.. _Initial Program Loader Application Note:
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https://github.com/renesas/rza-initial-program-loader/tree/main/application_note
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.. _Getting Started with RZ/A Flexible Software Package:
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https://www.renesas.com/en/document/apn/rza-getting-started-flexible-software-package
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.. _Segger JLink Renesas R9A07G066:
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https://kb.segger.com/Renesas_R9A07G066

‎boards/renesas/rza3m_ek/doc/rza3m_block_diagram.webp

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‎boards/renesas/rza3m_ek/doc/rza3m_ek.webp

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‎boards/renesas/rza3m_ek/rza3m_ek.dts

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
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#include <freq.h>
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#include <arm64/renesas/rz/rza/r9a07g066.dtsi>
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#include "rza3m_ek-pinctrl.dtsi"
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/ {
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model = "Renesas RZ/A3M EK";
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compatible = "renesas,rza3m-ek";
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chosen {
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zephyr,sram = &ddr;
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zephyr,flash = &spi_flash;
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zephyr,console = &scif0;
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zephyr,shell-uart = &scif0;
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zephyr,code-partition= &slot0_partition;
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};
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ddr: memory@40200000 {
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compatible ="zephyr,memory-region", "mmio-sram";
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reg = <0x40200000 (DT_SIZE_M(128) - 0x200000)>;
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zephyr,memory-region = "DDR";
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};
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sram: memory@1e000 {
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compatible ="zephyr,memory-region", "mmio-sram";
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reg = <0x1e000 DT_SIZE_K(72)>;
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zephyr,memory-region = "SRAM";
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};
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spi_flash: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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header: partition@0 {
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label = "header";
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reg = <0x00000000 0x200>;
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read-only;
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};
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slot0_partition: partition@200 {
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label = "image-0";
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reg = <0x00000200 (DT_SIZE_M(16) - 0x20200)>;
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read-only;
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};
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};
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};
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aliases {
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led0 = &led1;
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sw0 = &sw1;
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};
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leds {
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compatible = "gpio-leds";
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led1: led1 {
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gpios = <&gpio10 1 GPIO_ACTIVE_HIGH>;
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label = "led1";
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};
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led2: led2 {
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gpios = <&gpio20 3 GPIO_ACTIVE_HIGH>;
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label = "led2";
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};
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led3: led3 {
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gpios = <&gpio20 4 GPIO_ACTIVE_HIGH>;
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label = "led3";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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sw1: sw1 {
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label = "sw1";
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gpios = <&gpio10 3 GPIO_ACTIVE_HIGH>;
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zephyr,code = <INPUT_KEY_0>;
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};
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sw2: sw2 {
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label = "sw2";
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gpios = <&gpio11 1 GPIO_ACTIVE_HIGH>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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};
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&scif0 {
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current-speed = <115200>;
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gpio {
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status = "okay";
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};
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&gpio10 {
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status = "okay";
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};
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&gpio11 {
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status = "okay";
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};
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&gpio20 {
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status = "okay";
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};

‎boards/renesas/rza3m_ek/rza3m_ek.yaml

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identifier: rza3m_ek
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name: Renesas RZ/A3M Evaluation Kit
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type: mcu
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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supported:
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- uart
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- gpio
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testing:
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ignore_tags:
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- bluetooth

‎boards/renesas/rza3m_ek/rza3m_ek_defconfig

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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# MMU Options
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CONFIG_MAX_XLAT_TABLES=24
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# Cache Options
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_DCACHE_LINE_SIZE_DETECT=y
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CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y

‎modules/Kconfig.renesas

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help
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Enable RZ FSP SCI UART driver
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menuconfig BUILD_WITH_RZA_IPL
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bool "Build with RZ/A Initial Program Loader (IPL)"
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help
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When enabled, this option instructs the Zephyr build process to
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additionally generate IPL image for Renesas RZ/A series.
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if BUILD_WITH_RZA_IPL
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config RZA_IPL_BUILD_DEBUG
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bool "Debug build"
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help
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When enabled, the build type of IPL would be debug.
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endif # BUILD_WITH_RZA_IPL
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endif
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270285
config HAS_RENESAS_RX_RDP

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