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soc: renesas: Add power management support for Renesas RA8
Updated `CMakeLists.txt` and `Kconfig` to integrate power management for RA8D1, RA8M1, and RA8T1. Modified `Kconfig.defconfig` to configure ULPT timer as the system timer when power management is enabled: - Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC` for ULPT timer. - Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer. Implemented power management logic in the new `power.c` file for: - RA8D1 (`soc/renesas/ra/ra8d1/power.c`) - RA8M1 (`soc/renesas/ra/ra8m1/power.c`) - RA8T1 (`soc/renesas/ra/ra8t1/power.c`) Signed-off-by: Khanh Nguyen <[email protected]>
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‎soc/renesas/ra/ra8d1/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ zephyr_sources(
77
soc.c
88
)
99

10+
zephyr_sources_ifdef(CONFIG_PM
11+
power.c
12+
)
13+
1014
zephyr_linker_sources(SECTIONS sections.ld)
1115

1216
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra8d1/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -15,3 +15,4 @@ config SOC_SERIES_RA8D1
1515
select HAS_RENESAS_RA_FSP
1616
select SOC_EARLY_INIT_HOOK
1717
select GPIO_RA_HAS_VBTICTLR
18+
select HAS_PM

‎soc/renesas/ra/ra8d1/Kconfig.defconfig

Lines changed: 16 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,6 @@ if SOC_SERIES_RA8D1
66
config NUM_IRQS
77
default 96
88

9-
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
10-
11-
config SYS_CLOCK_HW_CYCLES_PER_SEC
12-
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
13-
149
config BUILD_OUTPUT_HEX
1510
default y
1611

@@ -27,4 +22,20 @@ config DCACHE
2722
config CACHE_MANAGEMENT
2823
default n
2924

25+
config CORTEX_M_SYSTICK
26+
default n if RENESAS_RA_ULPT_TIMER
27+
28+
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
29+
DT_LOCO_PATH := $(dt_nodelabel_path,loco)
30+
31+
config SYS_CLOCK_HW_CYCLES_PER_SEC
32+
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
33+
default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
34+
35+
config SYS_CLOCK_TICKS_PER_SEC
36+
default 4096 if RENESAS_RA_ULPT_TIMER
37+
38+
config PM_DEVICE
39+
default y if PM
40+
3041
endif # SOC_SERIES_RA8D1

‎soc/renesas/ra/ra8d1/power.c

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
/*
2+
* Copyright (c) 2025 Renesas Electronics Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/kernel.h>
8+
#include <zephyr/pm/pm.h>
9+
#include <zephyr/init.h>
10+
#include <soc.h>
11+
#include <r_lpm.h>
12+
13+
#include <zephyr/logging/log.h>
14+
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
15+
16+
/* Low Power Mode instance control structure */
17+
static lpm_instance_ctrl_t pm_state_ctrl;
18+
19+
/* Configuration for Runtime Idle Power State */
20+
const lpm_cfg_t pm_state_runtime_idle_cfg = {
21+
.low_power_mode = LPM_MODE_SLEEP,
22+
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
23+
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
24+
.io_port_state = LPM_IO_PORT_NO_CHANGE,
25+
.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
26+
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
27+
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
28+
.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
29+
.ram_retention_cfg.tcm_retention = true,
30+
.ram_retention_cfg.standby_ram_retention = true,
31+
.ldo_standby_cfg.pll1_ldo = false,
32+
.ldo_standby_cfg.pll2_ldo = false,
33+
.ldo_standby_cfg.hoco_ldo = false,
34+
.p_extend = NULL,
35+
};
36+
37+
/* Configuration for Standby Power State */
38+
const lpm_cfg_t pm_state_standby_cfg = {
39+
.low_power_mode = LPM_MODE_STANDBY,
40+
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
41+
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
42+
.io_port_state = LPM_IO_PORT_NO_CHANGE,
43+
.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
44+
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
45+
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
46+
.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
47+
.ram_retention_cfg.tcm_retention = true,
48+
.ram_retention_cfg.standby_ram_retention = true,
49+
.ldo_standby_cfg.pll1_ldo = false,
50+
.ldo_standby_cfg.pll2_ldo = false,
51+
.ldo_standby_cfg.hoco_ldo = false,
52+
.p_extend = NULL,
53+
};
54+
55+
void pm_state_set(enum pm_state state, uint8_t substate_id)
56+
{
57+
switch (state) {
58+
case PM_STATE_RUNTIME_IDLE:
59+
R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
60+
__disable_irq();
61+
__set_BASEPRI(0);
62+
__ISB();
63+
64+
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
65+
__enable_irq();
66+
__ISB();
67+
break;
68+
69+
case PM_STATE_STANDBY:
70+
R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
71+
__disable_irq();
72+
__set_BASEPRI(0);
73+
__ISB();
74+
75+
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
76+
__enable_irq();
77+
__ISB();
78+
break;
79+
80+
default:
81+
break;
82+
}
83+
}
84+
85+
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
86+
{
87+
switch (state) {
88+
case PM_STATE_RUNTIME_IDLE:
89+
__fallthrough;
90+
case PM_STATE_STANDBY:
91+
R_LPM_Close(&pm_state_ctrl);
92+
break;
93+
94+
default:
95+
break;
96+
}
97+
irq_unlock(0);
98+
}

‎soc/renesas/ra/ra8m1/CMakeLists.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ zephyr_sources(
77
soc.c
88
)
99

10+
zephyr_sources_ifdef(CONFIG_PM
11+
power.c
12+
)
13+
1014
zephyr_linker_sources(SECTIONS sections.ld)
1115

1216
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra8m1/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -15,5 +15,6 @@ config SOC_SERIES_RA8M1
1515
select HAS_RENESAS_RA_FSP
1616
select SOC_EARLY_INIT_HOOK
1717
select GPIO_RA_HAS_VBTICTLR
18+
select HAS_PM
1819
help
1920
Enable support for Renesas RA8M1 MCU series

‎soc/renesas/ra/ra8m1/Kconfig.defconfig

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,11 @@
1-
# Copyright (c) 2024 Renesas Electronics Corporation
1+
# Copyright (c) 2024-2025 Renesas Electronics Corporation
22
# SPDX-License-Identifier: Apache-2.0
33

44
if SOC_SERIES_RA8M1
55

66
config NUM_IRQS
77
default 96
88

9-
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
10-
11-
config SYS_CLOCK_HW_CYCLES_PER_SEC
12-
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
13-
149
config BUILD_OUTPUT_HEX
1510
default y
1611

@@ -21,4 +16,20 @@ config CLOCK_CONTROL
2116
config FLASH_FILL_BUFFER_SIZE
2217
default 128
2318

19+
config CORTEX_M_SYSTICK
20+
default n if RENESAS_RA_ULPT_TIMER
21+
22+
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
23+
DT_LOCO_PATH := $(dt_nodelabel_path,loco)
24+
25+
config SYS_CLOCK_HW_CYCLES_PER_SEC
26+
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
27+
default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
28+
29+
config SYS_CLOCK_TICKS_PER_SEC
30+
default 4096 if RENESAS_RA_ULPT_TIMER
31+
32+
config PM_DEVICE
33+
default y if PM
34+
2435
endif # SOC_SERIES_RA8M1

‎soc/renesas/ra/ra8m1/power.c

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
/*
2+
* Copyright (c) 2025 Renesas Electronics Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/kernel.h>
8+
#include <zephyr/pm/pm.h>
9+
#include <zephyr/init.h>
10+
#include <soc.h>
11+
#include <r_lpm.h>
12+
13+
#include <zephyr/logging/log.h>
14+
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
15+
16+
/* Low Power Mode instance control structure */
17+
static lpm_instance_ctrl_t pm_state_ctrl;
18+
19+
/* Configuration for Runtime Idle Power State */
20+
const lpm_cfg_t pm_state_runtime_idle_cfg = {
21+
.low_power_mode = LPM_MODE_SLEEP,
22+
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
23+
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
24+
.io_port_state = LPM_IO_PORT_NO_CHANGE,
25+
.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
26+
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
27+
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
28+
.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
29+
.ram_retention_cfg.tcm_retention = true,
30+
.ram_retention_cfg.standby_ram_retention = true,
31+
.ldo_standby_cfg.pll1_ldo = false,
32+
.ldo_standby_cfg.pll2_ldo = false,
33+
.ldo_standby_cfg.hoco_ldo = false,
34+
.p_extend = NULL,
35+
};
36+
37+
/* Configuration for Standby Power State */
38+
const lpm_cfg_t pm_state_standby_cfg = {
39+
.low_power_mode = LPM_MODE_STANDBY,
40+
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
41+
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
42+
.io_port_state = LPM_IO_PORT_NO_CHANGE,
43+
.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
44+
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
45+
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
46+
.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
47+
.ram_retention_cfg.tcm_retention = true,
48+
.ram_retention_cfg.standby_ram_retention = true,
49+
.ldo_standby_cfg.pll1_ldo = false,
50+
.ldo_standby_cfg.pll2_ldo = false,
51+
.ldo_standby_cfg.hoco_ldo = false,
52+
.p_extend = NULL,
53+
};
54+
55+
void pm_state_set(enum pm_state state, uint8_t substate_id)
56+
{
57+
switch (state) {
58+
case PM_STATE_RUNTIME_IDLE:
59+
R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
60+
__disable_irq();
61+
__set_BASEPRI(0);
62+
__ISB();
63+
64+
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
65+
__enable_irq();
66+
__ISB();
67+
break;
68+
69+
case PM_STATE_STANDBY:
70+
R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
71+
__disable_irq();
72+
__set_BASEPRI(0);
73+
__ISB();
74+
75+
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
76+
__enable_irq();
77+
__ISB();
78+
break;
79+
80+
default:
81+
break;
82+
}
83+
}
84+
85+
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
86+
{
87+
switch (state) {
88+
case PM_STATE_RUNTIME_IDLE:
89+
__fallthrough;
90+
case PM_STATE_STANDBY:
91+
R_LPM_Close(&pm_state_ctrl);
92+
break;
93+
94+
default:
95+
break;
96+
}
97+
irq_unlock(0);
98+
}

‎soc/renesas/ra/ra8t1/CMakeLists.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,10 @@ zephyr_sources(
77
soc.c
88
)
99

10+
zephyr_sources_ifdef(CONFIG_PM
11+
power.c
12+
)
13+
1014
zephyr_linker_sources(SECTIONS sections.ld)
1115

1216
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra8t1/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,3 +15,4 @@ config SOC_SERIES_RA8T1
1515
select HAS_RENESAS_RA_FSP
1616
select SOC_EARLY_INIT_HOOK
1717
select GPIO_RA_HAS_VBTICTLR
18+
select HAS_PM

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