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dts: arm: st: n6: add dtsi for stm32n6 series
Add dtsi files for STM32N6 series Signed-off-by: Guillaume Gautier <[email protected]>
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‎dts/arm/st/n6/stm32n6.dtsi

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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8.1-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
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#include <zephyr/dt-bindings/reset/stm32n6_reset.h>
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#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m55";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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axisram1: memory@34000000 {
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compatible = "mmio-sram";
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};
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axisram2: memory@34180400 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32n6-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "st,stm32h7-hsi-clock";
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clock-frequency = <DT_FREQ_M(64)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <2>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32n6-pll-clock";
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status = "disabled";
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};
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pll2: pll2 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-pll-clock";
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status = "disabled";
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};
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pll3: pll3 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-pll-clock";
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status = "disabled";
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};
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pll4: pll4 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-pll-clock";
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status = "disabled";
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};
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cpusw: cpusw {
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#clock-cells = <0>;
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compatible = "st,stm32n6-cpu-clock-mux", "st,stm32-clock-mux";
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status = "disabled";
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};
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perck: perck {
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#clock-cells = <0>;
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compatible = "st,stm32-clock-mux";
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status = "disabled";
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};
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ic1: ic1 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic2: ic2 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic3: ic3 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic4: ic4 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic5: ic5 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic6: ic6 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic7: ic7 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic8: ic8 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic9: ic9 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic10: ic10 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic11: ic11 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic12: ic12 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic13: ic13 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic14: ic14 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic15: ic15 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic16: ic16 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic17: ic17 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic18: ic18 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic19: ic19 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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ic20: ic20 {
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#clock-cells = <0>;
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compatible = "st,stm32n6-ic-clock-mux";
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status = "disabled";
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};
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};
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soc {
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rcc: rcc@56028000 {
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compatible = "st,stm32n6-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x56028000 0x2000>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@56025000 {
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compatible = "st,stm32g0-exti", "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x56025000 0x400>;
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num-lines = <16>;
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interrupts = <20 0>, <21 0>, <22 0>, <23 0>,
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<24 0>, <25 0>, <26 0>, <27 0>,
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<28 0>, <29 0>, <30 0>, <31 0>,
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<32 0>, <33 0>, <34 0>, <35 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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pinctrl: pin-controller@56020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x56020000 0x2000>;
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gpioa: gpio@56020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56020000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
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};
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gpiob: gpio@56020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56020400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
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};
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gpioc: gpio@56020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56020800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
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};
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gpiod: gpio@56020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56020c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
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};
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gpioe: gpio@56021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56021000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
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};
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gpiof: gpio@56021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56021400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
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};
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gpiog: gpio@56021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56021800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
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};
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gpioh: gpio@56021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56021c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
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};
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gpion: gpio@56023400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56023400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 13)>;
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};
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gpioo: gpio@56023800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56023800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 14)>;
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};
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gpiop: gpio@56023c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56023C00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 15)>;
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};
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gpioq: gpio@56024000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x56024000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB4, 16)>;
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};
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};
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usart1: serial@52001000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x52001000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 4)>;
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resets = <&rctl STM32_RESET(APB2, 4)>;
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interrupts = <159 0>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};

‎dts/arm/st/n6/stm32n657.dtsi

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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/n6/stm32n6.dtsi>
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/ {
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soc {
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compatible = "st,stm32n657", "st,stm32n6", "simple-bus";
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};
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};

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