dts: rtc: sam0: Add clock properties

Add properties to differentiate the timer counter operating modes. This
properties are necessary to spetialize the driver to be used as a normal
16/32-bit counter or to provide the clock/calendar functions.

Signed-off-by: Gerson Fernando Budke <[email protected]>

Author: nandojve

drivers/timer/Kconfig.sam0_rtc

@@ -1,12 +1,14 @@
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # Copyright (c) 2019 Intel Corp.
+# Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
 # SPDX-License-Identifier: Apache-2.0
 
 config SAM0_RTC_TIMER
 	bool "Atmel SAM0 series RTC timer"
 	default y
-	depends on DT_HAS_ATMEL_SAM0_RTC_ENABLED
+	depends on DT_HAS_ATMEL_SAM0_RTC_ENABLED \
+		&& $(dt_nodelabel_bool_prop,rtc,systimer)
 	select PINCTRL
 	select TICKLESS_CAPABLE
 	help

dts/arm/atmel/samc2x.dtsi

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022 Kamil Serwus
- * Copyright (c) 2024 Gerson Fernando Budke <[email protected]>
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,8 @@
 		port-b = &portb;
 		port-c = &portc;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -274,6 +276,9 @@
 			atmel,assigned-clocks = <&osc32kctrl 0>;
 			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
+
+			alarms-count = <1>;
+			cal-constant = <(4096 * 240)>;
 		};
 	};
 };

dts/arm/atmel/samd2x.dtsi

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017 Google LLC.
- * Copyright (c) 2024 Gerson Fernando Budke <[email protected]>
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +19,8 @@
 		port-a = &porta;
 		port-b = &portb;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -189,7 +191,12 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40001400 0x1C>;
 			interrupts = <3 0>;
+			clocks = <&gclk 4 4>, <&pm 0x18 5>;
+			clock-names = "GCLK", "PM";
 			status = "disabled";
+
+			alarms-count = <1>;
+			cal-constant = <(1024 * 976)>;
 		};
 
 		adc: adc@42004000 {

dts/arm/atmel/samd5x.dtsi

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019 ML!PA Consulting GmbH
- * Copyright (c) 2024 Gerson Fernando Budke <[email protected]>
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,8 @@
 		port-c = &portc;
 		port-d = &portd;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -45,6 +47,7 @@
 	};
 
 	chosen {
+		zephyr,flash-controller = &nvmctrl;
 		zephyr,entropy = &trng;
 		zephyr,flash-controller = &nvmctrl;
 	};
@@ -331,6 +334,9 @@
 			atmel,assigned-clocks = <&osc32kctrl 0>;
 			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
+
+			alarms-count = <2>;
+			cal-constant = <(8192 * 128)>;
 		};
 
 		adc0: adc@43001c00 {

dts/arm/atmel/saml2x.dtsi

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
- * Copyright (c) 2024 Gerson Fernando Budke <[email protected]>
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,8 @@
 		sercom-4 = &sercom4;
 		sercom-5 = &sercom5;
 
+		rtc = &rtc;
+
 		tc-4 = &tc4;
 
 		watchdog0 = &wdog;
@@ -203,6 +205,9 @@
 			atmel,assigned-clocks = <&osc32kctrl 0>;
 			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
+
+			alarms-count = <1>;
+			cal-constant = <(8192 * 128)>;
 		};
 
 		adc: adc@43000c00 {

dts/bindings/rtc/atmel,sam0-rtc.yaml

@@ -1,13 +1,13 @@
 # Copyright (c) 2018 omSquare s.r.o.
-# Copyright (c) 2024 Gerson Fernando Budke <[email protected]>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <[email protected]>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 RTC
 
 compatible: "atmel,sam0-rtc"
 
 include:
-  - name: rtc.yaml
+  - name: rtc-device.yaml
   - name: pinctrl-device.yaml
   - name: atmel,assigned-clocks.yaml
 
@@ -26,3 +26,105 @@ properties:
 
   atmel,assigned-clock-names:
     required: true
+
+  systimer:
+    type: boolean
+    description: |
+      Selects RTC peripheral to be used as a system timer and replace
+      the ARM systick. When this option is selected the normal RTC
+      functionality is in exclusive mode and the normal RTC functions
+      will not be available.
+
+      The systimer exclusive functionality can be enabled using the
+      following devicetree entry:
+
+        &rtc {
+          status = "okay";
+          systimer;
+        };
+
+  cal-constant:
+    type: int
+    required: true
+    description: |
+      Define the constant used to calculate the calibration. More
+      information can be found in the datasheet of each SoC series
+      at RTC Frequency Correction topic.
+
+      Example:
+        Correction in ppm = (FREQCORR.VALUE * 1e6 ppm) / (8192 * 128)
+
+        &rtc {
+          cal-constant = <8192 * 128>;
+        };
+
+  counter-mode:
+    type: string
+    enum:
+      - "count-32"
+      - "count-16"
+      - "clock"
+    description: |
+      Configure the RTC counter operating mode. In mode 0, the counter
+      register is configured as a 32-bit counter. In mode 1, simmilar
+      to mode 0, the counter register is only 16-bit counter. In mode
+      2 the counter register is configured as a clock/calendar.
+
+        &rtc {
+          status = "okay";
+          counter-mode = "clock";
+          prescaler = <1024>;
+        };
+
+  prescaler:
+    type: int
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+      - 256
+      - 512
+      - 1024
+    description: |
+      Enable CLKOUT at given frequency. When disabled, CLKOUT pin is LOW.
+      The default is 0 and corresponds to the disable the CLKOUT signal.
+
+        &rtc {
+          status = "okay";
+          counter-mode = "clock";
+          prescaler = <1024>;
+        };
+
+  event-control-msk:
+    type: int
+    default: 0
+    description: |
+      Enable peripheral event sources by bitmask. By default all the channels
+      are always disabled.
+
+      Event Table:
+
+        bit   Event Source
+         0    Periodic Interval 0 Event Output
+         1    Periodic Interval 1 Event Output
+         2    Periodic Interval 2 Event Output
+         3    Periodic Interval 3 Event Output
+         4    Periodic Interval 4 Event Output
+         5    Periodic Interval 5 Event Output
+         6    Periodic Interval 6 Event Output
+         7    Periodic Interval 7 Event Output
+         8    Compare/Alarm 0 Event Output
+         9    Compare/Alarm 1 Event Output
+        14    Tamper Event Output
+        15    Overflow Event Output
+        16    Tamper Event Input
+
+      Example how to enable Compare/Alarm 0 Event Output:
+        &rtc {
+          event-control-msk = <100>;
+        };