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adsp: dmic: Moved registers definitions to a separate file
Moved dmic register definitions to a separate file dmic_regs.h and added their description. Platform-dependent registers definitions are placed in separate files. Used standard macros FIELD_PREP, FIELD_GET in operations on registers. Signed-off-by: Adrian Warecki <[email protected]>
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6 files changed

+742
-511
lines changed

6 files changed

+742
-511
lines changed

‎drivers/dai/intel/dmic/dmic.c

Lines changed: 63 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
2222
#include <zephyr/irq.h>
2323

2424
#include "dmic.h"
25+
#include "dmic_regs.h"
2526

2627
/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
2728
static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3};
@@ -139,14 +140,14 @@ static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic)
139140
{
140141
/* DMIC Owner Select to DSP */
141142
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) |
142-
DMICLCTL_OSEL(0x3), dmic->shim_base + DMICLCTL_OFFSET);
143+
FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET);
143144
}
144145

145146
static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
146147
{
147148
/* DMIC Owner Select back to Host CPU + DSP */
148149
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) &
149-
~DMICLCTL_OSEL(0x0), dmic->shim_base + DMICLCTL_OFFSET);
150+
~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET);
150151
}
151152

152153
#else /* CONFIG_DAI_DMIC_HAS_OWNERSHIP */
@@ -172,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
172173
uint32_t base = dai_dmic_base(dmic);
173174
/* DMIC Change sync period */
174175
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
175-
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPRD(val),
176+
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
176177
base + DMICSYNC_OFFSET);
177178
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
178179
base + DMICSYNC_OFFSET);
@@ -182,7 +183,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
182183
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
183184
base + DMICSYNC_OFFSET);
184185
#else /* All other CAVS and ACE platforms */
185-
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPRD(val),
186+
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
186187
base + DMICSYNC_OFFSET);
187188
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
188189
base + DMICSYNC_OFFSET);
@@ -193,7 +194,7 @@ static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic)
193194
{
194195
uint32_t base = dai_dmic_base(dmic);
195196
/* DMIC Clean sync period */
196-
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD(0x0000),
197+
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD,
197198
base + DMICSYNC_OFFSET);
198199
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_CMDSYNC,
199200
base + DMICSYNC_OFFSET);
@@ -239,13 +240,13 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
239240
switch (fifo_index) {
240241
case 0:
241242
dai_dmic_update_bits(dmic, OUTCONTROL0,
242-
OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
243-
OUTCONTROL0_FINIT_BIT);
243+
OUTCONTROL_SIP | OUTCONTROL_FINIT,
244+
OUTCONTROL_FINIT);
244245
break;
245246
case 1:
246247
dai_dmic_update_bits(dmic, OUTCONTROL1,
247-
OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
248-
OUTCONTROL1_FINIT_BIT);
248+
OUTCONTROL_SIP | OUTCONTROL_FINIT,
249+
OUTCONTROL_FINIT);
249250
break;
250251
}
251252
}
@@ -264,13 +265,13 @@ static void dai_dmic_irq_handler(const void *data)
264265
val1 = dai_dmic_read(dmic, OUTSTAT1);
265266
LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1);
266267

267-
if (val0 & OUTSTAT0_ROR_BIT) {
268+
if (val0 & OUTSTAT_ROR) {
268269
LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun");
269270
dai_dmic_write(dmic, OUTSTAT0, val0);
270271
dai_dmic_stop_fifo_packers(dmic, 0);
271272
}
272273

273-
if (val1 & OUTSTAT1_ROR_BIT) {
274+
if (val1 & OUTSTAT_ROR) {
274275
LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun");
275276
dai_dmic_write(dmic, OUTSTAT1, val1);
276277
dai_dmic_stop_fifo_packers(dmic, 1);
@@ -281,10 +282,10 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
281282
{
282283
/* Disable DMIC clock gating */
283284
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
284-
sys_write32((sys_read32(dmic->vshim_base + DMICLCTL_OFFSET) | DMIC_DCGD),
285-
dmic->vshim_base + DMICLCTL_OFFSET);
285+
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
286+
dmic->vshim_base + DMICLVSCTL_OFFSET);
286287
#else
287-
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMIC_DCGD),
288+
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD),
288289
dmic->shim_base + DMICLCTL_OFFSET);
289290
#endif
290291
}
@@ -293,10 +294,10 @@ static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
293294
{
294295
/* Enable DMIC clock gating */
295296
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
296-
sys_write32((sys_read32(dmic->vshim_base + DMICLCTL_OFFSET) & ~DMIC_DCGD),
297-
dmic->vshim_base + DMICLCTL_OFFSET);
297+
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
298+
dmic->vshim_base + DMICLVSCTL_OFFSET);
298299
#else
299-
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMIC_DCGD),
300+
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),
300301
dmic->shim_base + DMICLCTL_OFFSET);
301302
#endif
302303

@@ -413,21 +414,20 @@ static int dai_timestamp_dmic_start(const struct device *dev, struct dai_ts_cfg
413414
/* First point CDMAS to GPDMA channel that is used by DMIC
414415
* also clear NTK to be sure there is no old timestamp.
415416
*/
416-
cdmas = TS_LOCAL_TSCTRL_CDMAS(cfg->dma_chan_index +
417+
cdmas = FIELD_PREP(TS_LOCAL_TSCTRL_CDMAS, cfg->dma_chan_index +
417418
cfg->dma_chan_count * cfg->dma_id);
418-
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT | cdmas, addr);
419+
sys_write32(TS_LOCAL_TSCTRL_NTK | cdmas, addr);
419420

420421
/* Request on demand timestamp */
421-
sys_write32(TS_LOCAL_TSCTRL_ODTS_BIT | cdmas, addr);
422+
sys_write32(TS_LOCAL_TSCTRL_ODTS | cdmas, addr);
422423

423424
return 0;
424425
}
425426

426427
static int dai_timestamp_dmic_stop(const struct device *dev, struct dai_ts_cfg *cfg)
427428
{
428429
/* Clear NTK and write zero to CDMAS */
429-
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT,
430-
TS_DMIC_LOCAL_TSCTRL);
430+
sys_write32(TS_LOCAL_TSCTRL_NTK, TS_DMIC_LOCAL_TSCTRL);
431431
return 0;
432432
}
433433

@@ -439,7 +439,7 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
439439
uint32_t ntk;
440440

441441
/* Read SSP timestamp registers */
442-
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK_BIT;
442+
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
443443
if (!ntk)
444444
goto out;
445445

@@ -450,7 +450,7 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
450450
tsd->sample = sys_read64(TS_DMIC_LOCAL_SAMPLE);
451451

452452
/* Clear NTK to enable successive timestamps */
453-
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT, tsctrl);
453+
sys_write32(TS_LOCAL_TSCTRL_NTK, tsctrl);
454454

455455
out:
456456
tsd->walclk_rate = cfg->walclk_rate;
@@ -514,28 +514,28 @@ static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
514514

515515
if (dmic->startcount == DMIC_UNMUTE_CIC)
516516
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
517-
CIC_CONTROL_MIC_MUTE_BIT, 0);
517+
CIC_CONTROL_MIC_MUTE, 0);
518518

519519
if (dmic->startcount == DMIC_UNMUTE_FIR) {
520520
switch (dmic->dai_config_params.dai_index) {
521521
case 0:
522522
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
523-
FIR_CONTROL_A_MUTE_BIT, 0);
523+
FIR_CONTROL_MUTE, 0);
524524
break;
525525
case 1:
526526
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
527-
FIR_CONTROL_B_MUTE_BIT, 0);
527+
FIR_CONTROL_MUTE, 0);
528528
break;
529529
}
530530
}
531531
switch (dmic->dai_config_params.dai_index) {
532532
case 0:
533-
val = OUT_GAIN_LEFT_A_GAIN(gval);
533+
val = FIELD_PREP(OUT_GAIN, gval);
534534
dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_A, val);
535535
dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_A, val);
536536
break;
537537
case 1:
538-
val = OUT_GAIN_LEFT_B_GAIN(gval);
538+
val = FIELD_PREP(OUT_GAIN, gval);
539539
dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_B, val);
540540
dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_B, val);
541541
break;
@@ -576,23 +576,23 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
576576
dai_dmic_update_bits(
577577
dmic,
578578
OUTCONTROL0,
579-
OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
580-
OUTCONTROL0_SIP_BIT);
579+
OUTCONTROL_FINIT | OUTCONTROL_SIP,
580+
OUTCONTROL_SIP);
581581
break;
582582
case 1:
583583
LOG_INF("dmic_start(), dmic->fifo_b");
584584
/* Clear FIFO B initialize, Enable interrupts to DSP,
585585
* Start FIFO B packer.
586586
*/
587587
dai_dmic_update_bits(dmic, OUTCONTROL1,
588-
OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
589-
OUTCONTROL1_SIP_BIT);
588+
OUTCONTROL_FINIT | OUTCONTROL_SIP,
589+
OUTCONTROL_SIP);
590590
}
591591

592592
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
593593
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
594594
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
595-
CIC_CONTROL_SOFT_RESET_BIT, 0);
595+
CIC_CONTROL_SOFT_RESET, 0);
596596

597597
LOG_INF("dmic_start(), cic 0x%08x",
598598
dai_dmic_read(dmic, base[i] + CIC_CONTROL));
@@ -611,41 +611,41 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
611611
*/
612612
if (mic_a && mic_b) {
613613
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
614-
CIC_CONTROL_CIC_START_A_BIT |
615-
CIC_CONTROL_CIC_START_B_BIT,
616-
CIC_CONTROL_CIC_START_A(1) |
617-
CIC_CONTROL_CIC_START_B(1));
614+
CIC_CONTROL_CIC_START_A |
615+
CIC_CONTROL_CIC_START_B,
616+
FIELD_PREP(CIC_CONTROL_CIC_START_A, 1) |
617+
FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
618618
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
619-
MIC_CONTROL_PDM_EN_A_BIT |
620-
MIC_CONTROL_PDM_EN_B_BIT,
621-
MIC_CONTROL_PDM_EN_A(1) |
622-
MIC_CONTROL_PDM_EN_B(1));
619+
MIC_CONTROL_PDM_EN_A |
620+
MIC_CONTROL_PDM_EN_B,
621+
FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1) |
622+
FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
623623
} else if (mic_a) {
624624
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
625-
CIC_CONTROL_CIC_START_A_BIT,
626-
CIC_CONTROL_CIC_START_A(1));
625+
CIC_CONTROL_CIC_START_A,
626+
FIELD_PREP(CIC_CONTROL_CIC_START_A, 1));
627627
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
628-
MIC_CONTROL_PDM_EN_A_BIT,
629-
MIC_CONTROL_PDM_EN_A(1));
628+
MIC_CONTROL_PDM_EN_A,
629+
FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1));
630630
} else if (mic_b) {
631631
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
632-
CIC_CONTROL_CIC_START_B_BIT,
633-
CIC_CONTROL_CIC_START_B(1));
632+
CIC_CONTROL_CIC_START_B,
633+
FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
634634
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
635-
MIC_CONTROL_PDM_EN_B_BIT,
636-
MIC_CONTROL_PDM_EN_B(1));
635+
MIC_CONTROL_PDM_EN_B,
636+
FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
637637
}
638638

639639
switch (dmic->dai_config_params.dai_index) {
640640
case 0:
641641
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
642-
FIR_CONTROL_A_START_BIT,
643-
FIR_CONTROL_A_START(fir_a));
642+
FIR_CONTROL_START,
643+
FIELD_PREP(FIR_CONTROL_START, fir_a));
644644
break;
645645
case 1:
646646
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
647-
FIR_CONTROL_B_START_BIT,
648-
FIR_CONTROL_B_START(fir_b));
647+
FIR_CONTROL_START,
648+
FIELD_PREP(FIR_CONTROL_START, fir_b));
649649
break;
650650
}
651651
}
@@ -656,7 +656,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
656656
*/
657657
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
658658
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
659-
CIC_CONTROL_SOFT_RESET_BIT, 0);
659+
CIC_CONTROL_SOFT_RESET, 0);
660660

661661
LOG_INF("dmic_start(), cic 0x%08x",
662662
dai_dmic_read(dmic, base[i] + CIC_CONTROL));
@@ -704,21 +704,21 @@ static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
704704
/* Don't stop CIC yet if one FIFO remains active */
705705
if (dai_dmic_global.active_fifos_mask == 0) {
706706
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
707-
CIC_CONTROL_SOFT_RESET_BIT |
708-
CIC_CONTROL_MIC_MUTE_BIT,
709-
CIC_CONTROL_SOFT_RESET_BIT |
710-
CIC_CONTROL_MIC_MUTE_BIT);
707+
CIC_CONTROL_SOFT_RESET |
708+
CIC_CONTROL_MIC_MUTE,
709+
CIC_CONTROL_SOFT_RESET |
710+
CIC_CONTROL_MIC_MUTE);
711711
}
712712
switch (dmic->dai_config_params.dai_index) {
713713
case 0:
714714
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
715-
FIR_CONTROL_A_MUTE_BIT,
716-
FIR_CONTROL_A_MUTE_BIT);
715+
FIR_CONTROL_MUTE,
716+
FIR_CONTROL_MUTE);
717717
break;
718718
case 1:
719719
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
720-
FIR_CONTROL_B_MUTE_BIT,
721-
FIR_CONTROL_B_MUTE_BIT);
720+
FIR_CONTROL_MUTE,
721+
FIR_CONTROL_MUTE);
722722
break;
723723
}
724724
}

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