soc: intel_s1000: define default MEMCTL reg value

When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined
which results in some variables not being able to be defined.
So define them.

Signed-off-by: Daniel Leung <[email protected]>

Author: dcpleung

soc/xtensa/intel_s1000/linker.ld

@@ -139,6 +139,9 @@ PHDRS
 _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
 
+PROVIDE(__memctl_default = 0xFFFFFF00);
+PROVIDE(_MemErrorHandler = 0xFFFFFF00);
+
 ENTRY(CONFIG_KERNEL_ENTRY)
 
 /* Various memory-map dependent cache attribute settings: */