drivers: clock_control: Add STM32 clock multiplexer driver

Add a clock multiplexer driver.
Its only function is to select a clock input.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

drivers/clock_control/CMakeLists.txt

@@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR       clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
+  zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c)
 if(CONFIG_SOC_SERIES_STM32MP1X)
   zephyr_library_sources(clock_stm32_ll_mp1.c)
 elseif(CONFIG_SOC_SERIES_STM32H7X)

drivers/clock_control/Kconfig.stm32

@@ -8,7 +8,7 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
 	bool "STM32 Reset & Clock Control"
 	depends on SOC_FAMILY_STM32
 	select USE_STM32_LL_UTILS
-	select USE_STM32_LL_RCC if SOC_SERIES_STM32MP1X
+	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X)
 	help
 	  Enable driver for Reset & Clock Control subsystem found
 	  in STM32 family of MCUs
@@ -17,6 +17,7 @@ if CLOCK_CONTROL_STM32_CUBE
 
 DT_STM32_HSE_CLOCK := $(dt_nodelabel_path,clk_hse)
 DT_STM32_HSE_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_HSE_CLOCK),clock-frequency)
+DT_COMPAT_ST_MUX_CLOCK := st,stm32-clock-mux
 
 config CLOCK_STM32_HSE_CLOCK
 	int "HSE clock value"
@@ -33,6 +34,15 @@ config CLOCK_STM32_HSE_CLOCK
 	  Note: Device tree configuration is overridden when current symbol is set:
 	  CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
 
+config CLOCK_STM32_MUX
+	bool "STM32 clock mux driver"
+	default $(dt_compat_enabled,$(DT_COMPAT_ST_MUX_CLOCK))
+	help
+	  Enable driver for STM32 clock mux which don't match an
+	  existing clock hardware block but allows to select a clock
+	  for a specific domain. For instance per_ck clock on STM32H7 or
+	  CLK48 clock
+
 # Micro-controller Clock output configuration options
 
 choice

drivers/clock_control/clock_stm32_mux.c

@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2022, Linaro Ltd
+ *
+ */
+
+#include <drivers/clock_control.h>
+#include <sys/util.h>
+#include <drivers/clock_control/stm32_clock_control.h>
+
+#include <logging/log.h>
+#include <soc.h>
+
+#define DT_DRV_COMPAT st_stm32_clock_mux
+
+LOG_MODULE_REGISTER(clock_mux, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
+
+
+struct stm32_clk_mux_config {
+	const struct stm32_pclken pclken;
+};
+
+static int stm32_clk_mux_init(const struct device *dev)
+{
+	const struct stm32_clk_mux_config *cfg = dev->config;
+
+	if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			       (clock_control_subsys_t) &cfg->pclken) != 0) {
+		LOG_ERR("Could not enable clock mux");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+#define STM32_MUX_CLK_INIT(id)						\
+									\
+static const struct stm32_clk_mux_config stm32_clk_mux_cfg_##id = {	\
+	.pclken = STM32_INST_CLOCK_INFO(id, 0)				\
+};									\
+									\
+DEVICE_DT_INST_DEFINE(id, &stm32_clk_mux_init, NULL,			\
+		    NULL, &stm32_clk_mux_cfg_##id,			\
+		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,	\
+		    NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(STM32_MUX_CLK_INIT)