dts: bindings: pll i2s for the stm32f412 has a Q divider

There is a Q-divider factor [2..15] for the stm32f412 serie
which supplies the 48MHz clock.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

dts/bindings/clock/st,stm32f411-plli2s-clock.yaml

@@ -24,3 +24,23 @@ properties:
     description: |
         Division factor for the PLL input clock
         Valid range: 2 - 63
+
+  div-q:
+    type: int
+    description: |
+        PLLI2S division factor for I2S Clocks to supply USB/SDIO/RNG
+    enum:
+      - 2
+      - 3
+      - 4
+      - 5
+      - 6
+      - 7
+      - 8
+      - 9
+      - 10
+      - 11
+      - 12
+      - 13
+      - 14
+      - 15

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -28,14 +28,18 @@
 /* defined in stm32_common_clocks.h */
 /** Fixed clocks */
 /* Low speed clocks defined in stm32_common_clocks.h */
-#define STM32_SRC_HSI      (STM32_SRC_LSI + 1)
-#define STM32_SRC_HSE      (STM32_SRC_HSI + 1)
+#define STM32_SRC_HSI		(STM32_SRC_LSI + 1)
+#define STM32_SRC_HSE		(STM32_SRC_HSI + 1)
 /** PLL clock outputs */
-#define STM32_SRC_PLL_P    (STM32_SRC_HSE + 1)
-#define STM32_SRC_PLL_Q    (STM32_SRC_PLL_P + 1)
-#define STM32_SRC_PLL_R    (STM32_SRC_PLL_Q + 1)
+#define STM32_SRC_PLL_P		(STM32_SRC_HSE + 1)
+#define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
+#define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 /** I2S sources */
-#define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1)
+#define STM32_SRC_PLLI2S_Q	(STM32_SRC_PLL_R + 1)
+#define STM32_SRC_PLLI2S_R	(STM32_SRC_PLLI2S_Q + 1)
+/* CLK48MHz sources */
+#define STM32_SRC_CK48		(STM32_SRC_PLLI2S_R + 1)
+
 /* I2S_CKIN not supported yet */
 /* #define STM32_SRC_I2S_CKIN	TBD */