drivers: pinctrl: stm32: add support for STM32N6 pinctrl

Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.

Signed-off-by: Mathieu Choplain <[email protected]>

Author: Mathieu Choplain

drivers/pinctrl/pinctrl_stm32.c

@@ -9,6 +9,8 @@
 #include <zephyr/init.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
 #include <gpio/gpio_stm32.h>
 
 #include <stm32_ll_bus.h>
@@ -225,6 +227,61 @@ static int stm32_pin_configure(uint32_t pin, uint32_t pin_cgf, uint32_t pin_func
 	return gpio_stm32_configure(port_device, STM32_PIN(pin), pin_cgf, pin_func);
 }
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl)
+static int apply_iosync_configuration(uint32_t port, uint32_t pin, uint32_t pincfg)
+{
+	const struct device *port_device;
+	const struct gpio_stm32_config *gpio_cfg;
+	uint32_t piocfgr, delayr, pinbit;
+	GPIO_TypeDef *gpio_reg;
+	int ret;
+
+	if (port >= gpio_ports_cnt) {
+		return -EINVAL;
+	}
+
+	port_device = gpio_ports[port];
+	if (port_device == NULL || !device_is_ready(port_device)) {
+		return -ENODEV;
+	}
+
+	/**
+	 * For lack of better way, obtain the GPIO base address from the
+	 * device's configuration directly. This *can* be made cleaner
+	 * but would require reworking the GPIO & PINCTRL entirely...
+	 */
+	gpio_cfg = port_device->config;
+	gpio_reg = (GPIO_TypeDef *)gpio_cfg->base;
+
+	/* Make sure GPIO clock is enabled */
+	ret = pm_device_runtime_get(port_device);
+	if (ret < 0) {
+		return ret;
+	}
+
+	piocfgr = (pincfg >> STM32_IORETIME_ADVCFGR_SHIFT) & STM32_IORETIME_ADVCFGR_MASK;
+	delayr = (pincfg >> STM32_IODELAY_LENGTH_SHIFT) & STM32_IODELAY_LENGTH_MASK;
+	pinbit = BIT(pin);
+
+	/**
+	 * Thanks to clever encoding, we don't have to check whether the I/O retiming
+	 * is to be enabled or not; all we need to do is write to the registers where
+	 * everything will fall in place nicely. This can obviously be updated for
+	 * new hardware, if required...
+	 */
+	if (pin <= 7) {
+		LL_GPIO_SetDelayPin_0_7(gpio_reg, pinbit, delayr);
+		LL_GPIO_SetPIOControlPin_0_7(gpio_reg, pinbit, piocfgr);
+	} else {
+		LL_GPIO_SetDelayPin_8_15(gpio_reg, pinbit, delayr);
+		LL_GPIO_SetPIOControlPin_8_15(gpio_reg, pinbit, piocfgr);
+	}
+
+	/* Release GPIO device since we are done */
+	return pm_device_runtime_put(port_device);
+}
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
@@ -285,6 +342,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 		if (ret < 0) {
 			return ret;
 		}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl)
+		ret = apply_iosync_configuration(
+			STM32_DT_PINMUX_PORT(mux),
+			STM32_DT_PINMUX_LINE(mux),
+			pins[i].pincfg);
+		if (ret < 0) {
+			return ret;
+		}
+#endif
 	}
 
 	return 0;

soc/st/stm32/common/pinctrl_soc.h

@@ -22,6 +22,11 @@
 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
 #endif
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl)
+/* Required for GPIO LL definitions we use */
+#include <stm32_ll_gpio.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -32,7 +37,7 @@ extern "C" {
 typedef struct pinctrl_soc_pin {
 	/** Pinmux settings (port, pin and function). */
 	uint32_t pinmux;
-	/** Pin configuration (bias, drive and slew rate). */
+	/** Pin configuration (bias, drive, slew rate, I/O retime) */
 	uint32_t pincfg;
 } pinctrl_soc_pin_t;
 
@@ -55,6 +60,23 @@ typedef struct pinctrl_soc_pin {
 #define STM32_OUTPUT_HIGH 0x1
 #define STM32_GPIO_OUTPUT 0x1
 
+/**
+ * @brief Definitions for the various fields related to I/O synchronization
+ *
+ * NOTES:
+ *  (1) Series-specific CMSIS and GPIO LL definitions are used here.
+ *      This is OK as long as the macros are never used on series where
+ *      the underlying definitions do not exist.
+ *  (2) I/O delay values definitions from GPIO LL definitions are used
+ *      directly to ensure greater portability to other platforms.
+ */
+#define STM32_IOSYNC_DELAY_DIRECTION_OUTPUT	0x0
+#define STM32_IOSYNC_DELAY_DIRECTION_INPUT	GPIO_ADVCFGRL_DLYPATH0
+#define STM32_IOSYNC_RETIME_EDGE_RISING		0x0
+#define STM32_IOSYNC_RETIME_EDGE_FALLING	GPIO_ADVCFGRL_INVCLK0
+#define STM32_IOSYNC_RETIME_EDGE_BOTH		GPIO_ADVCFGRL_DE0
+#define STM32_IOSYNC_RETIME_ENABLE		GPIO_ADVCFGRL_RET0
+
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 /**
  * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (F1).
@@ -71,6 +93,36 @@ typedef struct pinctrl_soc_pin {
 	 ((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
 	 (DT_ENUM_IDX(node_id, slew_rate) << STM32_MODE_OSPEED_SHIFT))
 #else
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl)
+/* Inner helper macro for Z_PINCTRL_STM32_IOSYNC_INIT */
+#define Z_PINCTRL_STM32_IOSYNC_INIT_INNER(delay_path, retime_edge, retime_enable, delay_ps)	\
+	((CONCAT(STM32_IOSYNC_DELAY_DIRECTION_, delay_path) << STM32_IODELAY_DIRECTION_SHIFT) | \
+	 ((retime_enable) << STM32_IORETIME_ENABLE_SHIFT) |					\
+	 (CONCAT(STM32_IOSYNC_RETIME_EDGE_, retime_edge) << STM32_IORETIME_EDGE_SHIFT) |	\
+	 (CONCAT(LL_GPIO_DELAY_, delay_ps) << STM32_IODELAY_LENGTH_SHIFT))
+
+/**
+ * @brief Utility macro to initialize fields of @ref{pinctrl_pin_t}.pincfg
+ *        related to the I/O synchronization feature
+ *
+ * @param node_id Pinctrl node identifier
+ *
+ * NOTE: a default value for st,retime-edge is specified to ensure the macro expands properly.
+ * However, this default value is never used, as I/O retiming is not enabled unless the property
+ * was explicitly specified in Device Tree.
+ */
+#define Z_PINCTRL_STM32_IOSYNC_INIT(node_id)							\
+	Z_PINCTRL_STM32_IOSYNC_INIT_INNER(							\
+		DT_STRING_UPPER_TOKEN(node_id, st_io_delay_path),				\
+		DT_STRING_UPPER_TOKEN_OR(node_id, st_retime_edge, RISING),			\
+		STM32_IOSYNC_RETIME_ENABLE * DT_NODE_HAS_PROP(node_id, st_retime_edge),		\
+		DT_PROP(node_id, st_io_delay_ps))
+#else /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl) */
+/** Dummy value for series without I/O synchronization feature */
+#define Z_PINCTRL_STM32_IOSYNC_INIT(node_id)	0
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_pinctrl) */
+
 /**
  * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (non-F1).
  *
@@ -86,7 +138,8 @@ typedef struct pinctrl_soc_pin {
 	 ((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
 	 ((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_low)) << STM32_MODER_SHIFT) | \
 	 ((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_high)) << STM32_MODER_SHIFT) | \
-	 (DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT))
+	 (DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT) | \
+	 (Z_PINCTRL_STM32_IOSYNC_INIT(node_id)))
 #endif /* CONFIG_SOC_SERIES_STM32F1X */
 
 /**