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boards: openhwgroup: add CVA6 on Arty A7 board
Adds support for the CVA6 CPU on an Arty A7 FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 32-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann <[email protected]>
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‎boards/openhwgroup/cv32a6_arty_a7_100/Kconfig.cv32a6_arty_a7_100‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV32A6_ARTY_A7_100
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select SOC_CV32A6
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select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

‎boards/openhwgroup/cv32a6_arty_a7_100/board.cmake‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
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board_runner_args(openocd "--use-elf")
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board_runner_args(openocd "--verify")
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board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x8f000000 -work-area-size 16780000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/openhwgroup/cv32a6_arty_a7_100/board.yml‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv32a6_arty_a7_100
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vendor: openhwgroup
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socs:
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- name: cv32a6

‎boards/openhwgroup/cv32a6_arty_a7_100/cv32a6_arty_a7_100.dts‎

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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv32a6.dtsi>
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/ {
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model = "Openhardwaregroup CV32A6 on Arty A7 100";
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compatible = "ariane,cv32a6_arty_a7_100";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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clock-frequency = <25000000>;
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current-speed = <57600>;
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// different interrupt than the CISPA version of the SoC
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interrupts = <1 4>;
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};
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&spi0 {
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status = "okay";
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// different interrupt than the CISPA version of the SoC
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interrupts = <2 2>;
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&mdio0{
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status = "disabled";
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};
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&eth0 {
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status = "disabled";
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};
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// Arty only has 256 MiB of memory
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&memory0 {
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reg = <0x80000000 0x10000000>;
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};
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// Arty can only run at 25 Mhz
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&cpus_0 {
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timebase-frequency = <12500000>;
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};
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&cpu_0 {
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clock-frequency = <25000000>;
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};
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‎boards/openhwgroup/cv32a6_arty_a7_100/cv32a6_arty_a7_100_defconfig‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_BASE64=y
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
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CONFIG_CONSOLE_HANDLER=y
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CONFIG_XIP=n
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CONFIG_INIT_STACKS=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
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CONFIG_POWEROFF=y
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# RNG
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CONFIG_TIMER_RANDOM_GENERATOR=y
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CONFIG_TEST_RANDOM_GENERATOR=y
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# IRQs
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CONFIG_MULTI_LEVEL_INTERRUPTS=y
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CONFIG_2ND_LEVEL_INTERRUPTS=y
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# 1 PLIC
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
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CONFIG_PLIC=y
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CONFIG_3RD_LEVEL_INTERRUPTS=n
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# no networking support on this board
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# logging
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CONFIG_LOG=y
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CONFIG_LOG_DEFAULT_LEVEL=3
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CONFIG_THREAD_NAME=y
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# increased stack sizes
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CONFIG_ISR_STACK_SIZE=524288
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CONFIG_MAIN_STACK_SIZE=524288
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CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
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CONFIG_IDLE_STACK_SIZE=524288
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# slower clock on Arty
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000

‎boards/openhwgroup/cv32a6_arty_a7_100/support/ariane.cfg‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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# Based on the ariane.cfg from the cva6 project:
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# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane_arty_a7.cfg
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adapter driver ftdi
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transport select jtag
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ftdi vid_pid 0x0403 0x6010
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# Channel 1 is UART
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ftdi channel 0
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# https://github.com/epsilon537/boxlambda/blob/master/scripts/arty_a7_100t.openocd.cfg
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ftdi layout_init 0x00e8 0x60eb
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x13631093
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
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riscv set_ir idcode 0x09
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riscv set_ir dtmcs 0x22
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riscv set_ir dmi 0x23
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riscv set_command_timeout_sec 120
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adapter speed 100
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# prefer to use sba for system bus access
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riscv set_mem_access progbuf sysbus abstract
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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# Try enabling address translation (only works for newer versions)
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if { [catch {riscv set_enable_virtual on} ] } {
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echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
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init
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halt
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echo "Ready for Remote Connections"

‎boards/openhwgroup/cv64a6_arty_a7_100/Kconfig.cv64a6_arty_a7_100‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CV64A6_ARTY_A7_100
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select SOC_CV64A6_IMAC
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select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

‎boards/openhwgroup/cv64a6_arty_a7_100/board.cmake‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
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board_runner_args(openocd "--use-elf")
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board_runner_args(openocd "--verify")
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board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x8f000000 -work-area-size 16780000")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

‎boards/openhwgroup/cv64a6_arty_a7_100/board.yml‎

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# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: cv64a6_arty_a7_100
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vendor: openhwgroup
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socs:
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- name: cv64a6

‎boards/openhwgroup/cv64a6_arty_a7_100/cv64a6_arty_a7_100.dts‎

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/*
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* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <openhwgroup/cv64a6.dtsi>
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/ {
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model = "Openhardwaregroup CV64A6 on Arty A7 100";
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compatible = "ariane,cv64a6_arty_a7_100";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &memory0;
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};
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};
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&uart0 {
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status = "okay";
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// different interrupt than the CISPA version of the SoC
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interrupts = <1 4>;
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};
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&spi0 {
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status = "okay";
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// different interrupt than the CISPA version of the SoC
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interrupts = <2 2>;
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};
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&clint{
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status = "okay";
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};
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&dma0 {
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status = "disabled";
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};
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&mdio0{
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status = "disabled";
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};
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&eth0 {
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status = "disabled";
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};
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// Arty only has 256 MiB of memory
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&memory0 {
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reg = <0x80000000 0x10000000>;
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};
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// Arty can only run at 25 Mhz
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&cpus_0 {
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timebase-frequency = <12500000>;
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};
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&cpu_0{
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clock-frequency = <25000000>;
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};
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