soc: nxp: rw: Move the code for pin configuration in sleep mode to SoC file

All pins are configured by default to be output low during sleep.
A device-tree property called "sleep-output" is provided for cases where
pins need to be configured differently.

Signed-off-by: Mahesh Mahadevan <[email protected]>

Author: mmahadevan108

boards/nxp/frdm_rw612/init.c

@@ -6,17 +6,6 @@
 #include <zephyr/pm/pm.h>
 #include <fsl_power.h>
 #include <fsl_common.h>
-#include <fsl_io_mux.h>
-
-#define NON_AON_PINS_START	0
-#define NON_AON_PINS_BREAK	21
-#define NON_AON_PINS_RESTART	28
-#define NON_AON_PINS_END	63
-#define RF_CNTL_PINS_START	0
-#define RF_CNTL_PINS_END	3
-#define LED_BLUE_GPIO		0
-#define LED_RED_GPIO		1
-#define LED_GREEN_GPIO		12
 
 static void frdm_rw612_power_init_config(void)
 {
@@ -53,26 +42,6 @@ void board_early_init_hook(void)
 	};
 
 	pm_notifier_register(&frdm_rw612_pm_notifier);
-
-	int32_t i;
-
-	/* Set all non-AON pins output low level in sleep mode. */
-	for (i = NON_AON_PINS_START; i <= NON_AON_PINS_BREAK; i++) {
-		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
-	for (i = NON_AON_PINS_RESTART; i <= NON_AON_PINS_END; i++) {
-		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
-
-	/* Set the LED GPIO output pins to be High in PM3 as these pins are Active Low */
-	IO_MUX_SetPinOutLevelInSleep(LED_BLUE_GPIO, IO_MUX_SleepPinLevelHigh);
-	IO_MUX_SetPinOutLevelInSleep(LED_RED_GPIO, IO_MUX_SleepPinLevelHigh);
-	IO_MUX_SetPinOutLevelInSleep(LED_GREEN_GPIO, IO_MUX_SleepPinLevelHigh);
-
-	/* Set RF_CNTL 0-3 output low level in sleep mode. */
-	for (i = RF_CNTL_PINS_START; i <= RF_CNTL_PINS_END; i++) {
-		IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
 #endif
 
 #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES

boards/nxp/rd_rw612_bga/init.c

@@ -6,14 +6,6 @@
 #include <zephyr/pm/pm.h>
 #include <fsl_power.h>
 #include <fsl_common.h>
-#include <fsl_io_mux.h>
-
-#define NON_AON_PINS_START      0
-#define NON_AON_PINS_BREAK      21
-#define NON_AON_PINS_RESTART    28
-#define NON_AON_PINS_END        63
-#define RF_CNTL_PINS_START      0
-#define RF_CNTL_PINS_END        3
 
 static void rdrw61x_power_init_config(void)
 {
@@ -50,21 +42,6 @@ void board_early_init_hook(void)
 	};
 
 	pm_notifier_register(&rdrw61x_pm_notifier);
-
-	int32_t i;
-
-	/* Set all non-AON pins output low level in sleep mode. */
-	for (i = NON_AON_PINS_START; i <= NON_AON_PINS_BREAK; i++) {
-		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
-	for (i = NON_AON_PINS_RESTART; i <= NON_AON_PINS_END; i++) {
-		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
-
-	/* Set RF_CNTL 0-3 output low level in sleep mode. */
-	for (i = RF_CNTL_PINS_START; i <= RF_CNTL_PINS_END; i++) {
-		IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
-	}
 #endif
 
 #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES

soc/nxp/rw/soc.c

@@ -17,10 +17,18 @@
 #include <fsl_clock.h>
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
+#include <fsl_io_mux.h>
 #include "soc.h"
 #include "flexspi_clock_setup.h"
 #include "fsl_ocotp.h"
 
+#define NON_AON_PINS_START      0
+#define NON_AON_PINS_BREAK      21
+#define NON_AON_PINS_RESTART    28
+#define NON_AON_PINS_END        63
+#define RF_CNTL_PINS_START      0
+#define RF_CNTL_PINS_END        3
+
 extern void nxp_nbu_init(void);
 #ifdef CONFIG_NXP_RW6XX_BOOT_HEADER
 extern char z_main_stack[];
@@ -325,6 +333,20 @@ void soc_early_init_hook(void)
 #endif
 #if CONFIG_PM
 	nxp_rw6xx_power_init();
+
+	int32_t i;
+	/* Set all non-AON pins output low level in sleep mode. */
+	for (i = NON_AON_PINS_START; i <= NON_AON_PINS_BREAK; i++) {
+		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+	}
+	for (i = NON_AON_PINS_RESTART; i <= NON_AON_PINS_END; i++) {
+		IO_MUX_SetPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+	}
+
+	/* Set RF_CNTL 0-3 output low level in sleep mode. */
+	for (i = RF_CNTL_PINS_START; i <= RF_CNTL_PINS_END; i++) {
+		IO_MUX_SetRfPinOutLevelInSleep(i, IO_MUX_SleepPinLevelLow);
+	}
 #endif
 
 #if defined(CONFIG_BT) || defined(CONFIG_IEEE802154)