boards: st: fix NOR/PSRAM bank 'st,control' indentation

Correct 'st,control' values indentation.

Signed-off-by: Georgij Černyšiov <[email protected]>

Author: GeorgeCGV

boards/st/stm32h573i_dk/stm32h573i_dk.dts

@@ -112,19 +112,19 @@
 		bank@0 {
 			reg = <0x0>;
 			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
-				STM32_FMC_MEMORY_TYPE_SRAM
-				STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
-				STM32_FMC_BURST_ACCESS_MODE_DISABLE
-				STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
-				STM32_FMC_WAIT_TIMING_BEFORE_WS
-				STM32_FMC_WRITE_OPERATION_ENABLE
-				STM32_FMC_WAIT_SIGNAL_DISABLE
-				STM32_FMC_EXTENDED_MODE_DISABLE
-				STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
-				STM32_FMC_WRITE_BURST_DISABLE
-				STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
-				STM32_FMC_WRITE_FIFO_DISABLE
-				STM32_FMC_PAGE_SIZE_NONE>;
+				      STM32_FMC_MEMORY_TYPE_SRAM
+				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
+				      STM32_FMC_BURST_ACCESS_MODE_DISABLE
+				      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
+				      STM32_FMC_WAIT_TIMING_BEFORE_WS
+				      STM32_FMC_WRITE_OPERATION_ENABLE
+				      STM32_FMC_WAIT_SIGNAL_DISABLE
+				      STM32_FMC_EXTENDED_MODE_DISABLE
+				      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
+				      STM32_FMC_WRITE_BURST_DISABLE
+				      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
+				      STM32_FMC_WRITE_FIFO_DISABLE
+				      STM32_FMC_PAGE_SIZE_NONE>;
 			st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
 
 			fmc-mipi-dbi {

boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi

@@ -71,19 +71,19 @@
 		bank@0 {
 			reg = <0x0>;
 			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
-				STM32_FMC_MEMORY_TYPE_SRAM
-				STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
-				STM32_FMC_BURST_ACCESS_MODE_DISABLE
-				STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
-				STM32_FMC_WAIT_TIMING_BEFORE_WS
-				STM32_FMC_WRITE_OPERATION_ENABLE
-				STM32_FMC_WAIT_SIGNAL_DISABLE
-				STM32_FMC_EXTENDED_MODE_DISABLE
-				STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
-				STM32_FMC_WRITE_BURST_DISABLE
-				STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
-				STM32_FMC_WRITE_FIFO_DISABLE
-				STM32_FMC_PAGE_SIZE_NONE>;
+				      STM32_FMC_MEMORY_TYPE_SRAM
+				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
+				      STM32_FMC_BURST_ACCESS_MODE_DISABLE
+				      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
+				      STM32_FMC_WAIT_TIMING_BEFORE_WS
+				      STM32_FMC_WRITE_OPERATION_ENABLE
+				      STM32_FMC_WAIT_SIGNAL_DISABLE
+				      STM32_FMC_EXTENDED_MODE_DISABLE
+				      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
+				      STM32_FMC_WRITE_BURST_DISABLE
+				      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
+				      STM32_FMC_WRITE_FIFO_DISABLE
+				      STM32_FMC_PAGE_SIZE_NONE>;
 			st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
 
 			fmc-mipi-dbi {