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drivers: misc: ethos_u: Add support NPU on Renesas devices
Add support NPU driver on Renesas devices Signed-off-by: Khoa Nguyen <[email protected]>
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‎drivers/misc/ethos_u/CMakeLists.txt‎

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@@ -6,3 +6,4 @@ zephyr_library()
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zephyr_library_sources(ethos_u_common.c)
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zephyr_library_sources_ifdef(CONFIG_ETHOS_U_ARM ethos_u_arm.c)
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zephyr_library_sources_ifdef(CONFIG_ETHOS_U_NUMAKER ethos_u_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_ETHOS_U_RENESAS ethos_u_renesas.c)

‎drivers/misc/ethos_u/Kconfig‎

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@@ -6,6 +6,7 @@ choice
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depends on ETHOS_U
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default ETHOS_U_ARM if DT_HAS_ARM_ETHOS_U_ENABLED
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default ETHOS_U_NUMAKER if DT_HAS_NUVOTON_NUMAKER_NPU_ENABLED
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default ETHOS_U_RENESAS if DT_HAS_RENESAS_RA_NPU_ENABLED
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config ETHOS_U_ARM
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bool "Arm Ethos-U NPU driver"
@@ -17,6 +18,11 @@ config ETHOS_U_NUMAKER
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help
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Enables Nuvoton NuMaker frontend of Arm Ethos-U NPU driver
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config ETHOS_U_RENESAS
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bool "Renesas RA Ethos-U NPU driver"
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help
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Enables Renesas RA frontend of Arm Ethos-U NPU driver.
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endchoice
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config ETHOS_U_DCACHE

‎drivers/misc/ethos_u/ethos_u_renesas.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/logging/log.h>
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#include <ethosu_driver.h>
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#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
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#include <soc.h>
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#include "ethos_u_common.h"
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#define DT_DRV_COMPAT renesas_ra_npu
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LOG_MODULE_REGISTER(renesas_ra_npu, CONFIG_ETHOS_U_LOG_LEVEL);
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struct ethos_u_renesas_config {
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const struct ethosu_dts_info ethosu_dts_info;
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const struct device *clock_dev;
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const struct clock_control_ra_subsys_cfg clock_subsys;
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};
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void ethos_u_renesas_ra_irq_handler(const struct device *dev)
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{
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struct ethosu_data *data = dev->data;
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struct ethosu_driver *drv = &data->drv;
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IRQn_Type irq = R_FSP_CurrentIrqGet();
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ethosu_irq_handler(drv);
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R_BSP_IrqStatusClear(irq);
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}
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static int ethos_u_renesas_ra_init(const struct device *dev)
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{
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const struct ethos_u_renesas_config *config = dev->config;
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const struct ethosu_dts_info ethosu_dts_info = config->ethosu_dts_info;
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struct ethosu_data *data = dev->data;
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struct ethosu_driver *drv = &data->drv;
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struct ethosu_driver_version version;
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int err;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_subsys);
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if (err < 0) {
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LOG_ERR("Could not initialize clock (%d)", err);
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return err;
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}
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if ((((0 == R_SYSTEM->PGCSAR_b.NONSEC2) && FSP_PRIV_TZ_USE_SECURE_REGS) ||
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((1 == R_SYSTEM->PGCSAR_b.NONSEC2) && BSP_TZ_NONSECURE_BUILD)) &&
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(0 != R_SYSTEM->PDCTRNPU)) {
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/* Turn on NPU power domain */
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
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FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk |
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R_SYSTEM_PDCTRGD_PDPGSF_Msk)),
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R_SYSTEM_PDCTRGD_PDPGSF_Msk);
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R_SYSTEM->PDCTRNPU = 0;
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FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRNPU & (R_SYSTEM_PDCTRNPU_PDCSF_Msk |
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R_SYSTEM_PDCTRGD_PDPGSF_Msk)),
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0);
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
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}
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LOG_DBG("Ethos-U DTS info. base_address=0x%p, secure_enable=%u, privilege_enable=%u",
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ethosu_dts_info.base_addr, ethosu_dts_info.secure_enable,
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ethosu_dts_info.privilege_enable);
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ethosu_get_driver_version(&version);
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LOG_DBG("Version. major=%u, minor=%u, patch=%u", version.major, version.minor,
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version.patch);
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if (ethosu_init(drv, ethosu_dts_info.base_addr, NULL, 0, ethosu_dts_info.secure_enable,
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ethosu_dts_info.privilege_enable)) {
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LOG_ERR("Failed to initialize NPU with ethosu_init().");
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return -EINVAL;
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}
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ethosu_dts_info.irq_config();
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return 0;
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}
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#define ETHOSU_RENESAS_RA_DEVICE_INIT(idx) \
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static struct ethosu_data ethosu_data_##idx; \
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\
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static void ethosu_zephyr_irq_config_##idx(void) \
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{ \
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R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(idx, npu_irq, irq)].IELS = \
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BSP_PRV_IELS_ENUM(EVENT_NPU_IRQ); \
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\
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BSP_ASSIGN_EVENT_TO_CURRENT_CORE(BSP_PRV_IELS_ENUM(EVENT_NPU_IRQ)); \
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\
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), \
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ethos_u_renesas_ra_irq_handler, DEVICE_DT_INST_GET(idx), 0); \
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\
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irq_enable(DT_INST_IRQN(idx)); \
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} \
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\
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static const struct ethos_u_renesas_config ethos_u_renesas_config##idx = { \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_subsys = \
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{ \
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.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(idx, 0, mstp), \
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.stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(idx, 0, stop_bit), \
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}, \
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.ethosu_dts_info = \
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{ \
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.base_addr = (void *)DT_INST_REG_ADDR(idx), \
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.secure_enable = DT_INST_PROP(idx, secure_enable), \
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.privilege_enable = DT_INST_PROP(idx, privilege_enable), \
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.irq_config = &ethosu_zephyr_irq_config_##idx, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, ethos_u_renesas_ra_init, NULL, &ethosu_data_##idx, \
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&ethos_u_renesas_config##idx, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
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DT_INST_FOREACH_STATUS_OKAY(ETHOSU_RENESAS_RA_DEVICE_INIT);

‎dts/bindings/arm/renesas,ra-npu.yaml‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA frontend of Arm Ethos-U NPU driver
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compatible: "renesas,ra-npu"
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include: "arm,ethos-u.yaml"
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properties:
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clocks:
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required: true
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interrupt-names:
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required: true
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enum:
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- "npu-irq"

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