boards: arm: Introduce gd32f450i_eval board

Add GD32F450i_EVAL board initial version.
Only support hello_world sample.

Signed-off-by: HaiLong Yang <[email protected]>

Author: cameled

boards/arm/gd32f450i_eval/CMakeLists.txt

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+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/arm/gd32f450i_eval/Kconfig

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+# Copyright (c) 2021 ATL-Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+	int "Board initialization priority"
+	default 50
+	help
+	  Board initialization priority.

boards/arm/gd32f450i_eval/Kconfig.board

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+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GD32F450I_EVAL
+	bool "GigaDevice GD32F450I Evaluation Kit"
+	depends on SOC_GD32F450I

boards/arm/gd32f450i_eval/Kconfig.defconfig

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+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_GD32F450I_EVAL
+
+config BOARD
+	default "gd32f450i_eval"
+
+endif # BOARD_GD32F450I_EVAL

boards/arm/gd32f450i_eval/board.c

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+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+
+#include <gd32f4xx.h>
+
+/** Initialize the board's hardware through GD32 HAL */
+static int board_init(const struct device *dev)
+{
+	/* Enable GPIOA clock for PA9, PA10 */
+	rcu_periph_clock_enable(RCU_GPIOA);
+
+	/* Pin AF definition can be found in datasheet Device overview section */
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9);
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_10);
+
+	/* Configure USART0 Tx as alternate function push-pull */
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
+
+	/* Configure USART0 Rx as alternate function push-pull */
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_10);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
+
+	return 0;
+}
+
+SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

boards/arm/gd32f450i_eval/board.cmake

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+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=GD32F450IK")
+board_runner_args(jlink "--iface=JTAG")
+board_runner_args(jlink "--speed=4000")
+board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
+board_runner_args(jlink "--tool-opt=-autoconnect 1")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png

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+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <gigadevice/gd32f450ikh6.dtsi>
+
+/ {
+	model = "GigaDevice GD32F450I Evaluation Kit";
+	compatible = "gd,gd32f450i";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+
+	current-speed = <115200>;
+};

boards/arm/gd32f450i_eval/gd32f450i_eval.dts

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+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: gd32f450i_eval
+name: GigaDevice GD32F450I Evaluation Kit
+type: mcu
+arch: arm
+ram: 256
+flash: 3072
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools

boards/arm/gd32f450i_eval/gd32f450i_eval.yaml

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+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_GD32F4=y
+CONFIG_SOC_GD32F450I=y
+CONFIG_BOARD_GD32F450I_EVAL=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_CORTEX_M_SYSTICK=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y