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Phuc Phamkartben
Phuc Pham
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kartben
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drivers: adc: Initial support for RZ/G3S
Add ADC driver support for Renesas RZ/G3S Signed-off-by: Phuc Pham <[email protected]> Signed-off-by: Binh Nguyen <[email protected]>
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‎drivers/adc/CMakeLists.txt

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@@ -55,6 +55,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU adc_mcux_gau_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA adc_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RZ adc_renesas_rz.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MAX32 adc_max32.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD4114 adc_ad4114.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AD7124 adc_ad7124.c)

‎drivers/adc/Kconfig

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@@ -134,6 +134,8 @@ source "drivers/adc/Kconfig.ambiq"
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source "drivers/adc/Kconfig.renesas_ra"
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source "drivers/adc/Kconfig.renesas_rz"
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source "drivers/adc/Kconfig.max32"
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source "drivers/adc/Kconfig.ad4114"

‎drivers/adc/Kconfig.renesas_rz

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# Renesas RZ Family
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config ADC_RENESAS_RZ
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bool "Renesas RZ ADC Driver"
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default y
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depends on DT_HAS_RENESAS_RZ_ADC_ENABLED
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select USE_RZ_FSP_ADC
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help
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Enable the RZ ADC driver.

‎drivers/adc/adc_renesas_rz.c

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rz_adc
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#include <zephyr/drivers/adc.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include "r_adc_c.h"
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LOG_MODULE_REGISTER(adc_renesas_rz, CONFIG_ADC_LOG_LEVEL);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define ADC_RZ_MAX_RESOLUTION 12
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void adc_c_scan_end_isr(void);
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/**
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* @brief RZ ADC config
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*
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* This structure contains constant config data for given instance of RZ ADC.
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*/
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struct adc_rz_config {
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/** Mask for channels existed in each board */
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uint32_t channel_available_mask;
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/** Structure that handle FSP API */
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const adc_api_t *fsp_api;
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};
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/**
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* @brief RZ ADC data
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*
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* This structure contains data structures used by a RZ ADC.
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*/
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struct adc_rz_data {
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/** Structure that handle state of ongoing read operation */
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struct adc_context ctx;
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/** Pointer to RZ ADC own device structure */
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const struct device *dev;
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/** Structure that handle fsp ADC */
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adc_c_instance_ctrl_t fsp_ctrl;
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/** Structure that handle fsp ADC config */
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struct st_adc_cfg fsp_cfg;
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/** Structure that handle fsp ADC channel config */
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adc_c_channel_cfg_t fsp_channel_cfg;
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/** Pointer to memory where next sample will be written */
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uint16_t *buf;
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/** Mask with channels that will be sampled */
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uint32_t channels;
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/** Buffer id */
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uint16_t buf_id;
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};
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/**
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* @brief Setup channels before starting to scan ADC
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*
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* @param dev RZ ADC device
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* @param channel_cfg channel configuration (user-defined)
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*
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* @return 0 on success
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* @return -ENOTSUP if channel id or differential is wrong value
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* @return -EINVAL if channel configuration is invalid
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*/
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static int adc_rz_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg)
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{
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fsp_err_t fsp_err = FSP_SUCCESS;
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struct adc_rz_data *data = dev->data;
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const struct adc_rz_config *config = dev->config;
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if (!((config->channel_available_mask & BIT(channel_cfg->channel_id)) != 0)) {
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LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
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return -ENOTSUP;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Unsupported channel acquisition time");
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return -ENOTSUP;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Unsupported channel reference");
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return -ENOTSUP;
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}
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data->fsp_channel_cfg.scan_mask |= (1U << channel_cfg->channel_id);
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/** Enable channels. */
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config->fsp_api->scanCfg(&data->fsp_ctrl, &data->fsp_channel_cfg);
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if (FSP_SUCCESS != fsp_err) {
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* Interrupt handler
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*/
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static void adc_rz_isr(const struct device *dev)
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{
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struct adc_rz_data *data = dev->data;
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const struct adc_rz_config *config = dev->config;
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fsp_err_t fsp_err = FSP_SUCCESS;
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adc_channel_t channel_id = 0;
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uint32_t channels = 0;
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int16_t *sample_buffer = (int16_t *)data->buf;
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channels = data->channels;
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for (channel_id = 0; channels > 0; channel_id++) {
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/** Get channel ids from scan mask "channels" */
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if ((channels & 0x01) != 0) {
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/** Read converted data */
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config->fsp_api->read(&data->fsp_ctrl, channel_id,
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&sample_buffer[data->buf_id]);
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if (FSP_SUCCESS != fsp_err) {
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break;
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}
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data->buf_id = data->buf_id + 1;
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}
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channels = channels >> 1;
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}
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adc_c_scan_end_isr();
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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/**
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* @brief Check if buffer in @p sequence is big enough to hold all ADC samples
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*
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* @param dev RZ ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOMEM if buffer is not big enough
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*/
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static int adc_rz_check_buffer_size(const struct device *dev, const struct adc_sequence *sequence)
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{
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uint8_t channels = 0;
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size_t needed;
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channels = POPCOUNT(sequence->channels);
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needed = channels * sizeof(uint16_t);
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if (sequence->options) {
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needed *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed) {
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return -ENOMEM;
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}
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return 0;
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}
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/**
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* @brief Start processing read request
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*
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* @param dev RZ ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_rz_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_rz_start_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct adc_rz_config *config = dev->config;
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struct adc_rz_data *data = dev->data;
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int err;
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if (sequence->resolution > ADC_RZ_MAX_RESOLUTION || sequence->resolution == 0) {
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LOG_ERR("unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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if ((sequence->channels & ~config->channel_available_mask) != 0) {
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LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
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return -ENOTSUP;
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}
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err = adc_rz_check_buffer_size(dev, sequence);
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if (err) {
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LOG_ERR("buffer size too small");
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return err;
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}
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data->buf_id = 0;
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data->buf = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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adc_context_wait_for_completion(&data->ctx);
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return 0;
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}
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/**
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* @brief Start processing read request asynchronously.
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*
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* @param dev RZ ADC device
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* @param sequence ADC sequence description
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* @param async async pointer to asynchronous signal
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_rz_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_rz_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_rz_data *data = dev->data;
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int err;
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adc_context_lock(&data->ctx, async ? true : false, async);
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err = adc_rz_start_read(dev, sequence);
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adc_context_release(&data->ctx, err);
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return err;
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}
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/**
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* @brief Start processing read request synchronously.
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*
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* @param dev RZ ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_rz_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_rz_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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return adc_rz_read_async(dev, sequence, NULL);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_rz_data *data = CONTAINER_OF(ctx, struct adc_rz_data, ctx);
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const struct device *dev = data->dev;
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const struct adc_rz_config *config = dev->config;
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data->channels = ctx->sequence.channels;
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/** Start a scan */
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config->fsp_api->scanStart(&data->fsp_ctrl);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct adc_rz_data *data = CONTAINER_OF(ctx, struct adc_rz_data, ctx);
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if (repeat_sampling) {
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data->buf_id = 0;
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}
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}
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/**
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* @brief Function called on init for each RZ ADC device. It setups all
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* channels.
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*
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* @param dev RZ ADC device
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*
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* @return -EIO if error
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*
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* @return 0 on success
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*/
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static int adc_rz_init(const struct device *dev)
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{
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const struct adc_rz_config *config = dev->config;
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struct adc_rz_data *data = dev->data;
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fsp_err_t fsp_err = FSP_SUCCESS;
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/**Open the ADC module */
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config->fsp_api->open(&data->fsp_ctrl, &data->fsp_cfg);
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if (FSP_SUCCESS != fsp_err) {
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return -EIO;
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}
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/** Release context unconditionally */
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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/**
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* ************************* DRIVER REGISTER SECTION ***************************
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*/
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#define ADC_RZG_IRQ_CONNECT(idx, irq_name, isr) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, irq_name, irq), \
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DT_INST_IRQ_BY_NAME(idx, irq_name, priority), isr, \
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DEVICE_DT_INST_GET(idx), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(idx, irq_name, irq)); \
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} while (0)
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#define ADC_RZG_CONFIG_FUNC(idx) ADC_RZG_IRQ_CONNECT(idx, scanend, adc_rz_isr);
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#define ADC_RZG_INIT(idx) \
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static const adc_c_extended_cfg_t g_adc##idx##_cfg_extend = { \
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.trigger_mode = ADC_C_TRIGGER_MODE_SOFTWARE, \
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.trigger_source = ADC_C_ACTIVE_TRIGGER_EXTERNAL, \
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.trigger_edge = ADC_C_TRIGGER_EDGE_FALLING, \
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.input_mode = ADC_C_INPUT_MODE_AUTO, \
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.operating_mode = ADC_C_OPERATING_MODE_SCAN, \
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.buffer_mode = ADC_C_BUFFER_MODE_1, \
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.sampling_time = 100, \
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.external_trigger_filter = ADC_C_FILTER_STAGE_SETTING_DISABLE, \
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}; \
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static DEVICE_API(adc, adc_rz_api_##idx) = { \
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.channel_setup = adc_rz_channel_setup, \
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.read = adc_rz_read, \
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.ref_internal = DT_INST_PROP(idx, vref_mv), \
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IF_ENABLED(CONFIG_ADC_ASYNC, \
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(.read_async = adc_rz_read_async))}; \
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static const struct adc_rz_config adc_rz_config_##idx = { \
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.channel_available_mask = DT_INST_PROP(idx, channel_available_mask), \
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.fsp_api = &g_adc_on_adc, \
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}; \
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static struct adc_rz_data adc_rz_data_##idx = { \
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ADC_CONTEXT_INIT_TIMER(adc_rz_data_##idx, ctx), \
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ADC_CONTEXT_INIT_LOCK(adc_rz_data_##idx, ctx), \
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ADC_CONTEXT_INIT_SYNC(adc_rz_data_##idx, ctx), \
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.dev = DEVICE_DT_INST_GET(idx), \
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.fsp_cfg = \
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{ \
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.mode = ADC_MODE_SINGLE_SCAN, \
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.p_callback = NULL, \
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.p_context = NULL, \
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.p_extend = &g_adc##idx##_cfg_extend, \
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.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
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.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
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}, \
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.fsp_channel_cfg = \
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{ \
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.scan_mask = 0, \
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.interrupt_setting = ADC_C_INTERRUPT_CHANNEL_SETTING_ENABLE, \
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}, \
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}; \
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static int adc_rz_init_##idx(const struct device *dev) \
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{ \
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ADC_RZG_CONFIG_FUNC(idx) \
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return adc_rz_init(dev); \
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} \
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DEVICE_DT_INST_DEFINE(idx, adc_rz_init_##idx, NULL, &adc_rz_data_##idx, \
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&adc_rz_config_##idx, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&adc_rz_api_##idx)
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DT_INST_FOREACH_STATUS_OKAY(ADC_RZG_INIT);

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