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andyross
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boards/mediatek: Add mt8196_adsp
Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a very similar device to previous designs. Most of this patch is just DTS. The biggest delta is the more complicated second level interrupt controller, though it is still able to be represented using some vaguely clever DTS config over the older intc_mtk_adsp driver. Also the memory layout is slightly different, requiring a little indirection to set the initial boot stack address and log output buffer. And the timer "irq_ack" register bits moved. Signed-off-by: Andy Ross <[email protected]>
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‎boards/mediatek/mt8196/Kconfig.mt8196

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# Copyright 2024 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MT8196
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select SOC_MT8196

‎boards/mediatek/mt8196/board.yml

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boards:
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- name: mt8196
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vendor: mediatek
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socs:
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- name: mt8196

‎boards/mediatek/mt8196/mt8196_adsp.dts

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/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@4e100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x4e100000 DT_SIZE_K(512)>;
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};
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dram0: memory@90000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90000000 DT_SIZE_M(6)>;
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};
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dram1: memory@90700000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90700000 DT_SIZE_M(1)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0 4>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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/* The 8196 interrupt controller is actually more complicated
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* than the driver here supports. There are 64 total
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* interrupt inputs, each of which is a associated with one of
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* 16 "groups", each of which is wired to a separate Xtensa
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* architectural interrupt. (Whether the mapping of external
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* interrupts to groups is mutable is an open question, the
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* values here appear to be hardware defaults). We represent
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* each group (strictly each of the high and low 32 interrupts
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* of each group) as a separate adsp_intc controller, pointing
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* at the same status and enable registers, but with disjoint
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* masks. Note that this disallows configurations where a
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* single controller needs to manage interrupts in both the
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* high and low 32 bits of the set, but no current drivers
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* rely on such a configuration.
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*/
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intc_g1: intc_g1@1a014010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1a014010 4>;
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status-reg = <0x1a014008>;
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mask = <0x00007f3f>;
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interrupts = <1 0 0>;
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interrupt-parent = <&core_intc>;
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};
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intc_g2: intc_g2@1a014010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1a014010 4>;
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status-reg = <0x1a014008>;
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mask = <0x000000c0>;
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interrupts = <2 0 0>;
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interrupt-parent = <&core_intc>;
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};
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ostimer64: ostimer64@1a00b080 {
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compatible = "mediatek,ostimer64";
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reg = <0x1a00b080 28>;
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};
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ostimer0: ostimer@1a00b000 {
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compatible = "mediatek,ostimer";
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reg = <0x1a00b000 16>;
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interrupt-parent = <&intc_g1>;
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interrupts = <8 0 0>;
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};
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mbox0: mbox@1a360100 {
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compatible = "mediatek,mbox";
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reg = <0x1a360100 16>;
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interrupt-parent = <&intc_g2>;
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interrupts = <6 0 0>;
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};
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mbox1: mbox@1a370100 {
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compatible = "mediatek,mbox";
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reg = <0x1a370100 16>;
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interrupt-parent = <&intc_g2>;
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interrupts = <7 0 0>;
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};
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}; /* soc */
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chosen { };
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aliases { };
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};

‎boards/mediatek/twister.yaml

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name: MediaTek MT8188 Audio DSP
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mt8186/mt8186/adsp:
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name: MediaTek MT8186 Audio DSP
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mt8196/mt8196/adsp:
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name: MediaTek MT8196 Audio DSP

‎drivers/timer/mtk_adsp_timer.c

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#define OSTIMER_CON_CLKSRC_BCLK 0x20 /* CPU speed, 720 MHz */
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#define OSTIMER_CON_CLKSRC_PCLK 0x30 /* ~312 MHz experimentally */
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#ifndef CONFIG_SOC_MT8196
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#define OSTIMER_IRQ_ACK_ENABLE BIT(4) /* read = status, write = enable */
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#define OSTIMER_IRQ_ACK_CLEAR BIT(5)
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#else
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#define OSTIMER_IRQ_ACK_ENABLE BIT(0)
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#define OSTIMER_IRQ_ACK_CLEAR BIT(5)
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#endif
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#define OST64_HZ 13000000U
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#define OST_HZ 26000000U

‎soc/mediatek/mt8xxx/Kconfig.soc

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help
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Mediatek MT818x Audio DSPs
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config SOC_SERIES_MT8196
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bool
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select SOC_FAMILY_MTK
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help
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Mediatek MT8196 Audio DSPs
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config SOC_MT8195
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bool
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select SOC_SERIES_MT8195
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bool
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select SOC_SERIES_MT818X
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config SOC_MT8196
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bool
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select SOC_SERIES_MT8196
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config SOC
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default "mt8195" if SOC_MT8195
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default "mt8186" if SOC_MT8186
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default "mt8188" if SOC_MT8188
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default "mt8196" if SOC_MT8196

‎soc/mediatek/mt8xxx/irq.c

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__ASSERT_NO_MSG((*irq_inout & 0xff) == 23);
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*irq_inout = (*irq_inout >> 8) - 1;
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return DEVICE_DT_GET(DT_INST(1, mediatek_adsp_intc));
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#elif defined(CONFIG_SOC_SERIES_MT8196)
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/* Two subcontrollers on core IRQs 1 and 2 */
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uint32_t lvl1 = *irq_inout & 0xff;
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*irq_inout = (*irq_inout >> 8) - 1;
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if (lvl1 == 1) {
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return DEVICE_DT_GET(DT_INST(0, mediatek_adsp_intc));
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}
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__ASSERT_NO_MSG(lvl1 == 2);
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return DEVICE_DT_GET(DT_INST(1, mediatek_adsp_intc));
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#else
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/* Only one on 818x */
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return DEVICE_DT_GET(DT_INST(0, mediatek_adsp_intc));

‎soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig

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# Copyright 2024 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MT8196
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config LEGACY_MULTI_LEVEL_TABLE_GENERATION
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default n
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config NUM_2ND_LEVEL_AGGREGATORS
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default 2
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config 2ND_LVL_INTR_00_OFFSET
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default 1
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config 2ND_LVL_INTR_01_OFFSET
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default 2
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endif

‎soc/mediatek/mt8xxx/mt8196/linker.ld

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/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "../linker.ld"

‎soc/mediatek/mt8xxx/mt8196/soc.h

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/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_MT8196_SOC_H
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#define ZEPHYR_SOC_MT8196_SOC_H
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#include "../soc.h"
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#endif /* ZEPHYR_SOC_MT8196_SOC_H */

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