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drivers: pwm: Add support for cc23x0 LGPT PWM
Add PWM support for LGPT0, LGPT1, LGPT2 and LGPT3 for cc23x0 SoC. Signed-off-by: Stoyan Bogdanov <[email protected]>
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‎drivers/pwm/CMakeLists.txt

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@@ -6,6 +6,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_PWM_TELINK_B91 pwm_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CC13XX_CC26XX_TIMER pwm_cc13xx_cc26xx_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CC23X0_TIMER pwm_cc23x0_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_STM32 pwm_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRF_SW pwm_nrf_sw.c)

‎drivers/pwm/Kconfig

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@@ -36,6 +36,8 @@ source "drivers/pwm/Kconfig.b91"
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source "drivers/pwm/Kconfig.cc13xx_cc26xx_timer"
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source "drivers/pwm/Kconfig.cc23x0_timer"
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source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.sifive"

‎drivers/pwm/Kconfig.cc23x0_timer

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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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config PWM_CC23X0_TIMER
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bool "TI SimpleLink CC23x0 LGPT PWM driver"
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default y
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depends on DT_HAS_TI_CC23X0_LGPT_PWM_ENABLED
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select PINCTRL
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help
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Enables TI SimpleLink CC23x0 LGPT PWM driver.

‎drivers/pwm/pwm_cc23x0_timer.c

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/*
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_lgpt_pwm
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/pwm.h>
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#include <driverlib/gpio.h>
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#include <driverlib/clkctl.h>
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#include <inc/hw_lgpt.h>
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#include <inc/hw_lgpt1.h>
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#include <inc/hw_lgpt3.h>
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#include <inc/hw_types.h>
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#include <inc/hw_evtsvt.h>
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#include <inc/hw_memmap.h>
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#include <zephyr/logging/log.h>
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#define LOG_MODULE_NAME pwm_cc23x0_lgpt
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
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#define LGPT_CLK_PRESCALE(pres) ((pres + 1) << 8)
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struct pwm_cc23x0_data {
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uint32_t prescale;
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uint32_t base_clk;
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};
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struct pwm_cc23x0_config {
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const uint32_t base; /* LGPT register base address */
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const struct pinctrl_dev_config *pcfg;
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};
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static int pwm_cc23x0_set_cycles(const struct device *dev, uint32_t channel, uint32_t period,
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uint32_t pulse, pwm_flags_t flags)
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{
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const struct pwm_cc23x0_config *config = dev->config;
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LOG_DBG("set cycles period[%x] pulse[%x]", period, pulse);
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if ((config->base != LGPT3_BASE) && (pulse > 0xffff || period > 0xffff || pulse > period)) {
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/* LGPT0, LGPT1, LGPT2 - 16bit counters */
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LOG_ERR("Period of pulse out of range");
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return -EINVAL;
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} else if (pulse > 0xffffff || period > 0xffffff || pulse > period) {
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/* LGPT3 - 24bit counter */
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LOG_ERR("Period of pulse out of range");
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return -EINVAL;
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}
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if (channel == 0) {
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HWREG(config->base + LGPT_O_C0CC) = pulse;
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HWREG(config->base + LGPT_O_C0CFG) = 0x100 | 0xB;
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} else if (channel == 1) {
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HWREG(config->base + LGPT_O_C1CC) = pulse;
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HWREG(config->base + LGPT_O_C1CFG) = 0x200 | 0xB;
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} else if (channel == 2) {
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HWREG(config->base + LGPT_O_C2CC) = pulse;
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HWREG(config->base + LGPT_O_C2CFG) = 0x400 | 0xB;
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} else {
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LOG_ERR("Invalid chan ID");
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return -ENOTSUP;
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}
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/* get it from flags */
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HWREG(config->base + LGPT_O_CTL) = LGPT_CTL_MODE_UPDWN_PER;
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HWREG(config->base + LGPT_O_TGT) = period;
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/* Activate LGPT */
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HWREG(config->base + LGPT_O_STARTCFG) = 0x1;
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return 0;
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}
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static int pwm_cc23x0_get_cycles_per_sec(const struct device *dev, uint32_t channel,
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uint64_t *cycles)
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{
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struct pwm_cc23x0_data *data = dev->data;
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*cycles = data->base_clk / (data->prescale + 1);
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return 0;
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}
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static const struct pwm_driver_api pwm_cc23x0_driver_api = {
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.set_cycles = pwm_cc23x0_set_cycles,
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.get_cycles_per_sec = pwm_cc23x0_get_cycles_per_sec,
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};
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static int pwm_cc23x0_activate_clock(const struct device *dev)
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{
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const struct pwm_cc23x0_config *config = dev->config;
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struct pwm_cc23x0_data *data = dev->data;
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uint32_t lgpt_clk_id = 0;
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switch (config->base) {
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case LGPT0_BASE:
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lgpt_clk_id = CLKCTL_LGPT0;
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break;
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case LGPT1_BASE:
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lgpt_clk_id = CLKCTL_LGPT1;
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break;
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case LGPT2_BASE:
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lgpt_clk_id = CLKCTL_LGPT2;
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break;
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case LGPT3_BASE:
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lgpt_clk_id = CLKCTL_LGPT3;
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break;
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default:
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return -EINVAL;
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}
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CLKCTLEnable(CLKCTL_BASE, lgpt_clk_id);
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HWREG(config->base + LGPT_O_PRECFG) = LGPT_CLK_PRESCALE(data->prescale);
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HWREG(EVTSVT_BASE + EVTSVT_O_LGPTSYNCSEL) = EVTSVT_LGPTSYNCSEL_PUBID_SYSTIM0;
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return 0;
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}
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#define DT_TIMER(idx) DT_INST_PARENT(idx)
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#define DT_TIMER_BASE_ADDR(idx) (DT_REG_ADDR(DT_TIMER(idx)))
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static int pwm_cc23x0_init(const struct device *dev)
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{
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const struct pwm_cc23x0_config *config = dev->config;
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int ret;
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LOG_DBG("PWM cc23x0 base=[%x]", config->base);
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("[ERR] failed to setup PWM pinctrl");
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return ret;
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}
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pwm_cc23x0_activate_clock(dev);
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return 0;
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}
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#define PWM_DEVICE_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_PWM_LOG_LEVEL); \
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\
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static const struct pwm_cc23x0_config pwm_cc23x0_##idx##_config = { \
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.base = DT_TIMER_BASE_ADDR(idx), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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}; \
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\
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static struct pwm_cc23x0_data pwm_cc23x0_##idx##_data = { \
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.prescale = DT_PROP(DT_INST_PARENT(idx), clk_prescale), \
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.base_clk = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, pwm_cc23x0_init, NULL, &pwm_cc23x0_##idx##_data, \
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&pwm_cc23x0_##idx##_config, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_cc23x0_driver_api)
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DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT);

‎dts/bindings/pwm/ti,cc23x0-lgpt-pwm.yaml

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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI CC23x0 LGPT PWM Controller Node
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&lgpt0 {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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pinctrl-0 = <&pwm0_default>;
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pinctrl-names = "default";
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};
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Note: PWM0-PWM8 are 16bit without prescale, max timeout is 1365100 ns
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PWM9-PWM11 are 24bit without prescale, max timeout is 349519750 ns
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compatible: "ti,cc23x0-lgpt-pwm"
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include: [base.yaml, pwm-controller.yaml, pinctrl-device.yaml]
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properties:
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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pwm-cells:
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- channel
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- period
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- flags

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