Enabling ADC3 peripheral in stm32f303 family MCUs #61263
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I have been trying to enable ADC3 on a the stm32f303 family MCU, but I am not sure whether it is possible. If it isn't, I think this should be opened as an issue. I tried doing this specifically on two hardware boards:
They don't use the exact same device tree but they are very similar. I will take the stm32f3_disco as my example to explain my issues. I noticed in these device trees (more specifically, stm32f303.dtsi) that the ADC1 and ADC2 peripheral are defined, but not the ADC3 and ADC4, which are present in the stm32f303xc variants (as specified in the datasheet), and therefore I think they should be defined there. So I created an overlay for the stm32f3_disco board in the samples/drivers/adc project. Configured as such: / {
zephyr,user {
/* adjust channel number according to pinmux in board.dts */
//io-channels = <&adc1 1>, <&adc1 2>;
io-channels = <&adc3 12>;
//io-channels = <&adc4 4>;
};
};
&adc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&adc1_in1_pa0 &adc1_in2_pa1>;
pinctrl-names = "default";
status = "okay";
channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
};
channel@2 {
reg = <2>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
};
};
/ {
soc {
adc3: adc@50000400 {
compatible = "st,stm32-adc";
reg = <0x50000400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&adc3_in12_pb0>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
interrupts = <47 0>;
status = "okay";
vref-mv = <3000>;
#io-channel-cells = <1>;
vref-channel = <18>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <2 3 5 8 20 62 182 602>;
channel@12 {
reg = <12>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
};
};
adc4: adc@50000500 {
compatible = "st,stm32-adc";
reg = <0x50000500 0x4c>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&adc4_in4_pb14>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
interrupts = <61 0>;
status = "okay";
vref-mv = <3000>;
#io-channel-cells = <1>;
vref-channel = <18>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <2 3 5 8 20 62 182 602>;
channel@4 {
reg = <4>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
};
};
};
};If I use the channels configured on ADC1, it works normally. However if I try using the channels configured on ADC3 it doesn't work. Zephyr compiles and runs, but the output hangs after this: I went over my overlay configuration countless times, and I don't see if there is anything wrong. I am wondering if maybe this is a driver issue, that doesn't support ADC3 for this MCU family. However, trying to understand that from reading the Am I doing something wrong or is this actually a lack of support in the driver? If so how could it be enabled? It seems to me this should be possible since the ADC3 and ADC4 peripheral are very similar to ADC1 and ADC2. |
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Replies: 2 comments 4 replies
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I have tested with ADC3 channel12 of the stm32f3_disco, I can read the adc value (samples/drivers/adc) when connecting pin PB0 to GND or to 3V: Note that See branch : https://github.com/FRASTM/zephyr/tree/stm32f3_disco_adc3 |
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Thank you very much for you reply, I didn't think to try disabling ADC1. Only being able to use one of the ADC instances is a pretty big limitation though. In my application, I would need ADC2 and ADC3 to be both enabled. Is this possible? |
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Hello @flabou, The problem lies in the fact that ADC1 and ADC2 share the same interrupt line (18) on STM32F303 while ADC3 and ADC4 use respectively line 47 and 61. On STM32F303, by default the Kconfig ADC_STM32_SHARED_IRQS is enabled. This allows using both ADC1 and ADC2. But it prevents the use of ADC3 and ADC4. You can have up to 3 active ADC by disabling this Kconfig. In this case, you'll have access to ADC3, ADC4 and either one of ADC1 or ADC2 (but not both). Unfortunately, there is yet no existing way in Zephyr to handle such cases of mixed interrupt sharing so we have to workaround it. Hope this helps! |
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Dear Gautier, Do you think this will ever be fixed? I don't think it's so uncommon to have shared interrupt for some instances and no shared interrupt with some other instance that it wouldn't make sense to handle this, but I am not sure. If you don't mind, another question to help me learn to better navigate the zephyr documentation and code, where should I have looked to find this on my own? |
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There are several PR that try to solve this problem, like this recent one #61422, inspired by #57146, itself a continuation of #49427. None of them have been merged yet. It is not uncommon but rather complex to implement a solution that keep things relatively simple. Like you, I also look forward to a solution. As for your second question, I'd say it mostly comes with practice. I was able to answer you quickly because I already encountered the issue and knew what the problem was. In a case like this, it's about knowing the quirks of the specific driver (I've worked quite a bit on the ADC driver these past months, and still have some work to do) and I don't think it's properly documented anywhere but by understanding the code itself. |
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Thank you, it is reassuring to know that it is being worked on! Zephyr's documentation is good in some ways, but I think it would be nice to have a place for this kind of information. Maybe on the API reference page specific to the driver? I guess it's automated with doxygen documentation but it would be nice to have some introduction with additional details. Or some other place, I am not sure where it would be best. |
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Hello @flabou,
The problem lies in the fact that ADC1 and ADC2 share the same interrupt line (18) on STM32F303 while ADC3 and ADC4 use respectively line 47 and 61. On STM32F303, by default the Kconfig ADC_STM32_SHARED_IRQS is enabled. This allows using both ADC1 and ADC2. But it prevents the use of ADC3 and ADC4.
You can have up to 3 active ADC by disabling this Kconfig. In this case, you'll have access to ADC3, ADC4 and either one of ADC1 or ADC2 (but not both). Unfortunately, there is yet no existing way in Zephyr to handle such cases of mixed interrupt sharing so we have to workaround it.
Hope this helps!