lpcxpresso55s16 gets stuck in CLOCK_IsPLL1Locked() after PR #53754

[DerekSnell]

I am creating this discussion on behalf of @tyalie , who reported:

Hey. This commit (#53754) broke the lpcxpresso55s16 dev board for me. The program gets stuck in the CLOCK_IsPLL1Locked() function in the fsl_clock.h file.

@tyalie , I do not see the same issue. Can you please elaborate on how to replicate the issue? What revision of the lpcxpresso55s16 board are you using? A sticker on my board says the SCH-46431 schematic revision is Rev.B1. And it sounds like this board works for you with a previous commit? Does your board work with CONFIG_INIT_PLL1=n using this new commit or later? Are you able to probe the 16MHz crystal Y2 on the board, and see if it is oscillating?

I am using the latest commit in main (12e79ca), and I built a sample application for the lpcxpresso55s16 board. By default CONFIG_INIT_PLL1=y and the startup code initializes PLL1 and uses that clock, and the sample runs fine for me.

And FYI, there is an open PR that is working to change this PLL1 frequency, see #60812 . I doubt this impacts your issue, but I wanted you to be aware.

Thanks

[tyalie]

Hi. I'll fully test it tomorrow when I'm with the hardware, because it isn't really the evk but a board that should be similar enough. It works with the lpc55s16 evk board definitions when this commit is not applied thoo. We have the evk flying around thoo so I'll fully bisect the problem and report back here.

[DerekSnell]

Hi @tyalie ,
Thank you for confirming your issue is with a different, custom board.

Does your board have a crystal connected to the clock oscillator pins? If not, that would explain the issue. One change made in #53754 is to clock these MCUs at their maximum frequency by default. For the LPC55S16, that is 150 MHz. But that frequency requires using the PLL. And this clock config in soc.c clocks the PLL from the external crystal. Before this PR, I believe MCU was clocked from the internal FRO at 96 MHz, and the external crystal may not have been used.

If your board does not have a crystal, you can configure CONFIG_INIT_PLL1=n. That will not enable PLL1 or the crystal clock source, and will clock from the internal FRO at 96 MHz.

And for future reference, when you report issues or details like this, please specify the hardware platform that is used. When you wrote:

This commit broke the lpcxpresso55s16 dev board for me.

We assumed you saw the issue on the NXP board named lpcxpresso55s16 . I spent time debugging with this board to try and replicate the issue.

Let us know what you find. Best regards

[tyalie]

Hi @DerekSnell,

thank you for your quick reply. You were right. Looking into it, I found that we are missing an external crystal on our own boards which of course means that we won't be able to use an external clock source. Thank you for your quick help here.

And for future reference, when you report issues or details like this, please specify the hardware platform that is used.

Yeah I'm very sorry. I was a bit in a stress situation and did not find the time to really look into it / compare it against the actual evk / make an actual issue / … and just assumed that we copied the design 1:1. I'm very sorry for my faulty description / non conventional way of reporting it and the additional stress I caused through that. I'll be more mindful in the future.

Best regards
Tyalie

[DerekSnell]

Hi @tyalie ,
Thanks for confirming the issue. Best regards