Assessment of the difficulty in porting CPU architecture for zephyr

[wangyuliu]

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. In fact, the tool may have an average estimate of various architecture porting efforts.My focus is on the overall workload and difficulty of transplantation in the past and future,even if a project has already been ported.As part of my dataset, I have collected the zephyr project. I would like to gather community opinions to support my assessment. I appreciate your help and response! Based on scanning tools, the porting complexity is determined to be moderate, with a moderate amount of code related to the CPU architecture in the project. Is this assessment accurate?Do you have any opinions on personnel allocation and consumption time？ I look forward to your help and response.

[josuah]

Hello! By CPU architectures, could you point at one in particular?

New architecture family

Adding a directory in https://github.com/zephyrproject-rtos/zephyr/tree/main/arch ? I.e. adding AVR support?

For extending a CPU architectures or introducing a new one, it is typically about writing a few assembly for startup and a few tasks not reachable from C, like context swap, sometimes initialization (crt0.S), and a heap of compiler and linker optons.

A bit about wrapping a Makefile RTOS Hello World into Zephyr format.

New architecture variant

Such as adding support for a new family of ARM Cortex MCU, like adding a line here?

zephyr/modules/cmsis/cmsis_core_m.h

Lines 49 to 67 in 026dbdf

	#if defined(CONFIG_CPU_CORTEX_M0)
	#define __CM0_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
	#define __CM0PLUS_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M1)
	#define __CM1_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M3)
	#define __CM3_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M4)
	#define __CM4_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M7)
	#define __CM7_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M23)
	#define __CM23_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M33)
	#define __CM33_REV 0
	#elif defined(CONFIG_CPU_CORTEX_M55)
	#define __CM55_REV 0
	#else

This is less difficult than adding a new arch family, but could encounter particular challenges associated with what is needed to modify, and good GCC compiler knowledge (if GCC is used).

New SoC

Did you mean an SoC? Like adding one particular chip/MCU family?

This might be a matter of writing each missing driver, and adding device trees.