How to use the PLL fractional mode in the STM32U5 board

[jandriea]

Hello everyone,

I am new to Zephyr and excited to try it on my custom board.

However, my custom board uses a unique HSE Clock value (16777216 Hz) and it seems like I can't find any example that uses the PLL in fractional mode. After some digging into the Zephyr code base, I found out that the fractional mode is disabled. Like this code from https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/clock_control/clock_stm32_ll_u5.c

        LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);

	LL_RCC_PLL1FRACN_Disable();

	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
		LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
		LL_RCC_PLL1_EnableDomain_SAI();
	}

	if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
		LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
		LL_RCC_PLL1_EnableDomain_48M();
	}

	if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
		__ASSERT_NO_MSG((STM32_PLL_R_DIVISOR == 1) ||
				(STM32_PLL_R_DIVISOR % 2 == 0));
		LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
		LL_RCC_PLL1_EnableDomain_SYS();
	}

	LL_RCC_PLL1_Enable();

Any idea why it is disabled? Does Zephyr not support the PLL fractional mode?

Thank you for your help

[erwango]

Indeed, for now this isn't implemented (because not required/requested until now)
Don't hesitate to add it, contributions are always welcome (my request would be to enable configuration via device tree (if it makes sense) and add a dedicated test here).

[jandriea]

Thank you for your reply.

I will try to read the project structure and implement the PLL fractional mode