IRQ_CONNECT: build error "gen_isr_tables.py: error: multiple registrations at table_index [...]" #65786
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BrunoMelaneoVolpi
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I confirm
Most likely the code you're using enabled DMA2 from dma_stm32.c drivers which is itself enabling this IRQ, eventually colliding with your code. |
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Hi everyone,
apologies if this question has already been posed somewhere but unfortunately I was not able to find the answer I am looking for...
In a nutshell, I am trying to use some hardware functionalities provided by some STM32 timers (STM32F7 / nucleo STM32F746zg in my case).
Because my application is time critical, I am aiming to use the hardware as much as possible.
My objective is to:
This way the MCU timers hardware does almost everything without any software intervention except for a DMA ISR.
I was able to prototype this implementation using a bare metal STM HAL.
Because it worked as expected, I am now trying to incorporate this into my Zephyr work project.
If my research (sniffing Zephyr's code) is correct, these timer-chaining features are not supported by Zephyr and/or its STM32 drivers. (Can anyone confirm?)
As such, I am trying to incorporate� the bare metal prototype directly. Because STM's HAL/LL is used at Zephyr driver level I assumed this could be a valid way forward.
The problem I am facing is that I got to a point where I must register the DMA callback and I am not able to.
I am trying to use IRQ_CONNECT() to register my DMA callback as follows:
... but I get the following build error:
My implementation should be the only one using the DMA2_Stream0 IRQ.
As such, I was wondering if someone could lead/support me :
Using the CONFIG_SHARED_INTERRUPTS does not seem the correct option because as mentioned:
https://docs.zephyrproject.org/latest/kernel/services/interrupts.html#sharing-interrupt-lines
... its usage carries some penalties:
"[...]Please note that enabling CONFIG_SHARED_INTERRUPTS will result in a non-negligible increase in the binary size. Use with caution.[...]"
Moreover, this interrupt line sharing would cause the other unwanted ISR to be executed as well:
"[...]the interrupt line will become shared, meaning the two ISR/argument pairs (previous one and the one that has just been registered) will be invoked each time the interrupt is triggered[...]"
... which could affect my application timings
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