stm32h747i_disco_m7 screen periodcally (~10 sec) flickering

[cameled]

When I run samples/drivers/display application on stm32h747i_disco_m7 boards, screen periodically flickering, about 10 seconds.

I'm tring to find why this happened. Any suggestions would be highly appreciated.

[erwango]

I'd suggest to investigate clocks and try to use the most stable you'll find.

[cameled]

Thanks!

[cameled]

Still working on this problem. I have check the LTDC and DSI configuration, looks same as LCD_DSI_VideoMode_DoubleBuffering example on stm32cubeh7.

I try to disable the ltdc buffer update, but flickering still exist.

So, looks there have some config lost between ltdc and dsi, or otm8009a. EDIT: Same as STM32CubeH7

[cameled]

After compared display_otm8009a driver and STM32CubeH7 OTM8009A_Init, I found there have some difference between them.

diff --git a/drivers/display/display_otm8009a.c b/drivers/display/display_otm8009a.c
index 2463b43114..f683578e46 100644
--- a/drivers/display/display_otm8009a.c
+++ b/drivers/display/display_otm8009a.c
@@ -97,7 +97,7 @@ static int otm8009a_configure(const struct device *dev)
        uint8_t buf[4];
        int ret;
 
-       static const uint8_t pwr_ctrl2[] = {0x96, 0x34, 0x01, 0x33, 0x33, 0x34, 0x33};
+       static const uint8_t pwr_ctrl2[] = {0x96, 0x34, 0x01, 0x33, 0x33, 0x34, 0x43};
        static const uint8_t sd_ctrl[] = {0x0D, 0x1B, 0x02, 0x01, 0x3C, 0x08};
        static const uint8_t goavst[] = {
                0x85, 0x01, 0x00, 0x84, 0x01, 0x00, 0x81, 0x01, 0x28, 0x82, 0x01, 0x28
@@ -185,12 +185,13 @@ static int otm8009a_configure(const struct device *dev)
 
        /* source driver precharge control */
        buf[0] = 0x30;
-       buf[1] = 0x8A;
-       ret = otm8009a_mcs_write(dev, OTM8009A_MCS_SD_PCH_CTRL, buf, 2);
+       ret = otm8009a_mcs_write(dev, OTM8009A_MCS_SD_PCH_CTRL, buf, 1);
        if (ret < 0) {
                return ret;
        }
 
+       k_msleep(10);
+
        /* not documented */
        buf[0] = 0x40;
        ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC1, buf, 1);
@@ -198,6 +199,8 @@ static int otm8009a_configure(const struct device *dev)
                return ret;
        }
 
+       k_msleep(10);
+
        /* power control settings 4 for DC voltage settings */
        /* enable GVDD test mode */
        buf[0] = 0x04;
@@ -324,7 +327,7 @@ static int otm8009a_configure(const struct device *dev)
 
        /* not documented */
        buf[0] = 0x00;
-       ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC2, buf, 3);
+       ret = otm8009a_mcs_write(dev, OTM8009A_MCS_NO_DOC2, buf, 1);
        if (ret < 0) {
                return ret;
        }
@@ -404,7 +407,7 @@ static int otm8009a_configure(const struct device *dev)
        /* Pump 1 min and max DM */
        buf[0] = 0x08;
        buf[1] = 0x66;
-       buf[2] = 0x83;
+       buf[2] = 0x80;
        buf[3] = 0x00;
        ret = otm8009a_mcs_write(dev, OTM8009A_MCS_PWR_CTRL1, buf, 4);
        if (ret < 0) {
@@ -447,6 +450,8 @@ static int otm8009a_configure(const struct device *dev)
                return ret;
        }
 
+       k_msleep(10);
+
        /* exit sleep mode */
        ret = otm8009a_dcs_write(dev, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
        if (ret < 0) {

[cameled]

Adjust sys_ck can effect the time, 400MHz 10 sec, 200MHz 20 sec, 100MHz is 40 sec.

[cameled]

Meanwhile, If I disable the dcache, flicker disappeared.

Note, frame buffer udpate is disabled, there no frame buffer sync issue in here. If dcache is enabled, it will effect LTDC frame buffer rendering.

[cameled]

@erwango Any idea about this behavior?

[cameled]

Refer AN4861 4.6, add FMC_Bank1->BTCR[0] = 0x000030D2; to the end of memc_stm32_init() solve this problem.

[erwango]

Good job! Would you mind creating an issue to fix this in tree ?

[cameled]

Sure, I also want to add frame buffer number config to ltdc, like nxp, support 0 ~ 2 frame buffer. So, maybe latter to do it.