Display LTDC when using SDRAM have error (STM32H7)

[hanh-nn]

Describe the bug

I'm using stm32h743iit6 and create my own DTS. When i use internal ram for LTDC( by disabling the line "ext-sdram = <&sdram1>;" ), the screen work perfect ( I must reduce size of screen because the internal ram not enough). However, when i use external ram for LTDC, the screen sometime have error. I don't know what happen.
I have try to change the clock of LTDC and when it reduce about 7Mhz. The error not occur, but that frequency is so slow for screen. I can see the screen is blinking.
I also change the clock of SDRAM, but nothing happen (I have check write/read the external ram, so i think it not problem)
I'm using zephyr-sdk-0.16.4_linux-x86_64 and the master branch of zephyrproject

Error happen:

error_exram_ltdc.mp4

Describe DTS

Here is my ltdc:

&ltdc {
	pinctrl-0 = <
				&ltdc_r3_ph9
				&ltdc_r4_ph10 &ltdc_r5_ph11 &ltdc_r6_ph12 &ltdc_r7_pg6

				&ltdc_g2_ph13 &ltdc_g3_ph14
				&ltdc_g4_ph15 &ltdc_g5_pi0 &ltdc_g6_pi1 &ltdc_g7_pi2

				&ltdc_b3_pg11
				&ltdc_b4_pi4 &ltdc_b5_pi5 &ltdc_b6_pi6 &ltdc_b7_pi7
				
				&ltdc_de_pf10 &ltdc_clk_pg7	&ltdc_hsync_pi10 &ltdc_vsync_pi9
				>;
	pinctrl-names = "default";
	ext-sdram = <&sdram1>;
	status = "okay";

	width = <800>;
	height = <480>;
	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
	bl-ctrl-gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
	display-timings {
		compatible = "zephyr,panel-timing";
		de-active = <0>;
		pixelclk-active = <0>;
		hsync-active = <0>;
		vsync-active = <0>;
		hsync-len = <1>;
		vsync-len = <1>;

		hback-porch = <46>;
		vback-porch = <23>;
		hfront-porch = <210>;
		vfront-porch = <22>;
	};
	def-back-color-red = <0xFF>;
	def-back-color-green = <0xFF>;
	def-back-color-blue = <0xFF>;
};

And SDRAM:

&fmc {
	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
		     &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
		     &fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15

		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
			 &fmc_a14_pg4 &fmc_a15_pg5

			 &fmc_d0_pd14 &fmc_d1_pd15
		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
		     &fmc_d15_pd10>;
	pinctrl-names = "default";
	status = "okay";

	sdram {
		status = "okay";
		power-up-delay = <1000>;
		num-auto-refresh = <8>;
		mode-register = <0x220>;
		refresh-rate = <1667>;
		bank@0 {
			reg = <0>;
			st,sdram-control = <STM32_FMC_SDRAM_NC_9
						STM32_FMC_SDRAM_NR_13
						STM32_FMC_SDRAM_MWID_16
						STM32_FMC_SDRAM_NB_4
						STM32_FMC_SDRAM_CAS_2
						STM32_FMC_SDRAM_SDCLK_PERIOD_2
						STM32_FMC_SDRAM_RBURST_ENABLE
						STM32_FMC_SDRAM_RPIPE_0>;
			st,sdram-timing = <2 6 4 6 2 2 2>;
		};
	};
};

i config clock for ltdc:

&pll3 {
	status = "okay";
	clocks = <&clk_hse>;
	div-m = <5>;
	mul-n = <48>;
	div-p = <2>;
	div-q = <5>;
	div-r = <15>; /* clock ltdc 16Mhz */
};

and clock for SDRAM:

// for using pll2r
RCC->D1CCIPR &= 0xfffffffc;
RCC->D1CCIPR |= 2;

&pll2 {
	status = "okay";
	clocks = <&clk_hse>;
	div-m = <2>;
	mul-n = <32>;
	div-p = <2>;
	div-q = <2>;
	div-r = <2>; /* clock sdram chosen: 200Mhz */
};

I'm new on zephyr, so any idea are welcome. Thanks!

[hanh-nn]

This PR solve the issue: #66513