STM32 qspi memmory mapped flash + UART DMA issues

[xhpohanka]

Hello,

I have a project with stm32h750 where the code is run from external qspi flash. That means in normal situation the qspi runs in memory mapped mode. Because we need occasionally write the flash we have a mechanism when part of code located in RAM aborts the memory mapping, writes the flash and reenable memory mapping again.

Now we are thinking of using DMA for some large data transfers over uart, which can be quite easily enabled but I found that it collides with our flash writing mechanism. The easiest way to try uart DMA was to enable LOG_BACKEND_UART_ASYNC (on stm32h7 it needs to fix zephyr code and mark internal buffer as __nocache but that's a different story).

With async uart I'm getting Precise data bus error on any flash write attempt. My guess is that the DMA get's confused and maybe should be paused during the flash write operation, but I don't know yet, how to do that.

Can anyone give me some hint?

The code for writing the flash is following (simplified)

__ramfunc static uint32_t __qspi_abort_mm(struct flash_qspi_dev_data *devdata)
{
	__disable_irq();
	// what about DMA???

#if defined(RAM_TRAMPOLINE_DISABLE_CACHE)
	SCB_DisableDCache();
	SCB_DisableICache();
#endif

	uint32_t ccr_backup = QUADSPI->CCR;

	qspi_abort();
	devdata->memory_mapped = false;
	devdata->busy = 0;

	return ccr_backup;
}

static __ramfunc void __qspi_start_mm(struct flash_qspi_dev_data *devdata, bool restore, uint32_t ccr_backup)
{
	if (devdata->busy != 0)
		qspi_abort();

	devdata->busy = 1;

	// enable memory mapped again
	while ((QUADSPI->SR & QSPI_FLAG_BUSY) != 0) ; // TODO timeout
	QUADSPI->CCR = ccr_backup;

#if defined(RAM_TRAMPOLINE_DISABLE_CACHE)
	SCB_EnableICache();
	SCB_EnableDCache();
#endif

	__enable_irq();

	devdata->memory_mapped = true;
}

__ramfunc static int __flash_qspi_write(struct flash_qspi_dev_data *devdata, off_t offset,
					const void *data, size_t size)
{
	const uint8_t *data8 = data;
	uint32_t ccr_backup;

	ccr_backup = __qspi_abort_mm(devdata);

	while (size > 0) {
		// ... qspi commands
	}

	__qspi_start_mm(devdata, true, ccr_backup);

	return 0;
}

static int flash_qspi_write(const struct device *dev, off_t offset,
			    const void *data, size_t len)
{
	int rc;
	struct flash_qspi_dev_data *const devdata = DEV_DATA(dev);

	LOG_DBG("offset = 0x%lx, len = %zu", (long)offset, len);

	if (!flash_qspi_valid_range(dev, offset, len)) {
		return -EINVAL;
	}

	if (!len) {
		return 0;
	}

	k_sem_take(&devdata->sem, K_FOREVER);

	rc = __flash_qspi_write(devdata, offset, data, len);
	SCB_InvalidateDCache_by_Addr((uint32_t *)(QSPI_BASE + offset), len);

	k_sem_give(&devdata->sem);

	return rc;
}