Misuse of STM (User registers)

[mwsealey]

https://github.com/zephyrproject-rtos/zephyr/blame/6551492a3ffe72e57bbf6b826b84316d9ddeb9d3/arch/arm/core/cortex_a_r/macro_priv.inc#L36

    srsdb sp!, #MODE_SYS
	cps #MODE_SYS
	stmdb sp, {r0-r3, r12, lr}^
	sub sp, #24

In this snippet the code intent seems to be to put the LR_cur and SP_cur onto the SYStem mode stack, then changes to SYStem mode and attempts to store r0-r3, r12, LR(_usr) onto the SYStem mode stack afterwards. The sub sp, #24 bumps the stack pointer because the caret form of the STM instruction doesn't support writeback forms.

This is not only unnecessary work the caret instruction form is intended for use in modes other than SYStem (i.e. so that IRQ mode can stack the banked LR_usr and SP_usr registers above) which is CONSTRAINED UNPREDICTABLE in SYStem mode since the LR_usr and SP_usr registers are live at the time and not banked. Equivalent and working code would be

	srsdb sp!, #MODE_SYS
	cps #MODE_SYS
	stmdb sp!, {r0-r3, r12, lr}

.. which has the same effect, no side effects and less instructions.

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[nashif]

@ithinuel FYI

[PiotrZierhoffer]

For the record, we have observed this CONSTRAINED UNPREDICTABLE behavior in Renode while running certain SMP tests on Cortex-R platforms.

[ithinuel]

Hi, Thank you all for your patience.

There indeed seem to be something a little bit off there. We are looking into this and possibly another issue in the neighbooring code where more word are pushed to the stack at the IRQ entry than poped at the exit.

I will keep you posted on our progress.