Accessing PCIe through CM7 in IMX8MP

[mbahmani90]

Hi,

Hope you are all well.

I want to access PCIe in CM7 by memory mapping. I am testing with imx8mp_evk in which a WiFi module has been connected to the PCIe.

I can initialize the PCIe in Linux environment an the PCIe status details are:

01:00.0 Ethernet controller: Marvell Technology Group Ltd. Device 2b42 (rev 11)
        Flags: bus master, fast devsel, latency 0, IRQ 240
        Memory at 18100000 (64-bit, prefetchable) [size=1M]
        Memory at 18200000 (64-bit, prefetchable) [size=1M]
        Capabilities: [40] Power Management version 3
        Capabilities: [50] MSI: Enable+ Count=1/32 Maskable+ 64bit+
        Capabilities: [70] Express Endpoint, MSI 00
        Capabilities: [b0] MSI-X: Enable- Count=32 Masked-
        Capabilities: [100] Advanced Error Reporting
        Capabilities: [148] Device Serial Number 00-00-00-00-00-00-00-00
        Capabilities: [158] Power Budgeting <?>
        Capabilities: [168] Latency Tolerance Reporting
        Capabilities: [170] L1 PM Substates
        Kernel driver in use: wlan_pcie

As you see the memory addresses are 18100000 and 18200000 and I can read and write these memory addresses by memory mapping of /dev/mem in Linux.

Then, when I write these addresses in CM7 and read from Linux, the memory values are different from each other!

CM7 Code:

int main(void)
{

	volatile uint32_t* pci_wifi_address1     = (volatile uint32_t*) 0x18100000;
	volatile uint32_t* pci_wifi_address2     = (volatile uint32_t*) 0x18200000;

	while (1) {

		printf("%#x   %#x\r\n" , *pci_wifi_address1 , *pci_wifi_address2);
		*pci_wifi_address1 = 0xdeadbeef;
		k_msleep(SLEEP_TIME_MS);

	}
	
	return 0;
}

Do you have any idea why it is happening?

Thanks.