S32Z270DC2 defined SRAM region too small for almost all workloads

[benmordaunt]

The S32Z270DC2 board DeviceTree includes its chosen SRAM definition node from SoC dts dts/arm/nxp/nxp_s32z27x_r52.dtsi, which presents as:

sram0: memory@31780000 {
        compatible = "mmio-sram";
        reg = <0x31780000 DT_SIZE_M(1)>;
};

... offering 1MiB of application storage for an image programmed directly into RAM.
At least on the S32Z270DC2 evaluation board, it is known that a significantly larger region exists at 0x32100000 with size DT_SIZE_M(7), though without direct access to a datasheet myself, it is difficult to elaborate on this.

Can someone with more insight look into updating this board's SRAM definitions?
As it is only currently possible to run applications directly from SRAM using Lauterbach NXP programming tools on this board, a greater SRAM size is greatly desired.

Thanks.

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[benmordaunt]

On further investigation, it seems that these regions (as specified in the current Zephyr tree), are actually designated as "fast data" regions and not "code" regions, for which there are actually 2 7MiB regions for each RTU.

[manuargue]

Hi @benmordaunt, thanks for logging this issue. I've removed the bug label and tag this as a feature request to support CRAM besides DRAM currently supported. There's no restriction on how these RAM banks can be used, but a recommended use. I agree it would be better to separate data and code to use the optimized RAM banks, hence increasing the total available memory.
Our team @ NXP will look into this and feedback you.