stm42f412 "Failed to enable SDMMC domain clock"

[fariouche]

Describe the bug

Hello,

Using zephyr 4.2, I have an error when calling disk_access_init (more precisely the ioctl version) and I get the error "Failed to enable SDMMC domain clock".
Disk name is "sdio1".
Of course, the dts node is enabled by default, and I have the config DISK_ACCESS and SDMMC_STM32

A workaround is to remove the second clock in the sdmmc dts node like in my overlay:

&sdmmc1 {
	clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
};

I don't know the implications of that or what I'm missing to avoir the above error

Thanks

Regression

• This is a regression.

Steps to reproduce

Just call disk_access_ioctl("sdio1" DISK_IOCTL_CTRL_INIT, NULL);
Using an stm32f412_discovery board

Relevant log output

E: Failed to enable SDMMC domain clock
E: failed to init clocks

Impact

Annoyance – Major; cannot use functionality.

Environment

No response

Additional Context

No response

[erwango]

A workaround is to remove the second clock in the sdmmc dts node like in my overlay:

May I ask which clock it was and if it was actually enabled in the dts ?
Also I don't see any stm32f412_discovery, but stm32f412g_disco in which sdmmc is not enabled. So I assume this is an out of tree board ?

[fariouche]

I'm talking about stm32f412g_disco, sorry.
This is the relevant sdmmc node :

sdmmc1: sdmmc@40012c00 {
        clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
                     <&rcc STM32_SRC_CK48 SDIO_SEL(0)>;
};

from dts/arm/st/f4/stm32f412.dtsi
there is an other one in an include dtsi file, where clocks are

clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
              <&rcc STM32_SRC_PLL_Q NO_SEL>;

Not sure which one is overriding which.

ck48 is enabled in my overlay like so:

&clk48 {
    status = "okay";
};

In the final dts it is the following (and the comment in the dts says its from stm32f412.dts):

clocks = < &rcc 0x44 0x800 >,
              < &rcc 0xb 0x5c0094 >;

of course I also enable the sdmmc1 node

[erwango]

Ok, the issue seems legit indeed, we'll have a look.

[fariouche]

thanks! let me know if you need me to do some tests/investigations to help

[FRASTM]

@fariouche
I found STM32_CK48_ENABLED is not present in this series ; can you please test with the following patch :

diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h
index 6d342fd2149..e05dbb9cff6 100644
--- a/include/zephyr/drivers/clock_control/stm32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h
@@ -220,6 +220,10 @@
 #define STM32_PLLI2S_R_DIVISOR		DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk48), st_stm32_clock_mux, okay)
+#define STM32_CK48_ENABLED	1
+#endif
+
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
 #define STM32_PLLSAI1_ENABLED	1

(I do not have the same stm32 board but the testcase gives the expected freq. with that change )

[erwango]

@fariouche Can you verify #96353 has a positive impact on the issue you're seeing ?

[fariouche]

Hello, sorry for the late reply.
I just tested, and unfortunately the issue remains the same.