Cortex-R Cache line size might be wrong

[natto1784]

Describe the bug

Cortex-R5F Technical Reference Manual by Arm says DMINLINE is the Log2 of the minimum number of words in a cache line. However we see that it calculates the size based on number of halfwords instead:

zephyr/arch/arm/core/cortex_a_r/cache.c

Line 43 in fb7a74e

dcache_line_size = 2 << dminline;

I think it is supposed to be

dcache_line_size = 4 << dminline; 

or am I missing something?

Regression

• This is a regression.

Steps to reproduce

No response

Relevant log output

Impact

Functional Limitation – Some features not working as expected, but system usable.

Environment

No response

Additional Context

zephyr/arch/arm/core/cortex_a_r/cache.c

Line 43 in fb7a74e

dcache_line_size = 2 << dminline;