diff --git a/CODEOWNERS b/CODEOWNERS
index 20a40c8ccb2f6..399356ac1b5ca 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -100,6 +100,7 @@
 /drivers/*/*stm32*                        @erwango
 /drivers/*/*native_posix*                 @aescolar
 /drivers/adc/                             @anangl
+/drivers/adc/adc_stm32.c                  @cybertale
 /drivers/bluetooth/                       @joerchan @jhedberg @Vudentz
 /drivers/can/                             @alexanderwachter
 /drivers/can/*mcp2515*                    @karstenkoenig
@@ -154,6 +155,7 @@
 /dts/riscv32/rv32m1*                      @MaureenHelm
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
+/dts/bindings/iio/adc/st,stm32-adc.yaml   @cybertale
 /dts/bindings/serial/ns16550.yaml         @gnuless
 /dts/bindings/*/nordic*                   @anangl
 /dts/bindings/*/nxp*                      @MaureenHelm
diff --git a/boards/arm/nucleo_f091rc/doc/index.rst b/boards/arm/nucleo_f091rc/doc/index.rst
index 31adff67d4b51..740a14180107f 100644
--- a/boards/arm/nucleo_f091rc/doc/index.rst
+++ b/boards/arm/nucleo_f091rc/doc/index.rst
@@ -96,6 +96,8 @@ The Zephyr nucleo_f091rc board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | SPI controller                      |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported in this Zephyr port.
 
diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts b/boards/arm/nucleo_f091rc/nucleo_f091rc.dts
index 8a4736cbbff48..e7a430b6f9a1b 100644
--- a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts
+++ b/boards/arm/nucleo_f091rc/nucleo_f091rc.dts
@@ -93,3 +93,7 @@ arduino_spi: &spi1 {
 		};
 	};
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml b/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml
index aa8f0f3d9f915..fc990090a4183 100644
--- a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml
+++ b/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml
@@ -15,6 +15,7 @@ supported:
   - nvs
   - spi
   - watchdog
+  - adc
 testing:
   ignore_tags:
     - net
diff --git a/boards/arm/nucleo_f091rc/pinmux.c b/boards/arm/nucleo_f091rc/pinmux.c
index f88adbf8d421f..baff16656c418 100644
--- a/boards/arm/nucleo_f091rc/pinmux.c
+++ b/boards/arm/nucleo_f091rc/pinmux.c
@@ -40,6 +40,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PB14, STM32F0_PINMUX_FUNC_PB14_SPI2_MISO},
 	{STM32_PIN_PB15, STM32F0_PINMUX_FUNC_PB15_SPI2_MOSI},
 #endif /* CONFIG_SPI_2 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32F0_PINMUX_FUNC_PA0_ADC_IN0},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_f103rb/doc/index.rst b/boards/arm/nucleo_f103rb/doc/index.rst
index e7c3065883a6a..2a1605e1cd20a 100644
--- a/boards/arm/nucleo_f103rb/doc/index.rst
+++ b/boards/arm/nucleo_f103rb/doc/index.rst
@@ -93,6 +93,8 @@ The Zephyr nucleo_f103rb board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | WATCHDOG  | on-chip    | independent watchdog                |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported in this Zephyr port.
 
diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts b/boards/arm/nucleo_f103rb/nucleo_f103rb.dts
index 8781e8c8dde1f..72be307acf757 100644
--- a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts
+++ b/boards/arm/nucleo_f103rb/nucleo_f103rb.dts
@@ -78,3 +78,7 @@ arduino_spi: &spi1 {
 &iwdg {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml b/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml
index 40139decd7944..3e8557b091fd2 100644
--- a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml
+++ b/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml
@@ -13,3 +13,4 @@ supported:
   - spi
   - pwm
   - watchdog
+  - adc
diff --git a/boards/arm/nucleo_f103rb/pinmux.c b/boards/arm/nucleo_f103rb/pinmux.c
index c0929f7a6ca58..3a0e4afca604e 100644
--- a/boards/arm/nucleo_f103rb/pinmux.c
+++ b/boards/arm/nucleo_f103rb/pinmux.c
@@ -41,6 +41,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PB14, STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO},
 	{STM32_PIN_PB15, STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI},
 #endif /* CONFIG_SPI_2 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32F1_PINMUX_FUNC_PA0_ADC123_IN0},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_f207zg/doc/index.rst b/boards/arm/nucleo_f207zg/doc/index.rst
index 85c22b77e417c..76f70d9d5794e 100644
--- a/boards/arm/nucleo_f207zg/doc/index.rst
+++ b/boards/arm/nucleo_f207zg/doc/index.rst
@@ -92,6 +92,8 @@ The Zephyr nucleo_207zg board configuration supports the following hardware feat
 +-----------+------------+-------------------------------------+
 | WATCHDOG  | on-chip    | independent watchdog                |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts b/boards/arm/nucleo_f207zg/nucleo_f207zg.dts
index 8bf88bcd66ccf..0d6868afd940e 100644
--- a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts
+++ b/boards/arm/nucleo_f207zg/nucleo_f207zg.dts
@@ -72,3 +72,7 @@ arduino_serial: &usart6 {};
 &iwdg {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml b/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml
index abd38f69510ed..e04d478ac63a7 100644
--- a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml
+++ b/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml
@@ -12,3 +12,4 @@ supported:
   - gpio
   - usb_device
   - watchdog
+  - adc
diff --git a/boards/arm/nucleo_f207zg/pinmux.c b/boards/arm/nucleo_f207zg/pinmux.c
index 5edcc41aef0b1..f1d32dd689fe1 100644
--- a/boards/arm/nucleo_f207zg/pinmux.c
+++ b/boards/arm/nucleo_f207zg/pinmux.c
@@ -39,6 +39,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PA11, STM32F2_PINMUX_FUNC_PA11_OTG_FS_DM},
 	{STM32_PIN_PA12, STM32F2_PINMUX_FUNC_PA12_OTG_FS_DP},
 #endif	/* CONFIG_USB_DC_STM32 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32F2_PINMUX_FUNC_PA0_ADC123_IN0},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_f302r8/doc/index.rst b/boards/arm/nucleo_f302r8/doc/index.rst
index a6006f8b3d1ef..2e2366e50aefb 100644
--- a/boards/arm/nucleo_f302r8/doc/index.rst
+++ b/boards/arm/nucleo_f302r8/doc/index.rst
@@ -97,6 +97,8 @@ features:
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.dts b/boards/arm/nucleo_f302r8/nucleo_f302r8.dts
index 8422d49e74077..6e13287e873f2 100644
--- a/boards/arm/nucleo_f302r8/nucleo_f302r8.dts
+++ b/boards/arm/nucleo_f302r8/nucleo_f302r8.dts
@@ -82,3 +82,7 @@ arduino_spi: &spi2 {};
 &rtc {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml b/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml
index 222a7a0332076..2cc4b445630f4 100644
--- a/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml
+++ b/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml
@@ -16,3 +16,4 @@ supported:
   - pwm
   - rtc
   - counter
+  - adc
diff --git a/boards/arm/nucleo_f302r8/pinmux.c b/boards/arm/nucleo_f302r8/pinmux.c
index 38e443b4153fa..7e0c853fa0689 100644
--- a/boards/arm/nucleo_f302r8/pinmux.c
+++ b/boards/arm/nucleo_f302r8/pinmux.c
@@ -39,6 +39,9 @@ static const struct pin_config pinconf[] = {
 #ifdef CONFIG_PWM_STM32_2
 	{STM32_PIN_PA0, STM32F3_PINMUX_FUNC_PA0_PWM2_CH1},
 #endif /* CONFIG_PWM_STM32_2 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32F3_PINMUX_FUNC_PA0_ADC1_IN1},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_f401re/doc/index.rst b/boards/arm/nucleo_f401re/doc/index.rst
index 536b3d8ab9418..e3aad45d7d325 100644
--- a/boards/arm/nucleo_f401re/doc/index.rst
+++ b/boards/arm/nucleo_f401re/doc/index.rst
@@ -83,6 +83,8 @@ The Zephyr nucleo_401re board configuration supports the following hardware feat
 +-----------+------------+-------------------------------------+
 | I2C       | on-chip    | i2c                                 |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on Zephyr porting.
 
diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.dts b/boards/arm/nucleo_f401re/nucleo_f401re.dts
index 0840af3954d5d..7a8ee0c32bb95 100644
--- a/boards/arm/nucleo_f401re/nucleo_f401re.dts
+++ b/boards/arm/nucleo_f401re/nucleo_f401re.dts
@@ -117,3 +117,7 @@ arduino_spi: &spi1 {
 &rtc {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.yaml b/boards/arm/nucleo_f401re/nucleo_f401re.yaml
index 3dc75b6e5f440..0bb37c1f1c8b6 100644
--- a/boards/arm/nucleo_f401re/nucleo_f401re.yaml
+++ b/boards/arm/nucleo_f401re/nucleo_f401re.yaml
@@ -14,5 +14,6 @@ supported:
   - gpio
   - i2c
   - spi
+  - adc
 ram: 96
 flash: 512
diff --git a/boards/arm/nucleo_f401re/pinmux.c b/boards/arm/nucleo_f401re/pinmux.c
index cab1a0ee3232d..789857c434dc6 100644
--- a/boards/arm/nucleo_f401re/pinmux.c
+++ b/boards/arm/nucleo_f401re/pinmux.c
@@ -41,6 +41,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO},
 	{STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI},
 #endif	/* CONFIG_SPI_1 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32F4_PINMUX_FUNC_PA0_ADC123_IN0},
+#endif	/* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_f746zg/doc/index.rst b/boards/arm/nucleo_f746zg/doc/index.rst
index 560b17fdbdb33..aff3d533f521e 100644
--- a/boards/arm/nucleo_f746zg/doc/index.rst
+++ b/boards/arm/nucleo_f746zg/doc/index.rst
@@ -118,6 +118,8 @@ features:
 +-----------+------------+-------------------------------------+
 | WATCHDOG  | on-chip    | independent watchdog                |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts b/boards/arm/nucleo_f746zg/nucleo_f746zg.dts
index 57bf9686724ab..12ff00e7fd623 100644
--- a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts
+++ b/boards/arm/nucleo_f746zg/nucleo_f746zg.dts
@@ -108,3 +108,7 @@ arduino_spi: &spi1 {};
 	phase_seg2 = <5>;
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml b/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml
index bd3640739bb6f..061cb81c7b095 100644
--- a/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml
+++ b/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml
@@ -21,3 +21,4 @@ supported:
   - rtc
   - counter
   - can
+  - adc
diff --git a/boards/arm/nucleo_f746zg/pinmux.c b/boards/arm/nucleo_f746zg/pinmux.c
index 36dbc65f59814..16d4b30a2c832 100644
--- a/boards/arm/nucleo_f746zg/pinmux.c
+++ b/boards/arm/nucleo_f746zg/pinmux.c
@@ -66,6 +66,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PD0, STM32F7_PINMUX_FUNC_PD0_CAN_RX},
 	{STM32_PIN_PD1, STM32F7_PINMUX_FUNC_PD1_CAN_TX},
 #endif /* CONFIG_CAN_1 */
+#ifdef CONFIG_ADC_1
+	{ STM32_PIN_PA0, STM32F7_PINMUX_FUNC_PA0_ADC123_IN0 },
+#endif	/* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_l073rz/doc/index.rst b/boards/arm/nucleo_l073rz/doc/index.rst
index be8c71b51b075..b23dfab2f297c 100644
--- a/boards/arm/nucleo_l073rz/doc/index.rst
+++ b/boards/arm/nucleo_l073rz/doc/index.rst
@@ -94,6 +94,8 @@ The Zephyr nucleo_l073rz board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | WATCHDOG  | on-chip    | independent watchdog                |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported in this Zephyr port.
 
diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.dts b/boards/arm/nucleo_l073rz/nucleo_l073rz.dts
index 6b23193a70053..154e319ae40b8 100644
--- a/boards/arm/nucleo_l073rz/nucleo_l073rz.dts
+++ b/boards/arm/nucleo_l073rz/nucleo_l073rz.dts
@@ -65,3 +65,7 @@ arduino_spi: &spi1 {
 &iwdg {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml b/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml
index 7f9459c354e1d..df2d0266093d7 100644
--- a/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml
+++ b/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml
@@ -14,3 +14,4 @@ supported:
   - i2c
   - spi
   - watchdog
+  - adc
diff --git a/boards/arm/nucleo_l073rz/pinmux.c b/boards/arm/nucleo_l073rz/pinmux.c
index cc6ab8836b312..a1a386e17bf38 100644
--- a/boards/arm/nucleo_l073rz/pinmux.c
+++ b/boards/arm/nucleo_l073rz/pinmux.c
@@ -31,6 +31,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PA6, STM32L0_PINMUX_FUNC_PA6_SPI1_MISO},
 	{STM32_PIN_PA7, STM32L0_PINMUX_FUNC_PA7_SPI1_MOSI},
 #endif /* CONFIG_SPI_1 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PA0, STM32L0_PINMUX_FUNC_PA0_ADC_IN0},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/boards/arm/nucleo_l476rg/doc/index.rst b/boards/arm/nucleo_l476rg/doc/index.rst
index 9c8cdd276ce54..2058ddc88b64b 100644
--- a/boards/arm/nucleo_l476rg/doc/index.rst
+++ b/boards/arm/nucleo_l476rg/doc/index.rst
@@ -123,6 +123,8 @@ The Zephyr nucleo_l476rg board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC Controller                      |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts b/boards/arm/nucleo_l476rg/nucleo_l476rg.dts
index affa9d6fd35f1..71ab80c184ffe 100644
--- a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts
+++ b/boards/arm/nucleo_l476rg/nucleo_l476rg.dts
@@ -79,3 +79,7 @@ arduino_i2c: &i2c1 {
 &rtc {
 	status = "ok";
 };
+
+&adc1 {
+	status = "ok";
+};
diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml b/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml
index bf3ad5ca011b5..5c84bc9a19b7b 100644
--- a/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml
+++ b/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml
@@ -14,5 +14,6 @@ supported:
   - i2c
   - rtc
   - counter
+  - adc
 ram: 96
 flash: 1024
diff --git a/boards/arm/nucleo_l476rg/pinmux.c b/boards/arm/nucleo_l476rg/pinmux.c
index 63503aabd0236..9a0b4869d39a0 100644
--- a/boards/arm/nucleo_l476rg/pinmux.c
+++ b/boards/arm/nucleo_l476rg/pinmux.c
@@ -60,6 +60,9 @@ static const struct pin_config pinconf[] = {
 	{STM32_PIN_PC11, STM32L4X_PINMUX_FUNC_PC11_SPI3_MISO},
 	{STM32_PIN_PC12, STM32L4X_PINMUX_FUNC_PC12_SPI3_MOSI},
 #endif /* CONFIG_SPI_3 */
+#ifdef CONFIG_ADC_1
+	{STM32_PIN_PC0, STM32L4X_PINMUX_FUNC_PC0_ADC123_IN1},
+#endif /* CONFIG_ADC_1 */
 };
 
 static int pinmux_stm32_init(struct device *port)
diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt
index 2654b3a089636..8193a14d36a53 100644
--- a/drivers/adc/CMakeLists.txt
+++ b/drivers/adc/CMakeLists.txt
@@ -9,4 +9,5 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC	adc_nrfx_saadc.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_INTEL_QUARK_SE_C1000_SS	adc_intel_quark_se_c1000_ss.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_INTEL_QUARK_D2000	adc_intel_quark_d2000.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_SAM0		adc_sam0.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_STM32		adc_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		adc_handlers.c)
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index b981b8499dacd..65230269110df 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -57,4 +57,6 @@ source "drivers/adc/Kconfig.intel_quark"
 
 source "drivers/adc/Kconfig.sam0"
 
+source "drivers/adc/Kconfig.stm32"
+
 endif # ADC
diff --git a/drivers/adc/Kconfig.stm32 b/drivers/adc/Kconfig.stm32
new file mode 100644
index 0000000000000..49fd2ba40f41a
--- /dev/null
+++ b/drivers/adc/Kconfig.stm32
@@ -0,0 +1,25 @@
+# Kconfig - ADC configuration options
+
+#
+# Copyright (c) 2019 Intel Corporation
+# Copyright (c) 2019 Endre Karlson
+# Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig ADC_STM32
+	bool "STM32 ADC driver"
+	depends on SOC_FAMILY_STM32
+	help
+	  Enable the driver implementation for the stm32xx ADC
+
+if ADC_STM32
+
+config ADC_1
+	bool "ADC1"
+	default y
+	help
+	  Enable ADC1
+
+endif # ADC_STM32
diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
new file mode 100644
index 0000000000000..e96ccaf728fff
--- /dev/null
+++ b/drivers/adc/adc_stm32.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2018 Kokoon Technology Limited
+ * Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
+ * Copyright (c) 2019 Endre Karlson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+
+#include <adc.h>
+#include <device.h>
+#include <kernel.h>
+#include <init.h>
+#include <soc.h>
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
+#include <logging/log.h>
+LOG_MODULE_REGISTER(adc_stm32);
+
+#include <clock_control/stm32_clock_control.h>
+
+#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
+	!defined(CONFIG_SOC_SERIES_STM32L0X)
+#define RANK(n)		LL_ADC_REG_RANK_##n
+static const u32_t table_rank[] = {
+	RANK(1),
+	RANK(2),
+	RANK(3),
+	RANK(4),
+	RANK(5),
+	RANK(6),
+	RANK(7),
+	RANK(8),
+	RANK(9),
+	RANK(10),
+	RANK(11),
+	RANK(12),
+	RANK(13),
+	RANK(14),
+	RANK(15),
+	RANK(16),
+};
+
+#define SEQ_LEN(n)	LL_ADC_REG_SEQ_SCAN_ENABLE_##n##RANKS
+static const u32_t table_seq_len[] = {
+	LL_ADC_REG_SEQ_SCAN_DISABLE,
+	SEQ_LEN(2),
+	SEQ_LEN(3),
+	SEQ_LEN(4),
+	SEQ_LEN(5),
+	SEQ_LEN(6),
+	SEQ_LEN(7),
+	SEQ_LEN(8),
+	SEQ_LEN(9),
+	SEQ_LEN(10),
+	SEQ_LEN(11),
+	SEQ_LEN(12),
+	SEQ_LEN(13),
+	SEQ_LEN(14),
+	SEQ_LEN(15),
+	SEQ_LEN(16),
+};
+#endif
+
+#define RES(n)		LL_ADC_RESOLUTION_##n##B
+static const u32_t table_resolution[] = {
+#if !defined(CONFIG_SOC_SERIES_STM32F1X)
+	RES(6),
+	RES(8),
+	RES(10),
+#endif
+	RES(12),
+};
+
+#define SMP_TIME(x, y)		LL_ADC_SAMPLINGTIME_##x##CYCLE##y
+
+/*
+ * Conversion time in ADC cycles. Many values should have been 0.5 less,
+ * but the adc api system currently does not support describing 'half cycles'.
+ * So all half cycles are counted as one.
+ */
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F1X)
+static const u16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(1,   _5),
+	SMP_TIME(7,   S_5),
+	SMP_TIME(13,  S_5),
+	SMP_TIME(28,  S_5),
+	SMP_TIME(41,  S_5),
+	SMP_TIME(55,  S_5),
+	SMP_TIME(71,  S_5),
+	SMP_TIME(239, S_5),
+};
+#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
+	defined(CONFIG_SOC_SERIES_STM32F4X) || \
+	defined(CONFIG_SOC_SERIES_STM32F7X)
+static const u16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(3,   S),
+	SMP_TIME(15,  S),
+	SMP_TIME(28,  S),
+	SMP_TIME(56,  S),
+	SMP_TIME(84,  S),
+	SMP_TIME(112, S),
+	SMP_TIME(144, S),
+	SMP_TIME(480, S),
+};
+#elif defined(CONFIG_SOC_SERIES_STM32F3X)
+#ifdef ADC5_V1_1
+static const u16_t acq_time_tbl[8] = {2, 3, 5, 8, 20, 62, 182, 602};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(1,   _5),
+	SMP_TIME(2,   S_5),
+	SMP_TIME(4,   S_5),
+	SMP_TIME(7,   S_5),
+	SMP_TIME(19,  S_5),
+	SMP_TIME(61,  S_5),
+	SMP_TIME(181, S_5),
+	SMP_TIME(601, S_5),
+};
+#else
+static const u16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(1,   _5),
+	SMP_TIME(7,   S_5),
+	SMP_TIME(13,  S_5),
+	SMP_TIME(28,  S_5),
+	SMP_TIME(41,  S_5),
+	SMP_TIME(55,  S_5),
+	SMP_TIME(71,  S_5),
+	SMP_TIME(239, S_5),
+};
+#endif /* ADC5_V1_1 */
+#elif defined(CONFIG_SOC_SERIES_STM32L0X)
+static const u16_t acq_time_tbl[8] = {2, 4, 8, 13, 20, 40, 80, 161};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(1,   _5),
+	SMP_TIME(3,   S_5),
+	SMP_TIME(7,   S_5),
+	SMP_TIME(12,  S_5),
+	SMP_TIME(19,  S_5),
+	SMP_TIME(39,  S_5),
+	SMP_TIME(79,  S_5),
+	SMP_TIME(160, S_5),
+};
+#elif defined(CONFIG_SOC_SERIES_STM32L4X)
+static const u16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
+static const u32_t table_samp_time[] = {
+	SMP_TIME(2,   S_5),
+	SMP_TIME(6,   S_5),
+	SMP_TIME(12,  S_5),
+	SMP_TIME(24,  S_5),
+	SMP_TIME(47,  S_5),
+	SMP_TIME(92,  S_5),
+	SMP_TIME(247, S_5),
+	SMP_TIME(640, S_5),
+};
+#endif
+
+/* 16 external channels. */
+#define STM32_CHANNEL_COUNT		16
+
+struct adc_stm32_data {
+	struct adc_context ctx;
+	struct device *dev;
+	u16_t *buffer;
+	u16_t *repeat_buffer;
+
+	u8_t resolution;
+	u8_t channel_count;
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
+	s8_t acq_time_index;
+#endif
+};
+
+struct adc_stm32_cfg {
+	ADC_TypeDef *base;
+
+	void (*irq_cfg_func)(void);
+
+	struct stm32_pclken pclken;
+	struct device *p_dev;
+};
+
+static int check_buffer_size(const struct adc_sequence *sequence,
+			     u8_t active_channels)
+{
+	size_t needed_buffer_size;
+
+	needed_buffer_size = active_channels * sizeof(u16_t);
+
+	if (sequence->options) {
+		needed_buffer_size *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < needed_buffer_size) {
+		LOG_ERR("Provided buffer is too small (%u/%u)",
+				sequence->buffer_size, needed_buffer_size);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void adc_stm32_start_conversion(struct device *dev)
+{
+	const struct adc_stm32_cfg *config = dev->config->config_info;
+	ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
+
+	LOG_DBG("Starting conversion");
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	LL_ADC_REG_StartConversion(adc);
+#else
+	LL_ADC_REG_StartConversionSWStart(adc);
+#endif
+}
+
+static int start_read(struct device *dev, const struct adc_sequence *sequence)
+{
+	const struct adc_stm32_cfg *config = dev->config->config_info;
+	struct adc_stm32_data *data = dev->driver_data;
+	ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
+	u8_t resolution;
+	int err;
+
+	switch (sequence->resolution) {
+#if !defined(CONFIG_SOC_SERIES_STM32F1X)
+	case 6:
+		resolution = table_resolution[0];
+		break;
+	case 8:
+		resolution = table_resolution[1];
+		break;
+	case 10:
+		resolution = table_resolution[2];
+		break;
+#endif
+	case 12:
+		resolution = table_resolution[3];
+		break;
+	default:
+		LOG_ERR("Invalid resolution");
+		return -EINVAL;
+	}
+
+	u32_t channels = sequence->channels;
+
+	data->buffer = sequence->buffer;
+	u8_t index;
+
+	index = find_lsb_set(channels) - 1;
+	u32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(index);
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X)
+	LL_ADC_REG_SetSequencerChannels(adc, channel);
+#else
+	LL_ADC_REG_SetSequencerRanks(adc, table_rank[0], channel);
+	LL_ADC_REG_SetSequencerLength(adc, table_seq_len[0]);
+#endif
+	data->channel_count = 1;
+
+	err = check_buffer_size(sequence, data->channel_count);
+	if (err) {
+		return err;
+	}
+
+#if !defined(CONFIG_SOC_SERIES_STM32F1X)
+	LL_ADC_SetResolution(adc, resolution);
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	LL_ADC_EnableIT_EOC(adc);
+#elif defined(CONFIG_SOC_SERIES_STM32F1X)
+	LL_ADC_EnableIT_EOS(adc);
+#else
+	LL_ADC_EnableIT_EOCS(adc);
+#endif
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	return adc_context_wait_for_completion(&data->ctx);
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_stm32_data *data =
+		CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
+
+	data->repeat_buffer = data->buffer;
+
+	adc_stm32_start_conversion(data->dev);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx,
+					      bool repeat_sampling)
+{
+	struct adc_stm32_data *data =
+		CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static void adc_stm32_isr(void *arg)
+{
+	struct device *dev = (struct device *)arg;
+	struct adc_stm32_data *data = (struct adc_stm32_data *)dev->driver_data;
+	struct adc_stm32_cfg *config =
+		(struct adc_stm32_cfg *)dev->config->config_info;
+	ADC_TypeDef *adc = config->base;
+
+	*data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
+
+	adc_context_on_sampling_done(&data->ctx, dev);
+
+	LOG_DBG("ISR triggered.");
+}
+
+static int adc_stm32_read(struct device *dev,
+			  const struct adc_sequence *sequence)
+{
+	struct adc_stm32_data *data = dev->driver_data;
+	int error;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	error = start_read(dev, sequence);
+	adc_context_release(&data->ctx, error);
+
+	return error;
+}
+
+#ifdef CONFIG_ADC_ASYNC
+static int adc_stm32_read_async(struct device *dev,
+				 const struct adc_sequence *sequence,
+				 struct k_poll_signal *async)
+{
+	struct adc_stm32_data *data = dev->driver_data;
+	int error;
+
+	adc_context_lock(&data->ctx, true, async);
+	error = start_read(dev, sequence);
+	adc_context_release(&data->ctx, error);
+
+	return error;
+}
+#endif
+
+static int adc_stm32_check_acq_time(u16_t acq_time)
+{
+	for (int i = 0; i < 8; i++) {
+		if (acq_time == ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS,
+					     acq_time_tbl[i])) {
+			return i;
+		}
+	}
+
+	if (acq_time == ADC_ACQ_TIME_DEFAULT) {
+		return 0;
+	}
+
+	LOG_ERR("Conversion time not supportted.");
+	return -EINVAL;
+}
+
+static void adc_stm32_setup_speed(struct device *dev, u8_t id,
+				  u8_t acq_time_index)
+{
+	struct adc_stm32_cfg *config =
+		(struct adc_stm32_cfg *)dev->config->config_info;
+	ADC_TypeDef *adc = config->base;
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
+	LL_ADC_SetSamplingTimeCommonChannels(adc,
+		table_samp_time[acq_time_index]);
+#else
+	LL_ADC_SetChannelSamplingTime(adc,
+		__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
+		table_samp_time[acq_time_index]);
+#endif
+}
+
+static int adc_stm32_channel_setup(struct device *dev,
+			    const struct adc_channel_cfg *channel_cfg)
+{
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
+	struct adc_stm32_data *data = dev->driver_data;
+#endif
+	int acq_time_index;
+
+	if (channel_cfg->channel_id >= STM32_CHANNEL_COUNT) {
+		LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
+		return -EINVAL;
+	}
+
+	acq_time_index = adc_stm32_check_acq_time(
+				channel_cfg->acquisition_time);
+	if (acq_time_index < 0) {
+		return acq_time_index;
+	}
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
+	if (data->acq_time_index == -1) {
+		data->acq_time_index = acq_time_index;
+	} else {
+		/* All channels of F0/L0 must have identical acquisition time.*/
+		if (acq_time_index != data->acq_time_index) {
+			return -EINVAL;
+		}
+	}
+#endif
+
+	if (channel_cfg->differential) {
+		LOG_ERR("Differential channels are not supported");
+		return -EINVAL;
+	}
+
+	if (channel_cfg->gain != ADC_GAIN_1) {
+		LOG_ERR("Invalid channel gain");
+		return -EINVAL;
+	}
+
+	if (channel_cfg->reference != ADC_REF_INTERNAL) {
+		LOG_ERR("Invalid channel reference");
+		return -EINVAL;
+	}
+
+	adc_stm32_setup_speed(dev, channel_cfg->channel_id,
+				  acq_time_index);
+
+	LOG_DBG("Channel setup succeeded!");
+
+	return 0;
+}
+
+#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F4X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F7X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F1X)
+static void adc_stm32_calib(struct device *dev)
+{
+	struct adc_stm32_cfg *config =
+		(struct adc_stm32_cfg *)dev->config->config_info;
+	ADC_TypeDef *adc = config->base;
+
+#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
+#elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X)
+	LL_ADC_StartCalibration(adc);
+#endif
+	while (LL_ADC_IsCalibrationOnGoing(adc))
+		;
+}
+#endif
+
+static int adc_stm32_init(struct device *dev)
+{
+	struct adc_stm32_data *data = dev->driver_data;
+	const struct adc_stm32_cfg *config = dev->config->config_info;
+	struct device *clk =
+		device_get_binding(STM32_CLOCK_CONTROL_NAME);
+	ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
+
+	LOG_DBG("Initializing....");
+
+	data->dev = dev;
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
+	/*
+	 * All conversion time for all channels on one ADC instance for F0 and
+	 * L0 series chips has to be the same. This additional variable is for
+	 * checking if the conversion time selection of all channels on one ADC
+	 * instance is the same.
+	 */
+	data->acq_time_index = -1;
+#endif
+
+	if (clock_control_on(clk,
+		(clock_control_subsys_t *) &config->pclken) != 0) {
+		return -EIO;
+	}
+
+#if defined(CONFIG_SOC_SERIES_STM32L4X)
+	/*
+	 * L4 series STM32 needs to be awaken from deep sleep mode, and restore
+	 * its calibration parameters if there are some previously stored
+	 * calibration parameters.
+	 */
+	LL_ADC_DisableDeepPowerDown(adc);
+#endif
+	/*
+	 * F3 and L4 ADC modules need some time to be stabilized before
+	 * performing any enable or calibration actions.
+	 */
+#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	LL_ADC_EnableInternalRegulator(adc);
+	k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X)
+	LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
+#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(),
+			LL_ADC_CLOCK_SYNC_PCLK_DIV4);
+#endif
+
+#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F4X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F7X) && \
+	!defined(CONFIG_SOC_SERIES_STM32F1X)
+	/*
+	 * Calibration of F1 series has to be started after ADC Module is
+	 * enabled.
+	 */
+	adc_stm32_calib(dev);
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X)
+	if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
+		LL_ADC_ClearFlag_ADRDY(adc);
+	}
+
+	/*
+	 * These two series STM32 has one internal voltage reference source
+	 * to be enabled.
+	 */
+	LL_ADC_SetCommonPathInternalCh(ADC, LL_ADC_PATH_INTERNAL_VREFINT);
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
+	defined(CONFIG_SOC_SERIES_STM32F3X) || \
+	defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32L4X)
+	/*
+	 * ADC modules on these series have to wait for some cycles to be
+	 * enabled.
+	 */
+	u32_t adc_rate, wait_cycles;
+
+	if (clock_control_get_rate(clk,
+		(clock_control_subsys_t *) &config->pclken, &adc_rate) < 0) {
+		LOG_ERR("ADC clock rate get error.");
+	}
+
+	wait_cycles = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / adc_rate *
+		      LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES;
+
+	for (int i = wait_cycles; i >= 0; i--)
+		;
+#endif
+
+	LL_ADC_Enable(adc);
+
+#ifdef CONFIG_SOC_SERIES_STM32L4X
+	/*
+	 * Enabling ADC modules in L4 series may fail if they are still not
+	 * stabilized, this will wait for a short time to ensure ADC modules
+	 * are properly enabled.
+	 */
+	u32_t countTimeout = 0;
+
+	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {
+		if (LL_ADC_IsEnabled(adc) == 0UL) {
+			LL_ADC_Enable(adc);
+			countTimeout++;
+			if (countTimeout == 10) {
+				return -ETIMEDOUT;
+			}
+		}
+	}
+#endif
+
+	config->irq_cfg_func();
+
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	/* Calibration of F1 must starts after two cycles after ADON is set. */
+	LL_ADC_StartCalibration(adc);
+	LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
+#endif
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static const struct adc_driver_api api_stm32_driver_api = {
+	.channel_setup = adc_stm32_channel_setup,
+	.read = adc_stm32_read,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = adc_stm32_read_async,
+#endif
+};
+
+#define STM32_ADC_INIT(index)						\
+									\
+static void adc_stm32_cfg_func_##index(void);				\
+									\
+static const struct adc_stm32_cfg adc_stm32_cfg_##index = {		\
+	.base = (ADC_TypeDef *)DT_ADC_##index##_BASE_ADDRESS,		\
+	.irq_cfg_func = adc_stm32_cfg_func_##index,			\
+	.pclken = {							\
+		.enr = DT_ADC_##index##_CLOCK_BITS,			\
+		.bus = DT_ADC_##index##_CLOCK_BUS,			\
+	},								\
+};									\
+static struct adc_stm32_data adc_stm32_data_##index = {			\
+	ADC_CONTEXT_INIT_TIMER(adc_stm32_data_##index, ctx),		\
+	ADC_CONTEXT_INIT_LOCK(adc_stm32_data_##index, ctx),		\
+	ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx),		\
+};									\
+									\
+DEVICE_AND_API_INIT(adc_##index, DT_ADC_##index##_NAME, &adc_stm32_init,\
+		    &adc_stm32_data_##index, &adc_stm32_cfg_##index,	\
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	\
+		    &api_stm32_driver_api);				\
+									\
+static void adc_stm32_cfg_func_##index(void)				\
+{									\
+	IRQ_CONNECT(DT_ADC_##index##_IRQ, DT_ADC_##index##_IRQ_PRI,	\
+		    adc_stm32_isr, DEVICE_GET(adc_##index), 0);		\
+	irq_enable(DT_ADC_##index##_IRQ);				\
+}
+
+#ifdef CONFIG_ADC_1
+STM32_ADC_INIT(1)
+#endif /* CONFIG_ADC_1 */
diff --git a/drivers/pinmux/stm32/pinmux_stm32f0.h b/drivers/pinmux/stm32/pinmux_stm32f0.h
index ba84f301105e8..f055962e85412 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f0.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f0.h
@@ -108,4 +108,37 @@
 #define STM32F0_PINMUX_FUNC_PD1_CAN_TX \
 	(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
 
+#define STM32F0_PINMUX_FUNC_PA0_ADC_IN0 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA1_ADC_IN1 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA2_ADC_IN2 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA3_ADC_IN3 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA4_ADC_IN4 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA5_ADC_IN5 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA6_ADC_IN6 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PA7_ADC_IN7 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PB0_ADC_IN8 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PB1_ADC_IN9 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC0_ADC_IN10 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC1_ADC_IN11 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC2_ADC_IN12 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC3_ADC_IN13 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC4_ADC_IN14 \
+	STM32_MODER_ANALOG_MODE
+#define STM32F0_PINMUX_FUNC_PC5_ADC_IN15 \
+	STM32_MODER_ANALOG_MODE
+
 #endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F0_H_ */
diff --git a/drivers/pinmux/stm32/pinmux_stm32f1.h b/drivers/pinmux/stm32/pinmux_stm32f1.h
index d92c8df1734d0..c4540f6c491eb 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f1.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f1.h
@@ -70,4 +70,26 @@
 
 #define STM32F1_PINMUX_FUNC_PA8_PWM1_CH1	     STM32_PIN_PWM
 
+#define STM32F1_PINMUX_FUNC_PF6_ADC3_IN4             STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PF7_ADC3_IN5             STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PF8_ADC3_IN6             STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PF9_ADC3_IN7             STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PF10_ADC3_IN8            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC0_ADC123_IN10          STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC1_ADC123_IN11          STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC2_ADC123_IN12          STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC3_ADC123_IN13          STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA0_ADC123_IN0           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA1_ADC123_IN1           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA2_ADC123_IN2           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA3_ADC123_IN3           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA4_ADC12_IN4            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA5_ADC12_IN5            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA6_ADC12_IN6            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PA7_ADC12_IN7            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC4_ADC12_IN14           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PC4_ADC12_IN15           STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PB0_ADC12_IN8            STM32_CNF_IN_ANALOG
+#define STM32F1_PINMUX_FUNC_PB1_ADC12_IN9            STM32_CNF_IN_ANALOG
+
 #endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F1_H_ */
diff --git a/drivers/pinmux/stm32/pinmux_stm32f2.h b/drivers/pinmux/stm32/pinmux_stm32f2.h
index af8365d4a0486..c869bdc025593 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f2.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f2.h
@@ -24,25 +24,44 @@
 #define STM32F2_PINMUX_FUNC_PA1_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PA0_ADC123_IN0	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PA1_UART4_RX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
+#define STM32F2_PINMUX_FUNC_PA1_ADC123_IN1	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PA2_USART2_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
 #define STM32F2_PINMUX_FUNC_PA2_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PA2_ADC123_IN2	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PA3_USART2_RX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
 #define STM32F2_PINMUX_FUNC_PA3_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PA3_ADC123_IN3	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PA4_ADC12_IN4	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PA5_ADC12_IN5	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PA6_ADC12_IN6	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PA7_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PA7_ADC12_IN7	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PA9_USART1_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
@@ -57,6 +76,12 @@
 	(STM32_PINMUX_ALT_FUNC_10 | STM32_PUSHPULL_NOPULL)
 
 /* Port B */
+#define STM32F2_PINMUX_FUNC_PB0_ADC12_IN8	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PB1_ADC12_IN9	\
+	STM32_MODER_ANALOG_MODE
+
 #define STM32F2_PINMUX_FUNC_PB6_USART1_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
 
@@ -81,17 +106,32 @@
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 
 /* Port C */
+#define STM32F2_PINMUX_FUNC_PC0_ADC123_IN10	\
+	STM32_MODER_ANALOG_MODE
+
 #define STM32F2_PINMUX_FUNC_PC1_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PC1_ADC123_IN11	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PC2_ADC123_IN12	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F2_PINMUX_FUNC_PC3_ADC123_IN13	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PC4_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PC4_ADC12_IN14	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PC5_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F2_PINMUX_FUNC_PC5_ADC12_IN15	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F2_PINMUX_FUNC_PC6_USART6_TX   \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
@@ -131,6 +171,22 @@
 /* Port E */
 
 /* Port F */
+#define STM32F2_PINMUX_FUNC_PF3_ADC3_IN9	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF4_ADC3_IN14	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF5_ADC3_IN15	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF6_ADC3_IN4	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF7_ADC3_IN5	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF8_ADC3_IN6	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF9_ADC3_IN7	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F2_PINMUX_FUNC_PF10_ADC3_IN8	\
+	STM32_MODER_ANALOG_MODE
 
 /* Port G */
 #define STM32F2_PINMUX_FUNC_PG9_USART6_RX   \
diff --git a/drivers/pinmux/stm32/pinmux_stm32f3.h b/drivers/pinmux/stm32/pinmux_stm32f3.h
index 1b5cdb65ab0b9..fde72028ccdcb 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f3.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f3.h
@@ -115,4 +115,85 @@
 #define STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI  \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
 
+#define STM32F3_PINMUX_FUNC_PF2_ADC12_IN10	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PF4_ADC1_IN5	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC0_ADC12_IN6	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC1_ADC12_IN7	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC2_ADC12_IN8	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC3_ADC12_IN9	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA0_ADC1_IN1	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA1_ADC1_IN2	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA2_ADC1_IN3	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA3_ADC1_IN4	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA4_ADC2_IN1	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA5_ADC2_IN2	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA6_ADC2_IN3	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PA7_ADC2_IN4	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC4_ADC2_IN5	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PC5_ADC2_IN11	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB0_ADC3_IN12	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB1_ADC3_IN1	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB2_ADC2_IN12	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE7_ADC3_IN13	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE8_ADC34_IN6	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE9_ADC3_IN2	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE10_ADC3_IN14	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE11_ADC3_IN15	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE12_ADC3_IN16	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE13_ADC3_IN3	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE14_ADC4_IN1	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PE15_ADC4_IN12	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB11_ADC12_IN14	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB12_ADC4_IN3	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB13_ADC3_IN5	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB14_ADC4_IN4	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PB15_ADC4_IN5	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD8_ADC4_IN12	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD9_ADC4_IN13	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD10_ADC34_IN7	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD11_ADC12_IN8	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD12_ADC34_IN9	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD13_ADC34_IN10	\
+	STM32_MODER_ANALOG_MODE
+#define STM32F3_PINMUX_FUNC_PD14_ADC34_IN11	\
+	STM32_MODER_ANALOG_MODE
+
 #endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F3_H_ */
diff --git a/drivers/pinmux/stm32/pinmux_stm32f4.h b/drivers/pinmux/stm32/pinmux_stm32f4.h
index da934ad4ef7d3..8dc80e2a330ee 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f4.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f4.h
@@ -28,6 +28,8 @@
 #define STM32F4_PINMUX_FUNC_PA0_ETH			    \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA0_ADC123_IN0		\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA1_I2S4_SD    \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_PULLUP)
@@ -38,18 +40,24 @@
 #define STM32F4_PINMUX_FUNC_PA1_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA1_ADC123_IN1	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA2_USART2_TX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
 #define STM32F4_PINMUX_FUNC_PA2_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA2_ADC123_IN2	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA3_USART2_RX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
 #define STM32F4_PINMUX_FUNC_PA3_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA3_ADC123_IN3	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA4_SPI1_NSS    \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
@@ -57,6 +65,8 @@
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
 #define STM32F4_PINMUX_FUNC_PA4_I2S3_WS    \
 	(STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL)
+#define STM32F4_PINMUX_FUNC_PA4_ADC12_IN4	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA5_SPI1_SCK    \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL | \
@@ -64,9 +74,13 @@
 #define STM32F4_PINMUX_FUNC_PA5_I2S1_CK  \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA5_ADC12_IN5	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA6_SPI1_MISO   \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32F4_PINMUX_FUNC_PA6_ADC12_IN6	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI   \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
@@ -75,6 +89,8 @@
 #define STM32F4_PINMUX_FUNC_PA7_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PA7_ADC12_IN7	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PA8_MCO	    \
 	(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL | \
@@ -120,6 +136,11 @@
 #define STM32F4_PINMUX_FUNC_PB0_ETH			    \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PB0_ADC12_IN8	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F4_PINMUX_FUNC_PB1_ADC12_IN9	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PB3_I2S3_CK   \
 	(STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL | \
@@ -256,29 +277,42 @@
 	(STM32_PINMUX_ALT_FUNC_12 | STM32_PUSHPULL_NOPULL)
 
 /* Port C */
+#define STM32F4_PINMUX_FUNC_PC0_ADC123_IN10	\
+	STM32_MODER_ANALOG_MODE
+
 #define STM32F4_PINMUX_FUNC_PC1_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 #define STM32F4_PINMUX_FUNC_PC1_I2S2_SD    \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
+#define STM32F4_PINMUX_FUNC_PC1_ADC123_IN11	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PC2_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PC2_ADC123_IN12	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PC3_ETH			    \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PC3_ADC123_IN13	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PC4_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PC4_ADC12_IN14	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PC5_USART3_RX   \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
 #define STM32F4_PINMUX_FUNC_PC5_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F4_PINMUX_FUNC_PC5_ADC12_IN15	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PC6_PWM3_CH1    \
 	(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_NOPULL)
@@ -410,17 +444,37 @@
 #define STM32F4_PINMUX_FUNC_PF1_I2C2_SCL    \
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
 
+#define STM32F4_PINMUX_FUNC_PF3_ADC3_IN9	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F4_PINMUX_FUNC_PF4_ADC3_IN14	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F4_PINMUX_FUNC_PF5_ADC3_IN15	\
+	STM32_MODER_ANALOG_MODE
+
 #define STM32F4_PINMUX_FUNC_PF6_UART7_RX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
+#define STM32F4_PINMUX_FUNC_PF6_ADC3_IN4	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PF7_UART7_TX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32F4_PINMUX_FUNC_PF7_ADC3_IN5	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PF8_UART8_RX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
+#define STM32F4_PINMUX_FUNC_PF8_ADC3_IN6	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F4_PINMUX_FUNC_PF9_UART8_TX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32F4_PINMUX_FUNC_PF9_ADC3_IN7	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F4_PINMUX_FUNC_PF10_ADC3_IN8	\
+	STM32_MODER_ANALOG_MODE
 
 /* Port G */
 #define STM32F4_PINMUX_FUNC_PG0_UART9_RX    \
diff --git a/drivers/pinmux/stm32/pinmux_stm32f7.h b/drivers/pinmux/stm32/pinmux_stm32f7.h
index b69db88b2db40..d93c5382c5fe2 100644
--- a/drivers/pinmux/stm32/pinmux_stm32f7.h
+++ b/drivers/pinmux/stm32/pinmux_stm32f7.h
@@ -20,6 +20,8 @@
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PA0_UART4_TX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32F7_PINMUX_FUNC_PA0_ADC123_IN0	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA1_PWM2_CH2 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -34,6 +36,8 @@
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 #define STM32F7_PINMUX_FUNC_PA1_LTDC_R2 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA1_ADC123_IN1	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA2_PWM2_CH3 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -48,6 +52,8 @@
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 #define STM32F7_PINMUX_FUNC_PA2_LTDC_R1 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA2_ADC123_IN2	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA3_PWM2_CH4 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -62,11 +68,15 @@
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 #define STM32F7_PINMUX_FUNC_PA3_LTDC_B5 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA3_ADC123_IN3	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA4_SPI1_NSS \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
 #define STM32F7_PINMUX_FUNC_PA4_LTDC_VSYNC \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA4_ADC12_IN4	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA5_PWM2_CH1 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -76,6 +86,8 @@
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
 #define STM32F7_PINMUX_FUNC_PA5_LTDC_R4 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA5_ADC12_IN5	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA6_PWM3_CH1 \
 	(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP)
@@ -85,6 +97,8 @@
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
 #define STM32F7_PINMUX_FUNC_PA6_LTDC_G2 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA6_ADC12_IN6	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA7_PWM1_CH1N \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -99,6 +113,8 @@
 	(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PA7_SPI1_MOSI \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PA7_ADC12_IN7	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PA8_PWM1_CH1 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -153,6 +169,8 @@
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PB0_LTDC_R3 \
 	(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PB0_ADC12_IN8	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PB1_PWM1_CH3N \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -162,6 +180,8 @@
 	(STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PB1_LTDC_R6 \
 	(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PB1_ADC12_IN9	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PB3_PWM2_CH2 \
 	(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
@@ -279,26 +299,38 @@
 /* Port C */
 #define STM32F7_PINMUX_FUNC_PC0_LTDC_R5 \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PC0_ADC123_IN10	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC1_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
 #define STM32F7_PINMUX_FUNC_PC1_SPI2_MOSI	\
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PC1_ADC123_IN11	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC2_SPI2_MISO	\
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PC2_ADC123_IN12	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC3_SPI2_MOSI	\
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PC3_ADC123_IN13	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC4_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F7_PINMUX_FUNC_PC4_ADC12_IN14	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC5_ETH         \
 	(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
 	 STM32_OSPEEDR_VERY_HIGH_SPEED)
+#define STM32F7_PINMUX_FUNC_PC5_ADC12_IN15	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PC6_PWM3_CH1 \
 	(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP)
@@ -476,25 +508,45 @@
 #define STM32F7_PINMUX_FUNC_PF1_I2C2_SCL   \
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
 
+#define STM32F7_PINMUX_FUNC_PF3_ADC3_IN9	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F7_PINMUX_FUNC_PF4_ADC3_IN14	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F7_PINMUX_FUNC_PF5_ADC3_IN15	\
+	STM32_MODER_ANALOG_MODE
+
 #define STM32F7_PINMUX_FUNC_PF6_PWM10_CH1 \
 	(STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PF6_UART7_RX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
+#define STM32F7_PINMUX_FUNC_PF6_ADC3_IN4	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PF7_PWM11_CH1 \
 	(STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PF7_UART7_TX    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32F7_PINMUX_FUNC_PF7_ADC3_IN5	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PF8_UART7_RTS    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PF8_PWM13_CH1 \
 	(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
+#define STM32F7_PINMUX_FUNC_PF8_ADC3_IN6	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PF9_UART7_CTS    \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
 #define STM32F7_PINMUX_FUNC_PF9_PWM14_CH1 \
 	(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
+#define STM32F7_PINMUX_FUNC_PF9_ADC3_IN7	\
+	STM32_MODER_ANALOG_MODE
+
+#define STM32F7_PINMUX_FUNC_PF10_ADC3_IN8	\
+	STM32_MODER_ANALOG_MODE
 
 #define STM32F7_PINMUX_FUNC_PF10_LTDC_DE \
 	(STM32_PINMUX_ALT_FUNC_14 | STM32_PUSHPULL_NOPULL)
diff --git a/drivers/pinmux/stm32/pinmux_stm32l0.h b/drivers/pinmux/stm32/pinmux_stm32l0.h
index 04b57dd0750d2..965893f6b66ad 100644
--- a/drivers/pinmux/stm32/pinmux_stm32l0.h
+++ b/drivers/pinmux/stm32/pinmux_stm32l0.h
@@ -108,4 +108,37 @@
 #define STM32L0_PINMUX_FUNC_PC3_SPI2_MOSI \
 	(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_NOPULL)
 
+#define STM32L0_PINMUX_FUNC_PC0_ADC_IN10 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PC1_ADC_IN11 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PC2_ADC_IN12 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PC3_ADC_IN13 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA0_ADC_IN0 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA1_ADC_IN1 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA2_ADC_IN2 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA3_ADC_IN3 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA4_ADC_IN4 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA5_ADC_IN5 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA6_ADC_IN6 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PA7_ADC_IN7 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PC4_ADC_IN14 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PC5_ADC_IN15 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PB0_ADC_IN8 \
+	STM32_MODER_ANALOG_MODE
+#define STM32L0_PINMUX_FUNC_PB1_ADC_IN9 \
+	STM32_MODER_ANALOG_MODE
+
 #endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32L0_H_ */
diff --git a/drivers/pinmux/stm32/pinmux_stm32l4x.h b/drivers/pinmux/stm32/pinmux_stm32l4x.h
index 42d0d832c0d7f..dffba7328c775 100644
--- a/drivers/pinmux/stm32/pinmux_stm32l4x.h
+++ b/drivers/pinmux/stm32/pinmux_stm32l4x.h
@@ -20,23 +20,35 @@
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PA0_UART4_TX \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PA0_ADC12_IN5   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA1_USART2_RTS \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PA1_UART4_RX \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUPDR_NO_PULL)
+#define STM32L4X_PINMUX_FUNC_PA1_ADC12_IN6   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA2_USART2_TX \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PA2_ADC12_IN7   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA3_USART2_RX \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)
+#define STM32L4X_PINMUX_FUNC_PA3_ADC12_IN8   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA4_SPI1_NSS \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32L4X_PINMUX_FUNC_PA4_ADC12_IN9   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA5_SPI1_SCK \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32L4X_PINMUX_FUNC_PA5_ADC12_IN10   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA6_SPI1_MISO \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
@@ -44,9 +56,13 @@
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PA6_LPUART1_CTS \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_OPENDRAIN_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PA6_ADC12_IN11   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA7_SPI1_MOSI \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
+#define STM32L4X_PINMUX_FUNC_PA7_ADC12_IN12   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PA9_USART1_TX \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
@@ -80,10 +96,15 @@
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_OPENDRAIN_PULLUP)
 
 /* Port B */
+#define STM32L4X_PINMUX_FUNC_PB0_ADC12_IN15   \
+	STM32_MODER_ANALOG_MODE
+
 #define STM32L4X_PINMUX_FUNC_PB1_USART3_RTS \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PB1_LPUART1_RTS \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_OPENDRAIN_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PB1_ADC12_IN16   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PB3_SPI1_SCK \
 	(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
@@ -154,17 +175,31 @@
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PC0_LPUART1_RX \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUPDR_NO_PULL)
+#define STM32L4X_PINMUX_FUNC_PC0_ADC123_IN1   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PC1_I2C3_SDA \
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
 #define STM32L4X_PINMUX_FUNC_PC1_LPUART1_TX \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PC1_ADC123_IN2   \
+	STM32_MODER_ANALOG_MODE
+
+#define STM32L4X_PINMUX_FUNC_PC2_ADC123_IN3   \
+	STM32_MODER_ANALOG_MODE
+
+#define STM32L4X_PINMUX_FUNC_PC3_ADC123_IN4   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PC4_USART3_TX \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PC4_ADC12_IN13   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PC5_USART3_RX \
 	(STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)
+#define STM32L4X_PINMUX_FUNC_PC5_ADC12_IN14   \
+	STM32_MODER_ANALOG_MODE
 
 #define STM32L4X_PINMUX_FUNC_PC6_USART6_TX \
 	(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
@@ -239,6 +274,22 @@
 
 #define STM32L4X_PINMUX_FUNC_PF1_I2C3_SCL \
 	(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
+#define STM32L4X_PINMUX_FUNC_PF3_ADC3_IN6   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF4_ADC3_IN7   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF5_ADC3_IN8   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF6_ADC3_IN9   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF7_ADC3_IN10   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF8_ADC3_IN11   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF9_ADC3_IN12   \
+	STM32_MODER_ANALOG_MODE
+#define STM32L4X_PINMUX_FUNC_PF10_ADC3_IN13   \
+	STM32_MODER_ANALOG_MODE
 
 /* Port G */
 #define STM32L4X_PINMUX_FUNC_PG7_I2C3_SCL \
diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi
index 162d2d228df7a..e32e368423503 100644
--- a/dts/arm/st/f0/stm32f0.dtsi
+++ b/dts/arm/st/f0/stm32f0.dtsi
@@ -293,6 +293,15 @@
 				#pwm-cells = <2>;
 			};
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 };
 
diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi
index 80668f9c84792..09b7b566e3e45 100644
--- a/dts/arm/st/f1/stm32f1.dtsi
+++ b/dts/arm/st/f1/stm32f1.dtsi
@@ -227,6 +227,15 @@
 				#pwm-cells = <2>;
 			};
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 };
 
diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi
index 45241a0c6203b..05059165af820 100644
--- a/dts/arm/st/f2/stm32f2.dtsi
+++ b/dts/arm/st/f2/stm32f2.dtsi
@@ -213,6 +213,15 @@
 			status = "disabled";
 			label = "OTGFS";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {
diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi
index 6e3461d46aef0..9b0ea00c03bfe 100644
--- a/dts/arm/st/f3/stm32f3.dtsi
+++ b/dts/arm/st/f3/stm32f3.dtsi
@@ -297,6 +297,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@50000000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50000000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 
 	usb_fs_phy: usbphy {
diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi
index cd519c51dbbc9..209c6ca2fd3a4 100644
--- a/dts/arm/st/f4/stm32f4.dtsi
+++ b/dts/arm/st/f4/stm32f4.dtsi
@@ -359,6 +359,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
index cfe79bd57e4e0..e53cbb52f1ebb 100644
--- a/dts/arm/st/f7/stm32f7.dtsi
+++ b/dts/arm/st/f7/stm32f7.dtsi
@@ -595,6 +595,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@40012000 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 
 	otghs_fs_phy: otghs_fs_phy {
diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi
index e78f640ed985f..c6e0f844f4098 100644
--- a/dts/arm/st/l0/stm32l0.dtsi
+++ b/dts/arm/st/l0/stm32l0.dtsi
@@ -162,6 +162,15 @@
 			status = "disabled";
 			label = "SPI_1";
 		};
+
+		adc1: adc@40012400 {
+			compatible = "st,stm32-adc";
+			reg = <0x40012400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			interrupts = <12 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 };
 
diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
index d1f911d7465d9..826a15b0ae665 100644
--- a/dts/arm/st/l4/stm32l4.dtsi
+++ b/dts/arm/st/l4/stm32l4.dtsi
@@ -291,6 +291,15 @@
 			status = "disabled";
 			label = "RTC_0";
 		};
+
+		adc1: adc@50040000 {
+			compatible = "st,stm32-adc";
+			reg = <0x50040000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			interrupts = <18 0>;
+			status = "disabled";
+			label = "ADC_1";
+		};
 	};
 };
 
diff --git a/dts/bindings/iio/adc/st,stm32-adc.yaml b/dts/bindings/iio/adc/st,stm32-adc.yaml
new file mode 100644
index 0000000000000..56368338504e4
--- /dev/null
+++ b/dts/bindings/iio/adc/st,stm32-adc.yaml
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2018, Endre Karlson
+# Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: ST STM32 family ADC
+version: 0.1
+
+description: >
+    This binding gives a base representation of the ST STM32 ADC
+
+inherits:
+    !include adc.yaml
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "st,stm32-adc"
+
+    reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+    clocks:
+      type: array
+      category: required
+      description: Clock gate control information
+      generation: define
+
+    interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+...
diff --git a/soc/arm/st_stm32/common/Kconfig.defconfig.series b/soc/arm/st_stm32/common/Kconfig.defconfig.series
index dfc364b4ef075..6349e2c16d365 100644
--- a/soc/arm/st_stm32/common/Kconfig.defconfig.series
+++ b/soc/arm/st_stm32/common/Kconfig.defconfig.series
@@ -95,4 +95,11 @@ config CAN_STM32
 
 endif
 
+if ADC
+
+config ADC_STM32
+	default y
+
+endif # ADC
+
 endif # SOC_FAMILY_STM32
diff --git a/soc/arm/st_stm32/stm32f0/dts_fixup.h b/soc/arm/st_stm32/stm32f0/dts_fixup.h
index ce2df49bd9232..8536285016d15 100644
--- a/soc/arm/st_stm32/stm32f0/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f0/dts_fixup.h
@@ -187,4 +187,11 @@
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
 
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012400_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012400_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012400_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012400_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f0/soc.h b/soc/arm/st_stm32/stm32f0/soc.h
index c57965f789c9a..9e838d1ceb413 100644
--- a/soc/arm/st_stm32/stm32f0/soc.h
+++ b/soc/arm/st_stm32/stm32f0/soc.h
@@ -59,6 +59,10 @@
 #include <stm32f0xx_ll_gpio.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f0xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F0_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32f1/dts_fixup.h b/soc/arm/st_stm32/stm32f1/dts_fixup.h
index 81cd435f55f93..f2ccab533436d 100644
--- a/soc/arm/st_stm32/stm32f1/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f1/dts_fixup.h
@@ -207,4 +207,11 @@
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
 
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012400_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012400_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012400_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012400_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f1/soc.h b/soc/arm/st_stm32/stm32f1/soc.h
index b12f359b50773..5a69f5f1c0ecc 100644
--- a/soc/arm/st_stm32/stm32f1/soc.h
+++ b/soc/arm/st_stm32/stm32f1/soc.h
@@ -59,6 +59,10 @@
 #include <stm32f1xx_ll_gpio.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f1xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F1_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32f2/dts_fixup.h b/soc/arm/st_stm32/stm32f2/dts_fixup.h
index 8be29b46e1b0a..9bf1c0119343b 100644
--- a/soc/arm/st_stm32/stm32f2/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f2/dts_fixup.h
@@ -148,4 +148,11 @@
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
 
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012000_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012000_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012000_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012000_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f2/soc.h b/soc/arm/st_stm32/stm32f2/soc.h
index 2582b565648ef..f2fdfa4f044c3 100644
--- a/soc/arm/st_stm32/stm32f2/soc.h
+++ b/soc/arm/st_stm32/stm32f2/soc.h
@@ -50,6 +50,10 @@
 #include <stm32f2xx_ll_iwdg.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f2xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F2_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32f3/dts_fixup.h b/soc/arm/st_stm32/stm32f3/dts_fixup.h
index a4da929fae8f1..3f24fd9006de9 100644
--- a/soc/arm/st_stm32/stm32f3/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f3/dts_fixup.h
@@ -263,4 +263,12 @@
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
 #define DT_RTC_0_CLOCK_BITS                 DT_ST_STM32_RTC_40002800_CLOCK_BITS
 #define DT_RTC_0_CLOCK_BUS                  DT_ST_STM32_RTC_40002800_CLOCK_BUS
+
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_50000000_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_50000000_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_50000000_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_50000000_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_50000000_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_50000000_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f3/soc.h b/soc/arm/st_stm32/stm32f3/soc.h
index 47f3a938b68de..eb0202cd3a697 100644
--- a/soc/arm/st_stm32/stm32f3/soc.h
+++ b/soc/arm/st_stm32/stm32f3/soc.h
@@ -66,6 +66,10 @@
 #include <stm32f3xx_ll_gpio.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f3xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F3_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32f4/dts_fixup.h b/soc/arm/st_stm32/stm32f4/dts_fixup.h
index 1d31916175cc5..00577d30321fa 100644
--- a/soc/arm/st_stm32/stm32f4/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f4/dts_fixup.h
@@ -386,4 +386,12 @@
 #define DT_RTC_0_CLOCK_BUS                  DT_ST_STM32_RTC_40002800_CLOCK_BUS
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
+
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012000_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012000_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012000_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012000_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f4/soc.h b/soc/arm/st_stm32/stm32f4/soc.h
index d0af3973850c0..5f00892031dde 100644
--- a/soc/arm/st_stm32/stm32f4/soc.h
+++ b/soc/arm/st_stm32/stm32f4/soc.h
@@ -69,6 +69,10 @@
 #include <stm32f4xx_ll_gpio.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f4xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F4_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h
index 68d6cb32864b7..5b423b736da42 100644
--- a/soc/arm/st_stm32/stm32f7/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h
@@ -386,4 +386,12 @@
 #define DT_CAN_1_CLOCK_BITS		DT_ST_STM32_CAN_40006400_CLOCK_BITS
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
+
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012000_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012000_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012000_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012000_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32f7/soc.h b/soc/arm/st_stm32/stm32f7/soc.h
index 287be586bcf4f..2c33c4e1b0781 100644
--- a/soc/arm/st_stm32/stm32f7/soc.h
+++ b/soc/arm/st_stm32/stm32f7/soc.h
@@ -68,6 +68,10 @@
 #include <stm32f7xx_ll_iwdg.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32f7xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F7_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32l0/dts_fixup.h b/soc/arm/st_stm32/stm32l0/dts_fixup.h
index fd2f5bfff4cb7..9f2477aa19f8b 100644
--- a/soc/arm/st_stm32/stm32l0/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32l0/dts_fixup.h
@@ -132,4 +132,12 @@
 #define DT_USB_RAM_SIZE			DT_ST_STM32_USB_40005C00_RAM_SIZE
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
+
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_40012400_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_40012400_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_40012400_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_40012400_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32l0/soc.h b/soc/arm/st_stm32/stm32l0/soc.h
index 4f8d826667a64..4fbbdb3cb84cb 100644
--- a/soc/arm/st_stm32/stm32l0/soc.h
+++ b/soc/arm/st_stm32/stm32l0/soc.h
@@ -60,6 +60,10 @@
 #include <stm32l0xx_ll_iwdg.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32l0xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L0_SOC_H_ */
diff --git a/soc/arm/st_stm32/stm32l4/dts_fixup.h b/soc/arm/st_stm32/stm32l4/dts_fixup.h
index f9e12418c4da1..25e9107529608 100644
--- a/soc/arm/st_stm32/stm32l4/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32l4/dts_fixup.h
@@ -310,4 +310,12 @@
 #define DT_CAN_1_CLOCK_BITS			DT_ST_STM32_CAN_40006400_CLOCK_BITS
 
 #define DT_WDT_0_NAME                   DT_ST_STM32_WATCHDOG_0_LABEL
+
+#define DT_ADC_1_BASE_ADDRESS		DT_ST_STM32_ADC_50040000_BASE_ADDRESS
+#define DT_ADC_1_IRQ			DT_ST_STM32_ADC_50040000_IRQ_0
+#define DT_ADC_1_IRQ_PRI		DT_ST_STM32_ADC_50040000_IRQ_0_PRIORITY
+#define DT_ADC_1_NAME			DT_ST_STM32_ADC_50040000_LABEL
+#define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_50040000_CLOCK_BITS_0
+#define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_50040000_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32l4/soc.h b/soc/arm/st_stm32/stm32l4/soc.h
index 19321ca562081..12b10cec60e2a 100644
--- a/soc/arm/st_stm32/stm32l4/soc.h
+++ b/soc/arm/st_stm32/stm32l4/soc.h
@@ -83,6 +83,10 @@
 #include <stm32l4xx_ll_gpio.h>
 #endif
 
+#ifdef CONFIG_ADC_STM32
+#include <stm32l4xx_ll_adc.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L4X_SOC_H_ */
diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c
index ef0cbc2036035..10371dc82733f 100644
--- a/tests/drivers/adc/adc_api/src/test_adc.c
+++ b/tests/drivers/adc/adc_api/src/test_adc.c
@@ -123,13 +123,43 @@
 
 #elif defined(CONFIG_SOC_FAMILY_SAM0)
 #include <soc.h>
-#define ADC_DEVICE_NAME		DT_ATMEL_SAM0_ADC_0_LABEL
+#define ADC_DEVICE_NAME         DT_ATMEL_SAM0_ADC_0_LABEL
+#define ADC_RESOLUTION          12
+#define ADC_GAIN                ADC_GAIN_1
+#define ADC_REFERENCE           ADC_REF_INTERNAL
+#define ADC_ACQUISITION_TIME    ADC_ACQ_TIME_DEFAULT
+#define ADC_1ST_CHANNEL_ID      0
+#define ADC_1ST_CHANNEL_INPUT   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val
+
+#elif defined(CONFIG_BOARD_NUCLEO_F091RC) || \
+	defined(CONFIG_BOARD_NUCLEO_F103RB) || \
+	defined(CONFIG_BOARD_NUCLEO_F207ZG) || \
+	defined(CONFIG_BOARD_NUCLEO_F401RE) || \
+	defined(CONFIG_BOARD_NUCLEO_F746ZG) || \
+	defined(CONFIG_BOARD_NUCLEO_L073RZ)
+#define ADC_DEVICE_NAME		DT_ADC_1_NAME
 #define ADC_RESOLUTION		12
 #define ADC_GAIN		ADC_GAIN_1
 #define ADC_REFERENCE		ADC_REF_INTERNAL
 #define ADC_ACQUISITION_TIME	ADC_ACQ_TIME_DEFAULT
 #define ADC_1ST_CHANNEL_ID	0
-#define ADC_1ST_CHANNEL_INPUT	ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val
+
+#elif defined(CONFIG_BOARD_NUCLEO_F302R8)
+#define ADC_DEVICE_NAME		DT_ADC_1_NAME
+#define ADC_RESOLUTION		12
+#define ADC_GAIN		ADC_GAIN_1
+#define ADC_REFERENCE		ADC_REF_INTERNAL
+#define ADC_ACQUISITION_TIME	ADC_ACQ_TIME_DEFAULT
+/* Some F3 series SOCs do not have channel 0 connected to an external GPIO. */
+#define ADC_1ST_CHANNEL_ID	1
+
+#elif defined(CONFIG_BOARD_NUCLEO_L476RG)
+#define ADC_DEVICE_NAME		DT_ADC_1_NAME
+#define ADC_RESOLUTION		10
+#define ADC_GAIN		ADC_GAIN_1
+#define ADC_REFERENCE		ADC_REF_INTERNAL
+#define ADC_ACQUISITION_TIME	ADC_ACQ_TIME_DEFAULT
+#define ADC_1ST_CHANNEL_ID	1
 
 #else
 #error "Unsupported board."