diff --git a/boards/arm/mimxrt1015_evk/CMakeLists.txt b/boards/arm/mimxrt1015_evk/CMakeLists.txt new file mode 100644 index 0000000000000..c03042225ad38 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_library_sources(pinmux.c) diff --git a/boards/arm/mimxrt1015_evk/Kconfig.board b/boards/arm/mimxrt1015_evk/Kconfig.board new file mode 100644 index 0000000000000..d4890f9ab5a8f --- /dev/null +++ b/boards/arm/mimxrt1015_evk/Kconfig.board @@ -0,0 +1,10 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT1015_EVK + bool "NXP MIMXRT1015-EVK" + depends on SOC_SERIES_IMX_RT + select SOC_PART_NUMBER_MIMXRT1015DAF5A diff --git a/boards/arm/mimxrt1015_evk/Kconfig.defconfig b/boards/arm/mimxrt1015_evk/Kconfig.defconfig new file mode 100644 index 0000000000000..7085044022776 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# Kconfig - MIMXRT1015-EVK board +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_MIMXRT1015_EVK + +config BOARD + default "mimxrt1015_evk" if BOARD_MIMXRT1015_EVK + +choice CODE_LOCATION + default CODE_FLEXSPI +endchoice + +if GPIO_MCUX_IGPIO + +config GPIO_MCUX_IGPIO_2 + default y + +config GPIO_MCUX_IGPIO_3 + default y + +endif # GPIO_MCUX_IGPIO + +if I2C_MCUX_LPI2C + +config I2C_1 + default y + +endif # I2C_MCUX_LPI2C + +if UART_MCUX_LPUART + +config UART_MCUX_LPUART_1 + default y + +config UART_MCUX_LPUART_4 + default y + +endif # UART_MCUX_LPUART + +endif # BOARD_MIMXRT1015_EVK diff --git a/boards/arm/mimxrt1015_evk/board.cmake b/boards/arm/mimxrt1015_evk/board.cmake new file mode 100644 index 0000000000000..ccbdb620d9083 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/board.cmake @@ -0,0 +1,14 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +set_ifndef(OPENSDA_FW jlink) + +if(OPENSDA_FW STREQUAL jlink) + set_ifndef(BOARD_DEBUG_RUNNER jlink) + set_ifndef(BOARD_FLASH_RUNNER jlink) +endif() + +board_runner_args(jlink "--device=MIMXRT1015") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/mimxrt1015_evk/doc/index.rst b/boards/arm/mimxrt1015_evk/doc/index.rst new file mode 100644 index 0000000000000..aae682c81b528 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/doc/index.rst @@ -0,0 +1,197 @@ +.. _mimxrt1015_evk: + +NXP MIMXRT1015-EVK +################## + +Overview +******** + +The i.MX RT1015 expands the i.MX RT crossover processor families by providing +high-performance feature set in low-cost LQFP packages, further simplifying +board design and layout for customers. The i.MX RT1015 runs on the Arm® +Cortex®-M7 core at 500 MHz. + +.. image:: ./mimxrt1015_evk.jpg + :width: 720px + :align: center + :alt: MIMXRT1015-EVK + +Hardware +******** + +- MIMXRT1015DAF5A MCU + +- Memory + + - 128 Mbit QSPI Flash + +- Connectivity + + - Micro USB host and OTG connectors + - Arduino interface + +- Audio + + - Audio Codec + - 4-pole audio headphone jack + - External speaker connection + - Microphone + +- Debug + + - JTAG 10-pin connector + - OpenSDA with DAPLink + +For more information about the MIMXRT1015 SoC and MIMXRT1015-EVK board, see +these references: + +- `i.MX RT1015 Website`_ +- `i.MX RT1015 Datasheet`_ +- `i.MX RT1015 Reference Manual`_ +- `MIMXRT1015-EVK Website`_ +- `MIMXRT1015-EVK Quick Reference Guide`_ +- `MIMXRT1015-EVK Design Files`_ + +Supported Features +================== + +The mimxrt1015_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1015 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_05 | GPIO | LED | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_09 | GPIO | SW4 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_06 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_07 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_32 | LPUART4_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_33 | LPUART4_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_15 | LPI2C1_SDA | I2C SDA | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_14 | LPI2C1_CLK | I2C SCL | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The MIMXRT1015 SoC is configured to use the 24 MHz external oscillator on the +board with the on-chip PLL to generate a 500 MHz core clock. + +Serial Port +=========== + +The MIMXRT1015 SoC has four UARTs. ``LPUART1`` is configured for the console, +and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +:ref:`jlink-external-debug-probe` +------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 10-pin connector to J55. Check that jumpers J47 and J48 are +**off** (they are on by default when boards ship from the factory) to ensure +SWD signals are disconnected from the OpenSDA microcontroller. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J45 and J46 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J41. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1015_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW9 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1-1297-g312d75f2459e ***** + Hello World! mimxrt1015_evk + + +.. _MIMXRT1015-EVK Website: + https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-rt1015-evaluation-kit:MIMXRT1015-EVK + +.. _MIMXRT1015-EVK Quick Reference Guide: + https://www.nxp.com/docs/en/quick-reference-guide/IMXRT1015QSG.pdf + +.. _MIMXRT1015-EVK Design Files: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1015-EVK-REVB-DS + +.. _i.MX RT1015 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1015-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1015 + +.. _i.MX RT1015 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1015CEC.pdf + +.. _i.MX RT1015 Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMXRT1015RM.pdf + diff --git a/boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg b/boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg new file mode 100644 index 0000000000000..c7f8e03f4d92c Binary files /dev/null and b/boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg differ diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts new file mode 100644 index 0000000000000..8fca5d69c0d25 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "NXP MIMXRT1015-EVK board"; + compatible = "nxp,mimxrt1015"; + + aliases { + gpio-1= &gpio1; + gpio-2= &gpio2; + gpio-3= &gpio3; + gpio-4= &gpio4; + gpio-5= &gpio5; + i2c-1 = &i2c1; + uart-1 = &uart1; + uart-4 = &uart4; + led0 = &green_led; + sw0 = &user_button; + }; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + leds { + compatible = "gpio-leds"; + green_led: led-1 { + gpios = <&gpio3 21 GPIO_INT_ACTIVE_LOW>; + label = "User LD1"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button-1 { + label = "User SW4"; + gpios = <&gpio2 9 GPIO_INT_ACTIVE_LOW>; + }; + }; +}; + +arduino_serial: &uart4 {}; + +&flexspi0 { + reg = <0x402a8000 0x4000>, <0x60000000 0x1000000>; + at25sf128a: at25sf128a@0 { + compatible = "adesto,at25sf128a", "jedec,spi-nor"; + reg = <0>; + status = "ok"; + }; +}; + +&i2c1 { + status = "ok"; +}; + +&uart1 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml new file mode 100644 index 0000000000000..a2107f07e276e --- /dev/null +++ b/boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1015_evk +name: NXP MIMXRT1015-EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 16384 +supported: + - i2c + - hwinfo diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig b/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig new file mode 100644 index 0000000000000..0af1f20fd728d --- /dev/null +++ b/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig @@ -0,0 +1,17 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_ARM=y +CONFIG_SOC_MIMXRT1015=y +CONFIG_SOC_SERIES_IMX_RT=y +CONFIG_BOARD_MIMXRT1015_EVK=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000 +CONFIG_ARM_MPU=y diff --git a/boards/arm/mimxrt1015_evk/pinmux.c b/boards/arm/mimxrt1015_evk/pinmux.c new file mode 100644 index 0000000000000..444d7f327c382 --- /dev/null +++ b/boards/arm/mimxrt1015_evk/pinmux.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2019, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static int mimxrt1015_evk_init(struct device *dev) +{ + ARG_UNUSED(dev); + + CLOCK_EnableClock(kCLOCK_Iomuxc); + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); + +#ifdef CONFIG_GPIO_MCUX_IGPIO_2 + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0); + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PUE(1) | + IOMUXC_SW_PAD_CTL_PAD_PUS(2) | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(4)); +#endif + +#ifdef CONFIG_UART_MCUX_LPUART_1 + /* LPUART1 TX/RX */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + +#ifdef CONFIG_UART_MCUX_LPUART_4 + /* LPUART4 TX/RX */ + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_LPUART4_TX, 0); + IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_LPUART4_RX, 0); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_LPUART4_TX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_33_LPUART4_RX, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + +#ifdef CONFIG_I2C_1 + /* LPI2C1 SCL, SDA */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL, 1); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA, 1); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); + + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA, + IOMUXC_SW_PAD_CTL_PAD_PUS(3) | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | + IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6)); +#endif + + return 0; +} + +SYS_INIT(mimxrt1015_evk_init, PRE_KERNEL_1, 0); diff --git a/drivers/serial/Kconfig.mcux_lpuart b/drivers/serial/Kconfig.mcux_lpuart index d9f1440a76242..2c5cf63e4aafb 100644 --- a/drivers/serial/Kconfig.mcux_lpuart +++ b/drivers/serial/Kconfig.mcux_lpuart @@ -35,4 +35,9 @@ menuconfig UART_MCUX_LPUART_3 help Enable UART 3. +menuconfig UART_MCUX_LPUART_4 + bool "UART 4" + help + Enable UART 4. + endif # UART_MCUX_LPUART diff --git a/ext/hal/nxp/mcux/README b/ext/hal/nxp/mcux/README index 28ac7209ef1b6..d3dbea42f3ea6 100644 --- a/ext/hal/nxp/mcux/README +++ b/ext/hal/nxp/mcux/README @@ -15,6 +15,7 @@ Status: SoC Version (Release Date) Tag ---------------------------------------------------------------------------- + MIMXRT1015 SDK 2.5.0 (2019-03-11) REL_2.5.0_RT1015_RFP LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 diff --git a/ext/hal/nxp/mcux/boards/CMakeLists.txt b/ext/hal/nxp/mcux/boards/CMakeLists.txt index 308c07c1259a6..411d6b3363596 100644 --- a/ext/hal/nxp/mcux/boards/CMakeLists.txt +++ b/ext/hal/nxp/mcux/boards/CMakeLists.txt @@ -4,6 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # +add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1015_EVK evkmimxrt1015) add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1020_EVK evkmimxrt1020) add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1050_EVK evkbimxrt1050) add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1050_EVK_QSPI evkbimxrt1050) diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1015/CMakeLists.txt b/ext/hal/nxp/mcux/boards/evkmimxrt1015/CMakeLists.txt new file mode 100644 index 0000000000000..5d0410f2dde03 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1015/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1) +zephyr_compile_definitions_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA XIP_BOOT_HEADER_DCD_ENABLE=1) + +zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR evkmimxrt1015_flexspi_nor_config.c) diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.c b/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.c new file mode 100644 index 0000000000000..a396fe60d8a6f --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.c @@ -0,0 +1,48 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1015_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.h b/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.h new file mode 100644 index 0000000000000..94af5a1151939 --- /dev/null +++ b/ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.h @@ -0,0 +1,268 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.h new file mode 100644 index 0000000000000..2dbc28d96d4ff --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.h @@ -0,0 +1,32299 @@ +/* +** ################################################################### +** Processors: MIMXRT1015CAF4A +** MIMXRT1015DAF5A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1015RM Rev.0, 12/2018 +** Version: rev. 1.1, 2019-02-20 +** Build: b190221 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMXRT1015 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2018-11-05) +** Initial version. +** - rev. 1.0 (2019-01-18) +** Rev.0 Header GA +** - rev. 1.1 (2019-02-20) +** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1015.h + * @version 1.1 + * @date 2019-02-20 + * @brief CMSIS Peripheral Access Layer for MIMXRT1015 + * + * CMSIS Peripheral Access Layer for MIMXRT1015 + */ + +#ifndef _MIMXRT1015_H_ +#define _MIMXRT1015_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 150 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ + DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ + DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ + DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ + DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ + DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ + DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ + DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ + DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ + DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ + DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ + DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ + DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ + DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ + DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ + DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ + DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ + CTI0_ERROR_IRQn = 17, /**< CTI trigger outputs */ + CTI1_ERROR_IRQn = 18, /**< CTI trigger outputs */ + CORE_IRQn = 19, /**< CorePlatform exception IRQ */ + LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ + LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ + LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ + LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ + Reserved40_IRQn = 24, /**< Reserved interrupt */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + Reserved43_IRQn = 27, /**< Reserved interrupt */ + LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ + LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + Reserved47_IRQn = 31, /**< Reserved interrupt */ + LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ + LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ + Reserved50_IRQn = 34, /**< Reserved interrupt */ + Reserved51_IRQn = 35, /**< Reserved interrupt */ + Reserved52_IRQn = 36, /**< Reserved interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt */ + FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ + KPP_IRQn = 39, /**< Keypad nterrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + GPR_IRQ_IRQn = 41, /**< Used to notify cores on exception condition while boot */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + WDOG2_IRQn = 45, /**< WDOG2 interrupt */ + SNVS_HP_WRAPPER_IRQn = 46, /**< SNVS Functional Interrupt */ + SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SNVS Security Interrupt */ + SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + CSU_IRQn = 49, /**< CSU interrupt */ + DCP_IRQn = 50, /**< Combined DCP channel interrupts(except channel 0) and CRC interrupt */ + DCP_VMI_IRQn = 51, /**< IRQ of DCP channel 0 */ + Reserved68_IRQn = 52, /**< Reserved interrupt */ + TRNG_IRQn = 53, /**< TRNG interrupt */ + Reserved70_IRQn = 54, /**< Reserved interrupt */ + BEE_IRQn = 55, /**< BEE interrupt */ + SAI1_IRQn = 56, /**< SAI1 interrupt */ + SAI2_IRQn = 57, /**< SAI1 interrupt */ + SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ + SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ + SPDIF_IRQn = 60, /**< SPDIF interrupt */ + PMU_IRQn = 61, /**< PMU interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TEMPMON interrupt */ + TEMP_PANIC_IRQn = 64, /**< TEMPMON interrupt */ + USB_PHY_IRQn = 65, /**< USBPHY (OTG1 UTMI), Interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + ADC1_IRQn = 67, /**< ADC1 interrupt */ + Reserved84_IRQn = 68, /**< Reserved interrupt */ + DCDC_IRQn = 69, /**< DCDC interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + Reserved102_IRQn = 86, /**< Reserved interrupt */ + Reserved103_IRQn = 87, /**< Reserved interrupt */ + GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + WDOG1_IRQn = 92, /**< WDOG1 interrupt */ + RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ + EWM_IRQn = 94, /**< EWM interrupt */ + CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ + CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ + GPC_IRQn = 97, /**< GPC interrupt */ + SRC_IRQn = 98, /**< SRC interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + GPT1_IRQn = 100, /**< GPT1 interrupt */ + GPT2_IRQn = 101, /**< GPT2 interrupt */ + PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ + PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ + PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ + PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ + PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ + Reserved125_IRQn = 109, /**< Reserved interrupt */ + Reserved126_IRQn = 110, /**< Reserved interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + Reserved128_IRQn = 112, /**< Reserved interrupt */ + USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ + Reserved130_IRQn = 114, /**< Reserved interrupt */ + Reserved131_IRQn = 115, /**< Reserved interrupt */ + XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ + XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ + ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ + ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ + ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ + ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ + PIT_IRQn = 122, /**< PIT interrupt */ + Reserved139_IRQn = 123, /**< Reserved interrupt */ + Reserved140_IRQn = 124, /**< Reserved interrupt */ + Reserved141_IRQn = 125, /**< Reserved interrupt */ + Reserved142_IRQn = 126, /**< Reserved interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + ENC1_IRQn = 129, /**< ENC1 interrupt */ + Reserved146_IRQn = 130, /**< Reserved interrupt */ + Reserved147_IRQn = 131, /**< Reserved interrupt */ + Reserved148_IRQn = 132, /**< Reserved interrupt */ + TMR1_IRQn = 133 /**< TMR1 interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M7 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ +#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm7.h" /* Core Peripheral Access Layer */ +#include "system_MIMXRT1015.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U, /**< FlexIO1 Request4 and Request5 */ + kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ + kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ + kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ + kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ + kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ + kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ + kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ + kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ + kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ + kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FLEXSPI Receive */ + kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FLEXSPI Transmit */ + kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR Request 0 */ + kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR Request 1 */ + kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ + kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ + kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ + kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ + kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ + kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ + kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ + kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U, /**< FlexIO1 Request6 and Request7 */ + kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ + kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ + kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ + kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ + kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ + kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ + kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ + kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR Request 2 */ + kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR Request 3 */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 = 11U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 = 12U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 = 13U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_3 = 14U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 = 15U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 = 16U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 = 17U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_3 = 18U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI_IPP_IND_SCK_FA_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 40U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 44U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER1_TMR3_INPUT_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 77U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 79U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 = 80U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 = 81U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 = 82U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 86U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 88U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 92U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 94U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_14 = 105U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_15 = 106U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_16 = 107U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_17 = 108U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_10 = 109U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_12 = 110U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_13 = 111U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_18 = 112U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_19 = 113U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +typedef enum _xbar_input_signal +{ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA_IN0 input. */ + kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA_IN1 input. */ + kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA_IN2 input is reserved. */ + kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA_IN3 input is reserved. */ + kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA_IN4 input. */ + kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA_IN5 input. */ + kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA_IN6 input. */ + kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA_IN7 input. */ + kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA_IN8 input. */ + kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA_IN9 input. */ + kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA_IN10 input. */ + kXBARA1_InputRESERVED11 = 11|0x100U, /**< XBARA_IN11 input is reserved. */ + kXBARA1_InputRESERVED12 = 12|0x100U, /**< XBARA_IN12 input is reserved. */ + kXBARA1_InputRESERVED13 = 13|0x100U, /**< XBARA_IN13 input is reserved. */ + kXBARA1_InputRESERVED14 = 14|0x100U, /**< XBARA_IN14 input is reserved. */ + kXBARA1_InputRESERVED15 = 15|0x100U, /**< XBARA_IN15 input is reserved. */ + kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA_IN16 input. */ + kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA_IN17 input. */ + kXBARA1_InputRESERVED18 = 18|0x100U, /**< XBARA_IN18 input is reserved. */ + kXBARA1_InputRESERVED19 = 19|0x100U, /**< XBARA_IN19 input is reserved. */ + kXBARA1_InputRESERVED20 = 20|0x100U, /**< XBARA_IN20 input is reserved. */ + kXBARA1_InputRESERVED21 = 21|0x100U, /**< XBARA_IN21 input is reserved. */ + kXBARA1_InputRESERVED22 = 22|0x100U, /**< XBARA_IN22 input is reserved. */ + kXBARA1_InputRESERVED23 = 23|0x100U, /**< XBARA_IN23 input is reserved. */ + kXBARA1_InputRESERVED24 = 24|0x100U, /**< XBARA_IN24 input is reserved. */ + kXBARA1_InputRESERVED25 = 25|0x100U, /**< XBARA_IN25 input is reserved. */ + kXBARA1_InputRESERVED26 = 26|0x100U, /**< XBARA_IN26 input is reserved. */ + kXBARA1_InputRESERVED27 = 27|0x100U, /**< XBARA_IN27 input is reserved. */ + kXBARA1_InputRESERVED28 = 28|0x100U, /**< XBARA_IN28 input is reserved. */ + kXBARA1_InputRESERVED29 = 29|0x100U, /**< XBARA_IN29 input is reserved. */ + kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA_IN30 input is reserved. */ + kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA_IN31 input is reserved. */ + kXBARA1_InputQtimer1Tmr0 = 32|0x100U, /**< QTIMER1_TMR0 output assigned to XBARA_IN32 input. */ + kXBARA1_InputQtimer1Tmr1 = 33|0x100U, /**< QTIMER1_TMR1 output assigned to XBARA_IN33 input. */ + kXBARA1_InputQtimer1Tmr2 = 34|0x100U, /**< QTIMER1_TMR2 output assigned to XBARA_IN34 input. */ + kXBARA1_InputQtimer1Tmr3 = 35|0x100U, /**< QTIMER1_TMR3 output assigned to XBARA_IN35 input. */ + kXBARA1_InputRESERVED36 = 36|0x100U, /**< XBARA_IN36 input is reserved. */ + kXBARA1_InputRESERVED37 = 37|0x100U, /**< XBARA_IN37 input is reserved. */ + kXBARA1_InputRESERVED38 = 38|0x100U, /**< XBARA_IN38 input is reserved. */ + kXBARA1_InputRESERVED39 = 39|0x100U, /**< XBARA_IN39 input is reserved. */ + kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN40 input. */ + kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN41 input. */ + kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN42 input. */ + kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN43 input. */ + kXBARA1_InputRESERVED44 = 44|0x100U, /**< XBARA_IN44 input is reserved. */ + kXBARA1_InputRESERVED45 = 45|0x100U, /**< XBARA_IN45 input is reserved. */ + kXBARA1_InputRESERVED46 = 46|0x100U, /**< XBARA_IN46 input is reserved. */ + kXBARA1_InputRESERVED47 = 47|0x100U, /**< XBARA_IN47 input is reserved. */ + kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA_IN48 input is reserved. */ + kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA_IN49 input is reserved. */ + kXBARA1_InputRESERVED50 = 50|0x100U, /**< XBARA_IN50 input is reserved. */ + kXBARA1_InputRESERVED51 = 51|0x100U, /**< XBARA_IN51 input is reserved. */ + kXBARA1_InputRESERVED52 = 52|0x100U, /**< XBARA_IN52 input is reserved. */ + kXBARA1_InputRESERVED53 = 53|0x100U, /**< XBARA_IN53 input is reserved. */ + kXBARA1_InputRESERVED54 = 54|0x100U, /**< XBARA_IN54 input is reserved. */ + kXBARA1_InputRESERVED55 = 55|0x100U, /**< XBARA_IN55 input is reserved. */ + kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA_IN56 input. */ + kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA_IN57 input. */ + kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA_IN58 input. */ + kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA_IN59 input. */ + kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA_IN60 input. */ + kXBARA1_InputRESERVED61 = 61|0x100U, /**< XBARA_IN61 input is reserved. */ + kXBARA1_InputRESERVED62 = 62|0x100U, /**< XBARA_IN62 input is reserved. */ + kXBARA1_InputRESERVED63 = 63|0x100U, /**< XBARA_IN63 input is reserved. */ + kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA_IN64 input. */ + kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA_IN65 input. */ + kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA_IN66 input. */ + kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA_IN67 input. */ + kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA_IN68 input. */ + kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA_IN69 input. */ + kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA_IN70 input. */ + kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA_IN71 input. */ + kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA_IN72 input. */ + kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA_IN73 input. */ + kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA_IN74 input. */ + kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA_IN75 input. */ + kXBARA1_InputRESERVED76 = 76|0x100U, /**< XBARA_IN76 input is reserved. */ + kXBARA1_InputRESERVED77 = 77|0x100U, /**< XBARA_IN77 input is reserved. */ + kXBARA1_InputRESERVED78 = 78|0x100U, /**< XBARA_IN78 input is reserved. */ + kXBARA1_InputRESERVED79 = 79|0x100U, /**< XBARA_IN79 input is reserved. */ + kXBARA1_InputAdcEtc0Coco0 = 80|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA_IN80 input. */ + kXBARA1_InputAdcEtc0Coco1 = 81|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA_IN81 input. */ + kXBARA1_InputAdcEtc0Coco2 = 82|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA_IN82 input. */ + kXBARA1_InputAdcEtc0Coco3 = 83|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA_IN83 input. */ + kXBARA1_InputAdcEtc1Coco0 = 84|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA_IN84 input. */ + kXBARA1_InputAdcEtc1Coco1 = 85|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA_IN85 input. */ + kXBARA1_InputAdcEtc1Coco2 = 86|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA_IN86 input. */ + kXBARA1_InputAdcEtc1Coco3 = 87|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA_IN87 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB_IN0 input. */ + kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB_IN1 input. */ + kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB_IN2 input is reserved. */ + kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB_IN3 input is reserved. */ + kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB_IN4 input is reserved. */ + kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB_IN5 input is reserved. */ + kXBARB2_InputRESERVED6 = 6|0x200U, /**< XBARB_IN6 input is reserved. */ + kXBARB2_InputRESERVED7 = 7|0x200U, /**< XBARB_IN7 input is reserved. */ + kXBARB2_InputRESERVED8 = 8|0x200U, /**< XBARB_IN8 input is reserved. */ + kXBARB2_InputRESERVED9 = 9|0x200U, /**< XBARB_IN9 input is reserved. */ + kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB_IN10 input is reserved. */ + kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB_IN11 input is reserved. */ + kXBARB2_InputQtimer1Tmr0 = 12|0x200U, /**< QTIMER1_TMR0 output assigned to XBARB_IN12 input. */ + kXBARB2_InputQtimer1Tmr1 = 13|0x200U, /**< QTIMER1_TMR1 output assigned to XBARB_IN13 input. */ + kXBARB2_InputQtimer1Tmr2 = 14|0x200U, /**< QTIMER1_TMR2 output assigned to XBARB_IN14 input. */ + kXBARB2_InputQtimer1Tmr3 = 15|0x200U, /**< QTIMER1_TMR3 output assigned to XBARB_IN15 input. */ + kXBARB2_InputRESERVED16 = 16|0x200U, /**< XBARB_IN16 input is reserved. */ + kXBARB2_InputRESERVED17 = 17|0x200U, /**< XBARB_IN17 input is reserved. */ + kXBARB2_InputRESERVED18 = 18|0x200U, /**< XBARB_IN18 input is reserved. */ + kXBARB2_InputRESERVED19 = 19|0x200U, /**< XBARB_IN19 input is reserved. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN20 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN21 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN22 input. */ + kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN23 input. */ + kXBARB2_InputRESERVED24 = 24|0x200U, /**< XBARB_IN24 input is reserved. */ + kXBARB2_InputRESERVED25 = 25|0x200U, /**< XBARB_IN25 input is reserved. */ + kXBARB2_InputRESERVED26 = 26|0x200U, /**< XBARB_IN26 input is reserved. */ + kXBARB2_InputRESERVED27 = 27|0x200U, /**< XBARB_IN27 input is reserved. */ + kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB_IN28 input is reserved. */ + kXBARB2_InputRESERVED29 = 29|0x200U, /**< XBARB_IN29 input is reserved. */ + kXBARB2_InputRESERVED30 = 30|0x200U, /**< XBARB_IN30 input is reserved. */ + kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB_IN31 input is reserved. */ + kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB_IN32 input is reserved. */ + kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB_IN33 input is reserved. */ + kXBARB2_InputRESERVED34 = 34|0x200U, /**< XBARB_IN34 input is reserved. */ + kXBARB2_InputRESERVED35 = 35|0x200U, /**< XBARB_IN35 input is reserved. */ + kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB_IN36 input. */ + kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB_IN37 input. */ + kXBARB2_InputAdcEtc0Coco0 = 38|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB_IN38 input. */ + kXBARB2_InputAdcEtc0Coco1 = 39|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB_IN39 input. */ + kXBARB2_InputAdcEtc0Coco2 = 40|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB_IN40 input. */ + kXBARB2_InputAdcEtc0Coco3 = 41|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB_IN41 input. */ + kXBARB2_InputAdcEtc1Coco0 = 42|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB_IN42 input. */ + kXBARB2_InputAdcEtc1Coco1 = 43|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB_IN43 input. */ + kXBARB2_InputAdcEtc1Coco2 = 44|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB_IN44 input. */ + kXBARB2_InputAdcEtc1Coco3 = 45|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB_IN45 input. */ + kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB_IN46 input. */ + kXBARB2_InputRESERVED47 = 47|0x200U, /**< XBARB_IN47 input is reserved. */ + kXBARB2_InputRESERVED48 = 48|0x200U, /**< XBARB_IN48 input is reserved. */ + kXBARB2_InputRESERVED49 = 49|0x200U, /**< XBARB_IN49 input is reserved. */ + kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB_IN50 input. */ + kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB_IN51 input. */ + kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB_IN52 input. */ + kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB_IN53 input. */ + kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB_IN54 input. */ + kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB_IN55 input. */ + kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB_IN56 input. */ + kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB_IN57 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBARA1_OutputRESERVED0 = 0|0x100U, /**< XBARA_OUT0 output is reserved. */ + kXBARA1_OutputRESERVED1 = 1|0x100U, /**< XBARA_OUT1 output is reserved. */ + kXBARA1_OutputRESERVED2 = 2|0x100U, /**< XBARA_OUT2 output is reserved. */ + kXBARA1_OutputRESERVED3 = 3|0x100U, /**< XBARA_OUT3 output is reserved. */ + kXBARA1_OutputRESERVED4 = 4|0x100U, /**< XBARA_OUT4 output is reserved. */ + kXBARA1_OutputRESERVED5 = 5|0x100U, /**< XBARA_OUT5 output is reserved. */ + kXBARA1_OutputRESERVED6 = 6|0x100U, /**< XBARA_OUT6 output is reserved. */ + kXBARA1_OutputRESERVED7 = 7|0x100U, /**< XBARA_OUT7 output is reserved. */ + kXBARA1_OutputRESERVED8 = 8|0x100U, /**< XBARA_OUT8 output is reserved. */ + kXBARA1_OutputRESERVED9 = 9|0x100U, /**< XBARA_OUT9 output is reserved. */ + kXBARA1_OutputRESERVED10 = 10|0x100U, /**< XBARA_OUT10 output is reserved. */ + kXBARA1_OutputRESERVED11 = 11|0x100U, /**< XBARA_OUT11 output is reserved. */ + kXBARA1_OutputRESERVED12 = 12|0x100U, /**< XBARA_OUT12 output is reserved. */ + kXBARA1_OutputRESERVED13 = 13|0x100U, /**< XBARA_OUT13 output is reserved. */ + kXBARA1_OutputRESERVED14 = 14|0x100U, /**< XBARA_OUT14 output is reserved. */ + kXBARA1_OutputRESERVED15 = 15|0x100U, /**< XBARA_OUT15 output is reserved. */ + kXBARA1_OutputRESERVED16 = 16|0x100U, /**< XBARA_OUT16 output is reserved. */ + kXBARA1_OutputRESERVED17 = 17|0x100U, /**< XBARA_OUT17 output is reserved. */ + kXBARA1_OutputRESERVED18 = 18|0x100U, /**< XBARA_OUT18 output is reserved. */ + kXBARA1_OutputRESERVED19 = 19|0x100U, /**< XBARA_OUT19 output is reserved. */ + kXBARA1_OutputRESERVED20 = 20|0x100U, /**< XBARA_OUT20 output is reserved. */ + kXBARA1_OutputRESERVED21 = 21|0x100U, /**< XBARA_OUT21 output is reserved. */ + kXBARA1_OutputRESERVED22 = 22|0x100U, /**< XBARA_OUT22 output is reserved. */ + kXBARA1_OutputRESERVED23 = 23|0x100U, /**< XBARA_OUT23 output is reserved. */ + kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA_OUT24 output is reserved. */ + kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA_OUT25 output is reserved. */ + kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA_OUT26 output assigned to FLEXPWM1_EXTA0 */ + kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA_OUT27 output assigned to FLEXPWM1_EXTA1 */ + kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA_OUT28 output assigned to FLEXPWM1_EXTA2 */ + kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA_OUT29 output assigned to FLEXPWM1_EXTA3 */ + kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA_OUT34 output assigned to FLEXPWM1_EXT_CLK */ + kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA_OUT35 output assigned to FLEXPWM1_FAULT0 */ + kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA_OUT36 output assigned to FLEXPWM1_FAULT1 */ + kXBARA1_OutputFlexpwm1Fault2 = 37|0x100U, /**< XBARA_OUT37 output assigned to FLEXPWM1_FAULT2 */ + kXBARA1_OutputFlexpwm1Fault3 = 38|0x100U, /**< XBARA_OUT38 output assigned to FLEXPWM1_FAULT3 */ + kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ + kXBARA1_OutputRESERVED40 = 40|0x100U, /**< XBARA_OUT40 output is reserved. */ + kXBARA1_OutputRESERVED41 = 41|0x100U, /**< XBARA_OUT41 output is reserved. */ + kXBARA1_OutputRESERVED42 = 42|0x100U, /**< XBARA_OUT42 output is reserved. */ + kXBARA1_OutputRESERVED43 = 43|0x100U, /**< XBARA_OUT43 output is reserved. */ + kXBARA1_OutputRESERVED44 = 44|0x100U, /**< XBARA_OUT44 output is reserved. */ + kXBARA1_OutputRESERVED45 = 45|0x100U, /**< XBARA_OUT45 output is reserved. */ + kXBARA1_OutputRESERVED46 = 46|0x100U, /**< XBARA_OUT46 output is reserved. */ + kXBARA1_OutputRESERVED47 = 47|0x100U, /**< XBARA_OUT47 output is reserved. */ + kXBARA1_OutputRESERVED48 = 48|0x100U, /**< XBARA_OUT48 output is reserved. */ + kXBARA1_OutputRESERVED49 = 49|0x100U, /**< XBARA_OUT49 output is reserved. */ + kXBARA1_OutputRESERVED50 = 50|0x100U, /**< XBARA_OUT50 output is reserved. */ + kXBARA1_OutputRESERVED51 = 51|0x100U, /**< XBARA_OUT51 output is reserved. */ + kXBARA1_OutputRESERVED52 = 52|0x100U, /**< XBARA_OUT52 output is reserved. */ + kXBARA1_OutputRESERVED53 = 53|0x100U, /**< XBARA_OUT53 output is reserved. */ + kXBARA1_OutputRESERVED54 = 54|0x100U, /**< XBARA_OUT54 output is reserved. */ + kXBARA1_OutputRESERVED55 = 55|0x100U, /**< XBARA_OUT55 output is reserved. */ + kXBARA1_OutputRESERVED56 = 56|0x100U, /**< XBARA_OUT56 output is reserved. */ + kXBARA1_OutputRESERVED57 = 57|0x100U, /**< XBARA_OUT57 output is reserved. */ + kXBARA1_OutputRESERVED58 = 58|0x100U, /**< XBARA_OUT58 output is reserved. */ + kXBARA1_OutputRESERVED59 = 59|0x100U, /**< XBARA_OUT59 output is reserved. */ + kXBARA1_OutputRESERVED60 = 60|0x100U, /**< XBARA_OUT60 output is reserved. */ + kXBARA1_OutputRESERVED61 = 61|0x100U, /**< XBARA_OUT61 output is reserved. */ + kXBARA1_OutputRESERVED62 = 62|0x100U, /**< XBARA_OUT62 output is reserved. */ + kXBARA1_OutputRESERVED63 = 63|0x100U, /**< XBARA_OUT63 output is reserved. */ + kXBARA1_OutputRESERVED64 = 64|0x100U, /**< XBARA_OUT64 output is reserved. */ + kXBARA1_OutputRESERVED65 = 65|0x100U, /**< XBARA_OUT65 output is reserved. */ + kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA_OUT66 output assigned to ENC1_PHASE_A_INPUT */ + kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA_OUT67 output assigned to ENC1_PHASE_B_INPUT */ + kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA_OUT68 output assigned to ENC1_INDEX */ + kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA_OUT69 output assigned to ENC1_HOME */ + kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA_OUT70 output assigned to ENC1_TRIGGER */ + kXBARA1_OutputRESERVED71 = 71|0x100U, /**< XBARA_OUT71 output is reserved. */ + kXBARA1_OutputRESERVED72 = 72|0x100U, /**< XBARA_OUT72 output is reserved. */ + kXBARA1_OutputRESERVED73 = 73|0x100U, /**< XBARA_OUT73 output is reserved. */ + kXBARA1_OutputRESERVED74 = 74|0x100U, /**< XBARA_OUT74 output is reserved. */ + kXBARA1_OutputRESERVED75 = 75|0x100U, /**< XBARA_OUT75 output is reserved. */ + kXBARA1_OutputRESERVED76 = 76|0x100U, /**< XBARA_OUT76 output is reserved. */ + kXBARA1_OutputRESERVED77 = 77|0x100U, /**< XBARA_OUT77 output is reserved. */ + kXBARA1_OutputRESERVED78 = 78|0x100U, /**< XBARA_OUT78 output is reserved. */ + kXBARA1_OutputRESERVED79 = 79|0x100U, /**< XBARA_OUT79 output is reserved. */ + kXBARA1_OutputRESERVED80 = 80|0x100U, /**< XBARA_OUT80 output is reserved. */ + kXBARA1_OutputRESERVED81 = 81|0x100U, /**< XBARA_OUT81 output is reserved. */ + kXBARA1_OutputRESERVED82 = 82|0x100U, /**< XBARA_OUT82 output is reserved. */ + kXBARA1_OutputRESERVED83 = 83|0x100U, /**< XBARA_OUT83 output is reserved. */ + kXBARA1_OutputRESERVED84 = 84|0x100U, /**< XBARA_OUT84 output is reserved. */ + kXBARA1_OutputRESERVED85 = 85|0x100U, /**< XBARA_OUT85 output is reserved. */ + kXBARA1_OutputQtimer1Tmr0 = 86|0x100U, /**< XBARA_OUT86 output assigned to QTIMER1_TMR0 */ + kXBARA1_OutputQtimer1Tmr1 = 87|0x100U, /**< XBARA_OUT87 output assigned to QTIMER1_TMR1 */ + kXBARA1_OutputQtimer1Tmr2 = 88|0x100U, /**< XBARA_OUT88 output assigned to QTIMER1_TMR2 */ + kXBARA1_OutputQtimer1Tmr3 = 89|0x100U, /**< XBARA_OUT89 output assigned to QTIMER1_TMR3 */ + kXBARA1_OutputRESERVED90 = 90|0x100U, /**< XBARA_OUT90 output is reserved. */ + kXBARA1_OutputRESERVED91 = 91|0x100U, /**< XBARA_OUT91 output is reserved. */ + kXBARA1_OutputRESERVED92 = 92|0x100U, /**< XBARA_OUT92 output is reserved. */ + kXBARA1_OutputRESERVED93 = 93|0x100U, /**< XBARA_OUT93 output is reserved. */ + kXBARA1_OutputRESERVED94 = 94|0x100U, /**< XBARA_OUT94 output is reserved. */ + kXBARA1_OutputRESERVED95 = 95|0x100U, /**< XBARA_OUT95 output is reserved. */ + kXBARA1_OutputRESERVED96 = 96|0x100U, /**< XBARA_OUT96 output is reserved. */ + kXBARA1_OutputRESERVED97 = 97|0x100U, /**< XBARA_OUT97 output is reserved. */ + kXBARA1_OutputRESERVED98 = 98|0x100U, /**< XBARA_OUT98 output is reserved. */ + kXBARA1_OutputRESERVED99 = 99|0x100U, /**< XBARA_OUT99 output is reserved. */ + kXBARA1_OutputRESERVED100 = 100|0x100U, /**< XBARA_OUT100 output is reserved. */ + kXBARA1_OutputRESERVED101 = 101|0x100U, /**< XBARA_OUT101 output is reserved. */ + kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA_OUT102 output assigned to EWM_EWM_IN */ + kXBARA1_OutputAdcEtcTrig00 = 103|0x100U, /**< XBARA_OUT103 output assigned to ADC_ETC_TRIG00 */ + kXBARA1_OutputAdcEtcTrig01 = 104|0x100U, /**< XBARA_OUT104 output assigned to ADC_ETC_TRIG01 */ + kXBARA1_OutputAdcEtcTrig02 = 105|0x100U, /**< XBARA_OUT105 output assigned to ADC_ETC_TRIG02 */ + kXBARA1_OutputAdcEtcTrig03 = 106|0x100U, /**< XBARA_OUT106 output assigned to ADC_ETC_TRIG03 */ + kXBARA1_OutputAdcEtcTrig10 = 107|0x100U, /**< XBARA_OUT107 output assigned to ADC_ETC_TRIG10 */ + kXBARA1_OutputAdcEtcTrig11 = 108|0x100U, /**< XBARA_OUT108 output assigned to ADC_ETC_TRIG11 */ + kXBARA1_OutputAdcEtcTrig12 = 109|0x100U, /**< XBARA_OUT109 output assigned to ADC_ETC_TRIG12 */ + kXBARA1_OutputAdcEtcTrig13 = 110|0x100U, /**< XBARA_OUT110 output assigned to ADC_ETC_TRIG13 */ + kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA_OUT111 output assigned to LPI2C1_TRG_INPUT */ + kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA_OUT112 output assigned to LPI2C2_TRG_INPUT */ + kXBARA1_OutputRESERVED113 = 113|0x100U, /**< XBARA_OUT113 output is reserved. */ + kXBARA1_OutputRESERVED114 = 114|0x100U, /**< XBARA_OUT114 output is reserved. */ + kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA_OUT115 output assigned to LPSPI1_TRG_INPUT */ + kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA_OUT116 output assigned to LPSPI2_TRG_INPUT */ + kXBARA1_OutputRESERVED117 = 117|0x100U, /**< XBARA_OUT117 output is reserved. */ + kXBARA1_OutputRESERVED118 = 118|0x100U, /**< XBARA_OUT118 output is reserved. */ + kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA_OUT119 output assigned to LPUART1_TRG_INPUT */ + kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA_OUT120 output assigned to LPUART2_TRG_INPUT */ + kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA_OUT121 output assigned to LPUART3_TRG_INPUT */ + kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA_OUT122 output assigned to LPUART4_TRG_INPUT */ + kXBARA1_OutputRESERVED123 = 123|0x100U, /**< XBARA_OUT123 output is reserved. */ + kXBARA1_OutputRESERVED124 = 124|0x100U, /**< XBARA_OUT124 output is reserved. */ + kXBARA1_OutputRESERVED125 = 125|0x100U, /**< XBARA_OUT125 output is reserved. */ + kXBARA1_OutputRESERVED126 = 126|0x100U, /**< XBARA_OUT126 output is reserved. */ + kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ + kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ + kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA_OUT129 output is reserved. */ + kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA_OUT130 output is reserved. */ + kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA_OUT131 output is reserved. */ + kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB_OUT0 output assigned to AOI1_IN00 */ + kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB_OUT1 output assigned to AOI1_IN01 */ + kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB_OUT2 output assigned to AOI1_IN02 */ + kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB_OUT3 output assigned to AOI1_IN03 */ + kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB_OUT4 output assigned to AOI1_IN04 */ + kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB_OUT5 output assigned to AOI1_IN05 */ + kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB_OUT6 output assigned to AOI1_IN06 */ + kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB_OUT7 output assigned to AOI1_IN07 */ + kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB_OUT8 output assigned to AOI1_IN08 */ + kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB_OUT9 output assigned to AOI1_IN09 */ + kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB_OUT10 output assigned to AOI1_IN10 */ + kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB_OUT11 output assigned to AOI1_IN11 */ + kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB_OUT12 output assigned to AOI1_IN12 */ + kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB_OUT13 output assigned to AOI1_IN13 */ + kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB_OUT14 output assigned to AOI1_IN14 */ + kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB_OUT15 output assigned to AOI1_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ + __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ + __IO uint32_t GC; /**< General control register, offset: 0x48 */ + __IO uint32_t GS; /**< General status register, offset: 0x4C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +/*! @{ */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (8U) + +/*! @name HS - Status register for HW triggers */ +/*! @{ */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ + +/*! @name R - Data result register for HW triggers */ +/*! @{ */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ + +/* The count of ADC_R */ +#define ADC_R_COUNT (8U) + +/*! @name CFG - Configuration register */ +/*! @{ */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ + +/*! @name GC - General control register */ +/*! @{ */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" + * functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" + * functionality based on the values placed in the ADC_CV registers. + */ +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ + +/*! @name GS - General status register */ +/*! @{ */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ + +/*! @name CV - Compare value register */ +/*! @{ */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ + +/*! @name OFS - Offset correction value register */ +/*! @{ */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ + +/*! @name CAL - Calibration value register */ +/*! @{ */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400C4000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer + * @{ + */ + +/** ADC_ETC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ + __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ + __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG3 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG3 Counter Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ + } TRIG[4]; +} ADC_ETC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks + * @{ + */ + +/*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ +#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) +#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) +#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) +#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) +#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) +#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) +#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) +#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) +#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ + +/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ + +/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ + +/*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ + +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG3 Control Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CTRL */ +#define ADC_ETC_TRIGn_CTRL_COUNT (4U) + +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG3 Counter Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_COUNTER */ +#define ADC_ETC_TRIGn_COUNTER_COUNT (4U) + +/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ +#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (4U) + +/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ +#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (4U) + +/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ +#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (4U) + +/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ +#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (4U) + +/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ +#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (4U) + +/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ +#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (4U) + +/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ +#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (4U) + +/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ +#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (4U) + + +/*! + * @} + */ /* end of group ADC_ETC_Register_Masks */ + + +/* ADC_ETC - Peripheral instance base addresses */ +/** Peripheral ADC_ETC base address */ +#define ADC_ETC_BASE (0x403B0000u) +/** Peripheral ADC_ETC base pointer */ +#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) +/** Array initializer of ADC_ETC peripheral base addresses */ +#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } +/** Array initializer of ADC_ETC peripheral base pointers */ +#define ADC_ETC_BASE_PTRS { ADC_ETC } +/** Interrupt vectors for the ADC_ETC peripheral type */ +#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } +#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } + +/*! + * @} + */ /* end of group ADC_ETC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +/*! @{ */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x4007C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x4017C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x4027C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x4037C000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI base address */ +#define AOI_BASE (0x403B4000u) +/** Peripheral AOI base pointer */ +#define AOI ((AOI_Type *)AOI_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BEE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer + * @{ + */ + +/** BEE - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */ + __IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */ + __IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */ + __IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */ + __IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */ + __IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */ + __IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */ + __IO uint32_t STATUS; /**< , offset: 0x1C */ + __O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */ + __O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */ + __O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */ + __O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */ + __O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */ + __O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */ + __O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */ + __O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */ + __IO uint32_t REGION1_TOP; /**< , offset: 0x40 */ + __IO uint32_t REGION1_BOT; /**< , offset: 0x44 */ +} BEE_Type; + +/* ---------------------------------------------------------------------------- + -- BEE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Register_Masks BEE Register Masks + * @{ + */ + +/*! @name CTRL - BEE Control Register */ +/*! @{ */ +#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) +#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ +#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) +#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) +#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) +#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) +#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) +#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) +#define BEE_CTRL_KEY_VALID_MASK (0x10U) +#define BEE_CTRL_KEY_VALID_SHIFT (4U) +#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) +#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) +#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ +#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) +#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) +#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) +#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) +#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, + * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to + * Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ +#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) +#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) +#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) +#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) +#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) +#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) +#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) +#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) +#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) +#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) +#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) +#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) +#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) +#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) +#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) +#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) +#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) +#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) +#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) +#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) +#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) +#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) +#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET0 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET1 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ + +/*! @name AES_KEY0_W0 - */ +/*! @{ */ +#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) +#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ + +/*! @name AES_KEY0_W1 - */ +/*! @{ */ +#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) +#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ + +/*! @name AES_KEY0_W2 - */ +/*! @{ */ +#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) +#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ + +/*! @name AES_KEY0_W3 - */ +/*! @{ */ +#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) +#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ + +/*! @name STATUS - */ +/*! @{ */ +#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) +#define BEE_STATUS_IRQ_VEC_SHIFT (0U) +#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) +#define BEE_STATUS_BEE_IDLE_MASK (0x100U) +#define BEE_STATUS_BEE_IDLE_SHIFT (8U) +#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) +#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) +#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) +#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) +#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) +#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) +#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) +#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) +#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ + +/*! @name REGION1_TOP - */ +/*! @{ */ +#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) +#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) +#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ + +/*! @name REGION1_BOT - */ +/*! @{ */ +#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) +#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) +#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BEE_Register_Masks */ + + +/* BEE - Peripheral instance base addresses */ +/** Peripheral BEE base address */ +#define BEE_BASE (0x403EC000u) +/** Peripheral BEE base pointer */ +#define BEE ((BEE_Type *)BEE_BASE) +/** Array initializer of BEE peripheral base addresses */ +#define BEE_BASE_ADDRS { BEE_BASE } +/** Array initializer of BEE peripheral base pointers */ +#define BEE_BASE_PTRS { BEE } + +/*! + * @} + */ /* end of group BEE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_3[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_4[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +/*! @{ */ +#define CCM_CCR_OSCNT_MASK (0xFFU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ + +/*! @name CSR - CCM Status Register */ +/*! @{ */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_CAMP2_READY_MASK (0x8U) +#define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ +#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ + +/*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ + +/*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ +#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) +#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ +#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) +#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ +#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ +#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL3 PFD3 + * 0b10..derive clock from PLL2 PFD3 + * 0b11..derive clock from divided PLL6 + */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +/*! @} */ + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF - Divider for perclk podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..Reserved + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..Reserved + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..Reserved + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ +#define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..Reserved + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF - Divider for uart clock podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ + +/*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U) +/*! FLEXIO1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U) +/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK) +/*! @} */ + +/*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..Reserved + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +/*! @{ */ +#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is + * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used + * to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ +#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ +#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the + * previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the + * previous value of select, and after the handshake periph_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ + +/*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain + * asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be + * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will + * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will + * continue with the exit from the STOP mode process. + */ +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) +#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) +#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ + +/*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ +#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..pll3_sw_clk (divided by 2) + * 0b0001..PLL2 (divided by 2) + * 0b0010..ENET PLL (divided by 2) + * 0b0011..Reserved + * 0b0101..Reserved + * 0b0110..Reserved + * 0b1010..Reserved + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..Reserved + * 0b1111..pll4_main_clk + */ +#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00101..Reserved + * 0b00110..lpi2c_clk_root + * 0b01110..osc_clk + * 0b10000..lpspi_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root + * 0b10110..trace_clk_root + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ + +/*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low + * Power Modes (WAIT and STOP without power gating) + */ +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ + +/*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) +#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) +#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x400FC000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_6[76]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + */ +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U) +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U) +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x400D8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer + * @{ + */ + +/** CSU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[384]; + __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ + uint8_t RESERVED_2[316]; + __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ +} CSU_Type; + +/* ---------------------------------------------------------------------------- + -- CSU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Register_Masks CSU Register Masks + * @{ + */ + +/*! @name CSL - Config security level register */ +/*! @{ */ +#define CSU_CSL_SUR_S2_MASK (0x1U) +#define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ +#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) +#define CSU_CSL_SSR_S2_MASK (0x2U) +#define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) +#define CSU_CSL_NUR_S2_MASK (0x4U) +#define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ +#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) +#define CSU_CSL_NSR_S2_MASK (0x8U) +#define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) +#define CSU_CSL_SUW_S2_MASK (0x10U) +#define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ +#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) +#define CSU_CSL_SSW_S2_MASK (0x20U) +#define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) +#define CSU_CSL_NUW_S2_MASK (0x40U) +#define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ +#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) +#define CSU_CSL_NSW_S2_MASK (0x80U) +#define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) +#define CSU_CSL_LOCK_S2_MASK (0x100U) +#define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ +#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) +#define CSU_CSL_SUR_S1_MASK (0x10000U) +#define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ +#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) +#define CSU_CSL_SSR_S1_MASK (0x20000U) +#define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) +#define CSU_CSL_NUR_S1_MASK (0x40000U) +#define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ +#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) +#define CSU_CSL_NSR_S1_MASK (0x80000U) +#define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) +#define CSU_CSL_SUW_S1_MASK (0x100000U) +#define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ +#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) +#define CSU_CSL_SSW_S1_MASK (0x200000U) +#define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ +#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) +#define CSU_CSL_NUW_S1_MASK (0x400000U) +#define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ +#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) +#define CSU_CSL_NSW_S1_MASK (0x800000U) +#define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ +#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) +#define CSU_CSL_LOCK_S1_MASK (0x1000000U) +#define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ +#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ + +/* The count of CSU_CSL */ +#define CSU_CSL_COUNT (32U) + +/*! @name HP0 - HP0 register */ +/*! @{ */ +#define CSU_HP0_HP_DMA_MASK (0x4U) +#define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) +#define CSU_HP0_L_DMA_MASK (0x8U) +#define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) +#define CSU_HP0_HP_LCDIF_MASK (0x10U) +#define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) +#define CSU_HP0_L_LCDIF_MASK (0x20U) +#define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) +#define CSU_HP0_HP_CSI_MASK (0x40U) +#define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) +#define CSU_HP0_L_CSI_MASK (0x80U) +#define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) +#define CSU_HP0_HP_PXP_MASK (0x100U) +#define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) +#define CSU_HP0_L_PXP_MASK (0x200U) +#define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) +#define CSU_HP0_HP_DCP_MASK (0x400U) +#define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) +#define CSU_HP0_L_DCP_MASK (0x800U) +#define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ +#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) +#define CSU_HP0_HP_ENET_MASK (0x4000U) +#define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) +#define CSU_HP0_L_ENET_MASK (0x8000U) +#define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) +#define CSU_HP0_HP_USDHC1_MASK (0x10000U) +#define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) +#define CSU_HP0_L_USDHC1_MASK (0x20000U) +#define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) +#define CSU_HP0_HP_USDHC2_MASK (0x40000U) +#define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) +#define CSU_HP0_L_USDHC2_MASK (0x80000U) +#define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) +#define CSU_HP0_HP_TPSMP_MASK (0x100000U) +#define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) +#define CSU_HP0_L_TPSMP_MASK (0x200000U) +#define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) +#define CSU_HP0_HP_USB_MASK (0x400000U) +#define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) +#define CSU_HP0_L_USB_MASK (0x800000U) +#define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ + +/*! @name SA - Secure access register */ +/*! @{ */ +#define CSU_SA_NSA_DMA_MASK (0x4U) +#define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) +#define CSU_SA_L_DMA_MASK (0x8U) +#define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) +#define CSU_SA_NSA_LCDIF_MASK (0x10U) +#define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) +#define CSU_SA_L_LCDIF_MASK (0x20U) +#define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) +#define CSU_SA_NSA_CSI_MASK (0x40U) +#define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) +#define CSU_SA_L_CSI_MASK (0x80U) +#define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) +#define CSU_SA_NSA_PXP_MASK (0x100U) +#define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) +#define CSU_SA_L_PXP_MASK (0x200U) +#define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) +#define CSU_SA_NSA_DCP_MASK (0x400U) +#define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) +#define CSU_SA_L_DCP_MASK (0x800U) +#define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) +#define CSU_SA_NSA_ENET_MASK (0x4000U) +#define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) +#define CSU_SA_L_ENET_MASK (0x8000U) +#define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) +#define CSU_SA_NSA_USDHC1_MASK (0x10000U) +#define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) +#define CSU_SA_L_USDHC1_MASK (0x20000U) +#define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) +#define CSU_SA_NSA_USDHC2_MASK (0x40000U) +#define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) +#define CSU_SA_L_USDHC2_MASK (0x80000U) +#define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) +#define CSU_SA_NSA_TPSMP_MASK (0x100000U) +#define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) +#define CSU_SA_L_TPSMP_MASK (0x200000U) +#define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) +#define CSU_SA_NSA_USB_MASK (0x400000U) +#define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) +#define CSU_SA_L_USB_MASK (0x800000U) +#define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ + +/*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ +#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) +#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) +#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) +#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) +#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) +#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) +#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) +#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) +#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) +#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) +#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) +#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) +#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) +#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) +#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) +#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) +#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) +#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) +#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) +#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) +#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) +#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) +#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) +#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) +#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) +#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) +#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) +#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) +#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) +#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) +#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) +#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) +#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) +#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) +#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) +#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) +#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) +#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) +#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) +#define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSU_Register_Masks */ + + +/* CSU - Peripheral instance base addresses */ +/** Peripheral CSU base address */ +#define CSU_BASE (0x400DC000u) +/** Peripheral CSU base pointer */ +#define CSU ((CSU_Type *)CSU_BASE) +/** Array initializer of CSU peripheral base addresses */ +#define CSU_BASE_ADDRS { CSU_BASE } +/** Array initializer of CSU peripheral base pointers */ +#define CSU_BASE_PTRS { CSU } + +/*! + * @} + */ /* end of group CSU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) +#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) +#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) +#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) +#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) +#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) +#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) +#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) +#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) +#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) +#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) +#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) +#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) +#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) +#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) +#define DCDC_REG1_VBG_TRIM_SHIFT (24U) +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) +#define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U) +#define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U) +#define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK) +#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) +#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) +#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ +#define DCDC_REG3_TRG_MASK (0x1FU) +#define DCDC_REG3_TRG_SHIFT (0U) +#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) +#define DCDC_REG3_TARGET_LP_MASK (0x700U) +#define DCDC_REG3_TARGET_LP_SHIFT (8U) +#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) +#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) +#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40080000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } +/** Interrupt vectors for the DCDC peripheral type */ +#define DCDC_IRQS { DCDC_IRQn } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - DCP status register */ +/*! @{ */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ + +/*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ + +/*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ + +/*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ + +/*! @name KEY - DCP key index */ +/*! @{ */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ + +/*! @name KEYDATA - DCP key data */ +/*! @{ */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ + +/*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ + +/*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ + +/*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ + +/*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ + +/*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ + +/*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ + +/*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ + +/*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ + +/*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ + +/*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ + +/*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ + +/*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ + +/*! @name DBGDATA - DCP debug data register */ +/*! @{ */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ + +/*! @name PAGETABLE - DCP page table register */ +/*! @{ */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ + +/*! @name VERSION - DCP version register */ +/*! @{ */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x402FC000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel Priority Register, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel Priority Register, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel Priority Register, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel Priority Register, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel Priority Register, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel Priority Register, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel Priority Register, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel Priority Register, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel Priority Register, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel Priority Register, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel Priority Register, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel Priority Register, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel Priority Register, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel Priority Register, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel Priority Register, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel Priority Register, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel Priority Register, offset: 0x11F */ + uint8_t RESERVED_7[32]; + __IO uint8_t DCHMID[32]; /**< Channel n Master ID Register, array offset: 0x140, array step: 0x1 */ + uint8_t RESERVED_8[3744]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to + * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated + * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel + * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the + * next minor loop. + */ +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES + * field. The individual enable fields allow the minor loop offset to be applied to the source address, the + * destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and + * force the minor loop to finish. The cancel takes effect after the last write of the current read/write + * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX + * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an + * optional error interrupt. + */ +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The + * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after + * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status Register */ +/*! @{ */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. + * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, + * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel + * priorities within a group are not unique. + */ +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request Register */ +/*! @{ */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request Register */ +/*! @{ */ +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit Register */ +/*! @{ */ +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error Register */ +/*! @{ */ +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request Register */ +/*! @{ */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error Register */ +/*! @{ */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status Register */ +/*! @{ */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI4 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI12 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI20 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI27 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI26 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI25 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI24 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI31 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI30 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI29 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI28 - Channel Priority Register */ +/*! @{ */ +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name DCHMID - Channel n Master ID Register */ +/*! @{ */ +#define DMA_DCHMID_MID_MASK (0xFU) +#define DMA_DCHMID_MID_SHIFT (0U) +#define DMA_DCHMID_MID(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_MID_SHIFT)) & DMA_DCHMID_MID_MASK) +#define DMA_DCHMID_PAL_MASK (0x40U) +#define DMA_DCHMID_PAL_SHIFT (6U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_DCHMID_PAL(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_PAL_SHIFT)) & DMA_DCHMID_PAL_MASK) +#define DMA_DCHMID_EMI_MASK (0x80U) +#define DMA_DCHMID_EMI_SHIFT (7U) +/*! EMI - Enable Master ID replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA_DCHMID_EMI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHMID_EMI_SHIFT)) & DMA_DCHMID_EMI_MASK) +/*! @} */ + +/* The count of DMA_DCHMID */ +#define DMA_DCHMID_COUNT (32U) + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF + * calculation is performed on the original register value. Setting this field provides the ability + * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the + * queue should start at a 0-modulo-size address and the SMOD field should be set to the + * appropriate value for the queue, freezing the desired number of upper address bits. The value + * programmed into this field specifies the number of lower address bits allowed to change. For a + * circular queue application, the SOFF is typically set to the transfer size to implement + * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ +/*! @{ */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer + * to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x400E8000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the + * specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x400EC000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The + * PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If + * CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, + * PHASEB = 1, then count up + */ +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +/** Peripheral ENC1 base address */ +#define ENC1_BASE (0x403C8000u) +/** Peripheral ENC1 base pointer */ +#define ENC1 ((ENC_Type *)ENC1_BASE) +/** Array initializer of ENC peripheral base addresses */ +#define ENC_BASE_ADDRS { 0u, ENC1_BASE } +/** Array initializer of ENC peripheral base pointers */ +#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1 } +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn } +#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn } +#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn } +#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn } +#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service Register */ +/*! @{ */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low Register */ +/*! @{ */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High Register */ +/*! @{ */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x400B4000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_12[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_14[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FlexIO Control Register */ +/*! @{ */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State Register */ +/*! @{ */ +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x401AC000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer + * @{ + */ + +/** FLEXRAM - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ + __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ +} FLEXRAM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks + * @{ + */ + +/*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) +/*! @} */ + +/*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXRAM_Register_Masks */ + + +/* FLEXRAM - Peripheral instance base addresses */ +/** Peripheral FLEXRAM base address */ +#define FLEXRAM_BASE (0x400B0000u) +/** Peripheral FLEXRAM base pointer */ +#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) +/** Array initializer of FLEXRAM peripheral base addresses */ +#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } +/** Array initializer of FLEXRAM peripheral base pointers */ +#define FLEXRAM_BASE_PTRS { FLEXRAM } +/** Interrupt vectors for the FLEXRAM peripheral type */ +#define FLEXRAM_IRQS { FLEXRAM_IRQn } + +/*! + * @} + */ /* end of group FLEXRAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[48]; + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + uint8_t RESERVED_4[4]; + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, + * external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is + * enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned + * automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or + * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP + * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash + * A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, + * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be + * ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). + * In this case, port B flash access is not available. After change the value of this feild, + * MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat + * of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus + * ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is + * granted by arbitrator and will not wait for AHB command finished. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB + * burst required to meet the alignment requirement. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for + * memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for + * memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted + * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be + * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be + * cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI base address */ +#define FLEXSPI_BASE (0x402A8000u) +/** Peripheral FLEXSPI base pointer */ +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI_IRQn } +/* FlexSPI AMBA address. */ +#define FlexSPI_AMBA_BASE (0x60000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI_ASFM_BASE (0x60000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI_ARDF_BASE (0x7FC00000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI_ATDF_BASE (0x7F800000U) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ + __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +/*! @{ */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) +#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain will keep power on even if CPU core is power down. + */ +#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + +/*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ +#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) +#define GPC_IMR5_IMR5_SHIFT (0U) +#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ + +/*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ +#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR5_ISR4_SHIFT (0U) +#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x400F4000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x401B8000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x401BC000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x401C0000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x400C0000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, 0u, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, (GPIO_Type *)0u, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, NotAvail_IRQn, GPIO5_Combined_0_15_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, NotAvail_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x401EC000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x401F0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[16]; + __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_CFR_MASK (0xF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (4U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (4U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_CFR_MASK (0xF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (4U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (4U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x40384000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x40388000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x4038C000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[36]; + __IO uint32_t SW_MUX_CTL_PAD[89]; /**< SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t SW_PAD_CTL_PAD[89]; /**< SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x198, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[114]; /**< ANATOP_USB_OTG_ID_SELECT_INPUT DAISY Register..XBAR1_XBAR_IN_SELECT_INPUT_19 DAISY Register, array offset: 0x2FC, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b001..Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT04 of instance: xbar1 + * 0b010..Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + * 0b011..Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2 + * 0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO16 of instance: flexio1 + * 0b101..Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + * 0b111..Select mux mode: ALT7 mux port: SJC_JTAG_ACT of instance: sjc + */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_EMC_04 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (89U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (89U) + +/*! @name SELECT_INPUT - ANATOP_USB_OTG_ID_SELECT_INPUT DAISY Register..XBAR1_XBAR_IN_SELECT_INPUT_19 DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b00..Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6 + * 0b01..Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0 + * 0b10..Reserved + */ +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (114U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x401F8000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ + __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ + __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select + * 0b00..ccm.spdif0_clk_root + * 0b01..SPDIF_EXT_CLK + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select + * 0b00..ccm.spdif0_clk_root + * 0b01..SPDIF_EXT_CLK + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select + * 0b00..ccm.spdif0_clk_root + * 0b01..SPDIF_EXT_CLK + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT - Global Interrupt + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR - sai1.MCLK signal direction control + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR - sai2.MCLK signal direction control + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR - sai3.MCLK signal direction control + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON - Exclusive monitor response select of illegal command + * 0b0..OKAY response + * 0b1..SLVError response + */ +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN - ARM CM7 platform AHB clock enable + * 0b0..AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible. + * 0b1..AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible. + */ +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ + +/*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING - Enable power saving features on L2 memory + * 0b0..Enters power saving mode only when chip is in SUSPEND mode + * 0b1..Controlled by L2_MEM_DEEPSLEEP bitfield + */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U) +/*! RAM_AUTO_CLK_GATING_EN + * 0b0..disable automatically gate off RAM clock + * 0b1..enable automatically gate off RAM clock + */ +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode) + * 0b1..Force memory into deep sleep mode (OCRAM in power saving mode) + */ +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + * 0b00000000..mclk frequency = 1/1 * hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b00000011..mclk frequency = 1/4 * hmclk frequency + * 0b00000100..mclk frequency = 1/5 * hmclk frequency + * 0b00000101..mclk frequency = 1/6 * hmclk frequency + * 0b00000110..mclk frequency = 1/7 * hmclk frequency + * 0b00000111..mclk frequency = 1/8 * hmclk frequency + * 0b00001000..mclk frequency = 1/9 * hmclk frequency + * 0b00001001..mclk frequency = 1/10 * hmclk frequency + * 0b00001010..mclk frequency = 1/11 * hmclk frequency + * 0b00001011..mclk frequency = 1/12 * hmclk frequency + * 0b00001100..mclk frequency = 1/13 * hmclk frequency + * 0b00001101..mclk frequency = 1/14 * hmclk frequency + * 0b00001110..mclk frequency = 1/15 * hmclk frequency + * 0b00001111..mclk frequency = 1/16 * hmclk frequency + * 0b00010000..mclk frequency = 1/17 * hmclk frequency + * 0b00010001..mclk frequency = 1/18 * hmclk frequency + * 0b00010010..mclk frequency = 1/19 * hmclk frequency + * 0b00010011..mclk frequency = 1/20 * hmclk frequency + * 0b00010100..mclk frequency = 1/21 * hmclk frequency + * 0b00010101..mclk frequency = 1/22 * hmclk frequency + * 0b00010110..mclk frequency = 1/23 * hmclk frequency + * 0b00010111..mclk frequency = 1/24 * hmclk frequency + * 0b00011000..mclk frequency = 1/25 * hmclk frequency + * 0b00011001..mclk frequency = 1/26 * hmclk frequency + * 0b00011010..mclk frequency = 1/27 * hmclk frequency + * 0b00011011..mclk frequency = 1/28 * hmclk frequency + * 0b00011100..mclk frequency = 1/29 * hmclk frequency + * 0b00011101..mclk frequency = 1/30 * hmclk frequency + * 0b00011110..mclk frequency = 1/31 * hmclk frequency + * 0b00011111..mclk frequency = 1/32 * hmclk frequency + * 0b00100000..mclk frequency = 1/33 * hmclk frequency + * 0b00100001..mclk frequency = 1/34 * hmclk frequency + * 0b00100010..mclk frequency = 1/35 * hmclk frequency + * 0b00100011..mclk frequency = 1/36 * hmclk frequency + * 0b00100100..mclk frequency = 1/37 * hmclk frequency + * 0b00100101..mclk frequency = 1/38 * hmclk frequency + * 0b00100110..mclk frequency = 1/39 * hmclk frequency + * 0b00100111..mclk frequency = 1/40 * hmclk frequency + * 0b00101000..mclk frequency = 1/41 * hmclk frequency + * 0b00101001..mclk frequency = 1/42 * hmclk frequency + * 0b00101010..mclk frequency = 1/43 * hmclk frequency + * 0b00101011..mclk frequency = 1/44 * hmclk frequency + * 0b00101100..mclk frequency = 1/45 * hmclk frequency + * 0b00101101..mclk frequency = 1/46 * hmclk frequency + * 0b00101110..mclk frequency = 1/47 * hmclk frequency + * 0b00101111..mclk frequency = 1/48 * hmclk frequency + * 0b00110000..mclk frequency = 1/49 * hmclk frequency + * 0b00110001..mclk frequency = 1/50 * hmclk frequency + * 0b00110010..mclk frequency = 1/51 * hmclk frequency + * 0b00110011..mclk frequency = 1/52 * hmclk frequency + * 0b00110100..mclk frequency = 1/53 * hmclk frequency + * 0b00110101..mclk frequency = 1/54 * hmclk frequency + * 0b00110110..mclk frequency = 1/55 * hmclk frequency + * 0b00110111..mclk frequency = 1/56 * hmclk frequency + * 0b00111000..mclk frequency = 1/57 * hmclk frequency + * 0b00111001..mclk frequency = 1/58 * hmclk frequency + * 0b00111010..mclk frequency = 1/59 * hmclk frequency + * 0b00111011..mclk frequency = 1/60 * hmclk frequency + * 0b00111100..mclk frequency = 1/61 * hmclk frequency + * 0b00111101..mclk frequency = 1/62 * hmclk frequency + * 0b00111110..mclk frequency = 1/63 * hmclk frequency + * 0b00111111..mclk frequency = 1/64 * hmclk frequency + * 0b01000000..mclk frequency = 1/65 * hmclk frequency + * 0b01000001..mclk frequency = 1/66 * hmclk frequency + * 0b01000010..mclk frequency = 1/67 * hmclk frequency + * 0b01000011..mclk frequency = 1/68 * hmclk frequency + * 0b01000100..mclk frequency = 1/69 * hmclk frequency + * 0b01000101..mclk frequency = 1/70 * hmclk frequency + * 0b01000110..mclk frequency = 1/71 * hmclk frequency + * 0b01000111..mclk frequency = 1/72 * hmclk frequency + * 0b01001000..mclk frequency = 1/73 * hmclk frequency + * 0b01001001..mclk frequency = 1/74 * hmclk frequency + * 0b01001010..mclk frequency = 1/75 * hmclk frequency + * 0b01001011..mclk frequency = 1/76 * hmclk frequency + * 0b01001100..mclk frequency = 1/77 * hmclk frequency + * 0b01001101..mclk frequency = 1/78 * hmclk frequency + * 0b01001110..mclk frequency = 1/79 * hmclk frequency + * 0b01001111..mclk frequency = 1/80 * hmclk frequency + * 0b01010000..mclk frequency = 1/81 * hmclk frequency + * 0b01010001..mclk frequency = 1/82 * hmclk frequency + * 0b01010010..mclk frequency = 1/83 * hmclk frequency + * 0b01010011..mclk frequency = 1/84 * hmclk frequency + * 0b01010100..mclk frequency = 1/85 * hmclk frequency + * 0b01010101..mclk frequency = 1/86 * hmclk frequency + * 0b01010110..mclk frequency = 1/87 * hmclk frequency + * 0b01010111..mclk frequency = 1/88 * hmclk frequency + * 0b01011000..mclk frequency = 1/89 * hmclk frequency + * 0b01011001..mclk frequency = 1/90 * hmclk frequency + * 0b01011010..mclk frequency = 1/91 * hmclk frequency + * 0b01011011..mclk frequency = 1/92 * hmclk frequency + * 0b01011100..mclk frequency = 1/93 * hmclk frequency + * 0b01011101..mclk frequency = 1/94 * hmclk frequency + * 0b01011110..mclk frequency = 1/95 * hmclk frequency + * 0b01011111..mclk frequency = 1/96 * hmclk frequency + * 0b01100000..mclk frequency = 1/97 * hmclk frequency + * 0b01100001..mclk frequency = 1/98 * hmclk frequency + * 0b01100010..mclk frequency = 1/99 * hmclk frequency + * 0b01100011..mclk frequency = 1/100 * hmclk frequency + * 0b01100100..mclk frequency = 1/101 * hmclk frequency + * 0b01100101..mclk frequency = 1/102 * hmclk frequency + * 0b01100110..mclk frequency = 1/103 * hmclk frequency + * 0b01100111..mclk frequency = 1/104 * hmclk frequency + * 0b01101000..mclk frequency = 1/105 * hmclk frequency + * 0b01101001..mclk frequency = 1/106 * hmclk frequency + * 0b01101010..mclk frequency = 1/107 * hmclk frequency + * 0b01101011..mclk frequency = 1/108 * hmclk frequency + * 0b01101100..mclk frequency = 1/109 * hmclk frequency + * 0b01101101..mclk frequency = 1/110 * hmclk frequency + * 0b01101110..mclk frequency = 1/111 * hmclk frequency + * 0b01101111..mclk frequency = 1/112 * hmclk frequency + * 0b01110000..mclk frequency = 1/113 * hmclk frequency + * 0b01110001..mclk frequency = 1/114 * hmclk frequency + * 0b01110010..mclk frequency = 1/115 * hmclk frequency + * 0b01110011..mclk frequency = 1/116 * hmclk frequency + * 0b01110100..mclk frequency = 1/117 * hmclk frequency + * 0b01110101..mclk frequency = 1/118 * hmclk frequency + * 0b01110110..mclk frequency = 1/119 * hmclk frequency + * 0b01110111..mclk frequency = 1/120 * hmclk frequency + * 0b01111000..mclk frequency = 1/121 * hmclk frequency + * 0b01111001..mclk frequency = 1/122 * hmclk frequency + * 0b01111010..mclk frequency = 1/123 * hmclk frequency + * 0b01111011..mclk frequency = 1/124 * hmclk frequency + * 0b01111100..mclk frequency = 1/125 * hmclk frequency + * 0b01111101..mclk frequency = 1/126 * hmclk frequency + * 0b01111110..mclk frequency = 1/127 * hmclk frequency + * 0b01111111..mclk frequency = 1/128 * hmclk frequency + * 0b10000000..mclk frequency = 1/129 * hmclk frequency + * 0b10000001..mclk frequency = 1/130 * hmclk frequency + * 0b10000010..mclk frequency = 1/131 * hmclk frequency + * 0b10000011..mclk frequency = 1/132 * hmclk frequency + * 0b10000100..mclk frequency = 1/133 * hmclk frequency + * 0b10000101..mclk frequency = 1/134 * hmclk frequency + * 0b10000110..mclk frequency = 1/135 * hmclk frequency + * 0b10000111..mclk frequency = 1/136 * hmclk frequency + * 0b10001000..mclk frequency = 1/137 * hmclk frequency + * 0b10001001..mclk frequency = 1/138 * hmclk frequency + * 0b10001010..mclk frequency = 1/139 * hmclk frequency + * 0b10001011..mclk frequency = 1/140 * hmclk frequency + * 0b10001100..mclk frequency = 1/141 * hmclk frequency + * 0b10001101..mclk frequency = 1/142 * hmclk frequency + * 0b10001110..mclk frequency = 1/143 * hmclk frequency + * 0b10001111..mclk frequency = 1/144 * hmclk frequency + * 0b10010000..mclk frequency = 1/145 * hmclk frequency + * 0b10010001..mclk frequency = 1/146 * hmclk frequency + * 0b10010010..mclk frequency = 1/147 * hmclk frequency + * 0b10010011..mclk frequency = 1/148 * hmclk frequency + * 0b10010100..mclk frequency = 1/149 * hmclk frequency + * 0b10010101..mclk frequency = 1/150 * hmclk frequency + * 0b10010110..mclk frequency = 1/151 * hmclk frequency + * 0b10010111..mclk frequency = 1/152 * hmclk frequency + * 0b10011000..mclk frequency = 1/153 * hmclk frequency + * 0b10011001..mclk frequency = 1/154 * hmclk frequency + * 0b10011010..mclk frequency = 1/155 * hmclk frequency + * 0b10011011..mclk frequency = 1/156 * hmclk frequency + * 0b10011100..mclk frequency = 1/157 * hmclk frequency + * 0b10011101..mclk frequency = 1/158 * hmclk frequency + * 0b10011110..mclk frequency = 1/159 * hmclk frequency + * 0b10011111..mclk frequency = 1/160 * hmclk frequency + * 0b10100000..mclk frequency = 1/161 * hmclk frequency + * 0b10100001..mclk frequency = 1/162 * hmclk frequency + * 0b10100010..mclk frequency = 1/163 * hmclk frequency + * 0b10100011..mclk frequency = 1/164 * hmclk frequency + * 0b10100100..mclk frequency = 1/165 * hmclk frequency + * 0b10100101..mclk frequency = 1/166 * hmclk frequency + * 0b10100110..mclk frequency = 1/167 * hmclk frequency + * 0b10100111..mclk frequency = 1/168 * hmclk frequency + * 0b10101000..mclk frequency = 1/169 * hmclk frequency + * 0b10101001..mclk frequency = 1/170 * hmclk frequency + * 0b10101010..mclk frequency = 1/171 * hmclk frequency + * 0b10101011..mclk frequency = 1/172 * hmclk frequency + * 0b10101100..mclk frequency = 1/173 * hmclk frequency + * 0b10101101..mclk frequency = 1/174 * hmclk frequency + * 0b10101110..mclk frequency = 1/175 * hmclk frequency + * 0b10101111..mclk frequency = 1/176 * hmclk frequency + * 0b10110000..mclk frequency = 1/177 * hmclk frequency + * 0b10110001..mclk frequency = 1/178 * hmclk frequency + * 0b10110010..mclk frequency = 1/179 * hmclk frequency + * 0b10110011..mclk frequency = 1/180 * hmclk frequency + * 0b10110100..mclk frequency = 1/181 * hmclk frequency + * 0b10110101..mclk frequency = 1/182 * hmclk frequency + * 0b10110110..mclk frequency = 1/183 * hmclk frequency + * 0b10110111..mclk frequency = 1/184 * hmclk frequency + * 0b10111000..mclk frequency = 1/185 * hmclk frequency + * 0b10111001..mclk frequency = 1/186 * hmclk frequency + * 0b10111010..mclk frequency = 1/187 * hmclk frequency + * 0b10111011..mclk frequency = 1/188 * hmclk frequency + * 0b10111100..mclk frequency = 1/189 * hmclk frequency + * 0b10111101..mclk frequency = 1/190 * hmclk frequency + * 0b10111110..mclk frequency = 1/191 * hmclk frequency + * 0b10111111..mclk frequency = 1/192 * hmclk frequency + * 0b11000000..mclk frequency = 1/193 * hmclk frequency + * 0b11000001..mclk frequency = 1/194 * hmclk frequency + * 0b11000010..mclk frequency = 1/195 * hmclk frequency + * 0b11000011..mclk frequency = 1/196 * hmclk frequency + * 0b11000100..mclk frequency = 1/197 * hmclk frequency + * 0b11000101..mclk frequency = 1/198 * hmclk frequency + * 0b11000110..mclk frequency = 1/199 * hmclk frequency + * 0b11000111..mclk frequency = 1/200 * hmclk frequency + * 0b11001000..mclk frequency = 1/201 * hmclk frequency + * 0b11001001..mclk frequency = 1/202 * hmclk frequency + * 0b11001010..mclk frequency = 1/203 * hmclk frequency + * 0b11001011..mclk frequency = 1/204 * hmclk frequency + * 0b11001100..mclk frequency = 1/205 * hmclk frequency + * 0b11001101..mclk frequency = 1/206 * hmclk frequency + * 0b11001110..mclk frequency = 1/207 * hmclk frequency + * 0b11001111..mclk frequency = 1/208 * hmclk frequency + * 0b11010000..mclk frequency = 1/209 * hmclk frequency + * 0b11010001..mclk frequency = 1/210 * hmclk frequency + * 0b11010010..mclk frequency = 1/211 * hmclk frequency + * 0b11010011..mclk frequency = 1/212 * hmclk frequency + * 0b11010100..mclk frequency = 1/213 * hmclk frequency + * 0b11010101..mclk frequency = 1/214 * hmclk frequency + * 0b11010110..mclk frequency = 1/215 * hmclk frequency + * 0b11010111..mclk frequency = 1/216 * hmclk frequency + * 0b11011000..mclk frequency = 1/217 * hmclk frequency + * 0b11011001..mclk frequency = 1/218 * hmclk frequency + * 0b11011010..mclk frequency = 1/219 * hmclk frequency + * 0b11011011..mclk frequency = 1/220 * hmclk frequency + * 0b11011100..mclk frequency = 1/221 * hmclk frequency + * 0b11011101..mclk frequency = 1/222 * hmclk frequency + * 0b11011110..mclk frequency = 1/223 * hmclk frequency + * 0b11011111..mclk frequency = 1/224 * hmclk frequency + * 0b11100000..mclk frequency = 1/225 * hmclk frequency + * 0b11100001..mclk frequency = 1/226 * hmclk frequency + * 0b11100010..mclk frequency = 1/227 * hmclk frequency + * 0b11100011..mclk frequency = 1/228 * hmclk frequency + * 0b11100100..mclk frequency = 1/229 * hmclk frequency + * 0b11100101..mclk frequency = 1/230 * hmclk frequency + * 0b11100110..mclk frequency = 1/231 * hmclk frequency + * 0b11100111..mclk frequency = 1/232 * hmclk frequency + * 0b11101000..mclk frequency = 1/233 * hmclk frequency + * 0b11101001..mclk frequency = 1/234 * hmclk frequency + * 0b11101010..mclk frequency = 1/235 * hmclk frequency + * 0b11101011..mclk frequency = 1/236 * hmclk frequency + * 0b11101100..mclk frequency = 1/237 * hmclk frequency + * 0b11101101..mclk frequency = 1/238 * hmclk frequency + * 0b11101110..mclk frequency = 1/239 * hmclk frequency + * 0b11101111..mclk frequency = 1/240 * hmclk frequency + * 0b11110000..mclk frequency = 1/241 * hmclk frequency + * 0b11110001..mclk frequency = 1/242 * hmclk frequency + * 0b11110010..mclk frequency = 1/243 * hmclk frequency + * 0b11110011..mclk frequency = 1/244 * hmclk frequency + * 0b11110100..mclk frequency = 1/245 * hmclk frequency + * 0b11110101..mclk frequency = 1/246 * hmclk frequency + * 0b11110110..mclk frequency = 1/247 * hmclk frequency + * 0b11110111..mclk frequency = 1/248 * hmclk frequency + * 0b11111000..mclk frequency = 1/249 * hmclk frequency + * 0b11111001..mclk frequency = 1/250 * hmclk frequency + * 0b11111010..mclk frequency = 1/251 * hmclk frequency + * 0b11111011..mclk frequency = 1/252 * hmclk frequency + * 0b11111100..mclk frequency = 1/253 * hmclk frequency + * 0b11111101..mclk frequency = 1/254 * hmclk frequency + * 0b11111110..mclk frequency = 1/255 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample + * 0b0..32 + * 0b1..64 + */ +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze + * 0b0..Timer counter works normally + * 0b1..Reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) +/*! @} */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL - Select 128-bit DCP key from 256-bit key from SNVS/OCOTP + * 0b0..Select [127:0] from SNVS/OCOTP key as DCP key + * 0b1..Select [255:128] from SNVS/OCOTP key as DCP key + */ +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) +/*! @} */ + +/*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from GPT2_CAPTURE1 + * 0b1..source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + */ +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ + +/*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ + +/*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x7E00U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..Reserved + * 0b11..Reserved + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..Reserved + * 0b11..Reserved + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..Reserved + * 0b11..Reserved + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..Reserved + * 0b11..Reserved + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U) +#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK) +/*! @} */ + +/*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) +#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +/*! @} */ + +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + +/*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) +/*! @} */ + +/*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFU) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ + +/*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ + +/*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ + +/*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ + +/*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ + +/*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ + +/*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ + +/*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x400AC000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ + __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ + __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x400A8000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ +} IOMUXC_SNVS_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks + * @{ + */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ + + +/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS_GPR base address */ +#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) +/** Peripheral IOMUXC_SNVS_GPR base pointer */ +#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) +/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ +#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } +/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ +#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +/*! @{ */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ + +/*! @name KPSR - Keypad Status Register */ +/*! @{ */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ + +/*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ + +/*! @name KPDR - Keypad Data Register */ +/*! @{ */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x401FC000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Master Control Register */ +/*! @{ */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Master Status Register */ +/*! @{ */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ + +/*! @name MDER - Master DMA Enable Register */ +/*! @{ */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ + +/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Master Data Match Register */ +/*! @{ */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Master Receive Data Register */ +/*! @{ */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Slave Control Register */ +/*! @{ */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Slave Status Register */ +/*! @{ */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address + * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid + * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Slave Address Match Register */ +/*! @{ */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Slave Address Status Register */ +/*! @{ */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x403F0000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x403F4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< Status Register, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + uint8_t RESERVED_3[20]; + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st + * data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., + * [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration Register */ +/*! @{ */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control Register */ +/*! @{ */ +#define LPSPI_FCR_TXWATER_MASK (0xFU) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0xF0000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ +#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command Register */ +/*! @{ */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data Register */ +/*! @{ */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status Register */ +/*! @{ */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data Register */ +/*! @{ */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x40394000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x40398000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - LPUART Status Register */ +/*! @{ */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle + * character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During + * address match wakeup, the IDLE bit does set when an address does not match. + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received + * after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on + * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is + * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - LPUART Control Register */ +/*! @{ */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - LPUART Data Register */ +/*! @{ */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a + * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the + * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent + * do not affect its transmission. + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the + * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and + * shift register are completely sent, including the last stop bit. + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause + * the receiver data register to become full. RTS is asserted if the receiver data register is not full and + * has not detected a start bit that would cause the receiver data register to become full. + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - LPUART Watermark Register */ +/*! @{ */ +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40184000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x40188000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x4018C000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x40190000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + uint8_t RESERVED_5[32]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_6[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_7[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_15[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_23[140]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_24[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_25[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_33[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_34[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_35[12]; + __IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_36[28]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_37[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +/*! @{ */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U) +#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U) +#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK) +#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP1_SHIFT (16U) +#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) +#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U) +#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) +#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) +#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) +#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) +#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) +#define OCOTP_LOCK_GP3_MASK (0xC000000U) +#define OCOTP_LOCK_GP3_SHIFT (26U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) +#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) +#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */ +/*! @{ */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ + +/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */ +/*! @{ */ +#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_BITS_SHIFT (0U) +#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK) +/*! @} */ + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ + +/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ + +/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP20_BITS_SHIFT (0U) +#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ + +/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP21_BITS_SHIFT (0U) +#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ + +/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP22_BITS_SHIFT (0U) +#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ + +/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP23_BITS_SHIFT (0U) +#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x401F4000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[544]; + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ + uint8_t RESERVED_1[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ + +/*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x400F4000u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +/*! @{ */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ + +/*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +/*! @{ */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +/*! @{ */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +/*! @{ */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40084000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[272]; + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ + __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ + __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ + __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ + __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ + __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ + __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ + __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ + __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ + __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ + __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ + __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ + __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) +#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) +#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) +#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) +#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) +#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) +#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) +#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) +#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) +#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) +#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) +#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) +#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) +#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_OSC_I_MASK (0x6000U) +#define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) +#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) +#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) +#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) +#define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) +#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) +#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) +#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) +#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) +#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) +#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) +#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) +#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) +#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) +#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_REG2_OK_SHIFT (22U) +#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) +#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) +#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) +#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) +#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) +#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x400D8000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + uint8_t RESERVED_1[8]; + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it will force the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master + * reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it + * will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA + * output that is high at the end of a period will maintain this state until a match with VAL3 clears the + * output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) +#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) +#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ +#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to + * which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) +#define PWM_DISMAP_DIS1A_MASK (0xFU) +#define PWM_DISMAP_DIS1A_SHIFT (0U) +#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) +#define PWM_DISMAP_DIS1B_MASK (0xF0U) +#define PWM_DISMAP_DIS1B_SHIFT (4U) +#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (2U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ +#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ +#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No + * further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and + * CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No + * further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and + * CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The + * process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further + * captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, + * then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and + * CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock + * will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL + * encounters problems. These bits are write protected until the next reset. + */ +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of + * FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual + * FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as + * programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further + * controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the + * state of FSTS[FFLAGx]. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x403DC000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } } +#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } } +#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn } } +#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x40180000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTWDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer + * @{ + */ + +/** RTWDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} RTWDOG_Type; + +/* ---------------------------------------------------------------------------- + -- RTWDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ +#define RTWDOG_CS_STOP_MASK (0x1U) +#define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ +#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) +#define RTWDOG_CS_WAIT_MASK (0x2U) +#define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ +#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) +#define RTWDOG_CS_DBG_MASK (0x4U) +#define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ +#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) +#define RTWDOG_CS_TST_MASK (0x18U) +#define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should + * use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ +#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) +#define RTWDOG_CS_UPDATE_MASK (0x20U) +#define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ +#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) +#define RTWDOG_CS_INT_MASK (0x40U) +#define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ +#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) +#define RTWDOG_CS_EN_MASK (0x80U) +#define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ +#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) +#define RTWDOG_CS_CLK_MASK (0x300U) +#define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ +#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) +#define RTWDOG_CS_RCS_MASK (0x400U) +#define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ +#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) +#define RTWDOG_CS_ULK_MASK (0x800U) +#define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ +#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) +#define RTWDOG_CS_PRES_MASK (0x1000U) +#define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ +#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) +#define RTWDOG_CS_CMD32EN_MASK (0x2000U) +#define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ +#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) +#define RTWDOG_CS_FLG_MASK (0x4000U) +#define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ +#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) +#define RTWDOG_CS_WIN_MASK (0x8000U) +#define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ +#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - Watchdog Counter Register */ +/*! @{ */ +#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) +#define RTWDOG_CNT_CNTLOW_SHIFT (0U) +#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) +#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) +#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ +#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) +#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) +#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) +#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window Register */ +/*! @{ */ +#define RTWDOG_WIN_WINLOW_MASK (0xFFU) +#define RTWDOG_WIN_WINLOW_SHIFT (0U) +#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) +#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) +#define RTWDOG_WIN_WINHIGH_SHIFT (8U) +#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTWDOG_Register_Masks */ + + +/* RTWDOG - Peripheral instance base addresses */ +/** Peripheral RTWDOG base address */ +#define RTWDOG_BASE (0x400BC000u) +/** Peripheral RTWDOG base pointer */ +#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) +/** Array initializer of RTWDOG peripheral base addresses */ +#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } +/** Array initializer of RTWDOG peripheral base pointers */ +#define RTWDOG_BASE_PTRS { RTWDOG } +/** Interrupt vectors for the RTWDOG peripheral type */ +#define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group RTWDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2792]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (4U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x400D4000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..XTALOSC input (XTALOSC clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b010..tx_clk1 (from SAI1) + * 0b011..tx_clk2 SPDIF_EXT_CLK, from pads + * 0b100..tx_clk3 (from SAI2) + * 0b101..ipg_clk input (frequency divided) + * 0b110..tx_clk4 (from SAI3) + */ +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x40380000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[16]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +/*! @{ */ +#define SRC_SCR_LOCKUP_RST_MASK (0x10U) +#define SRC_SCR_LOCKUP_RST_SHIFT (4U) +/*! lockup_rst + * 0b0..disabled + * 0b1..enabled + */ +#define SRC_SCR_LOCKUP_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCKUP_RST_SHIFT)) & SRC_SCR_LOCKUP_RST_MASK) +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_LOCKUP_MASK (0x2U) +#define SRC_SRSR_LOCKUP_SHIFT (1U) +/*! lockup + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ +#define SRC_SRSR_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SHIFT)) & SRC_SRSR_LOCKUP_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is not a result of the mentioned case. + */ +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x400F8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +/* Backward compatibility */ +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_LOCKUP_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[384]; + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ + uint8_t RESERVED_1[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x400D8000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer + * @{ + */ + +/** TMR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ + __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ + __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ + __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ + __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ + __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ + __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ + __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ + __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ + __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ + __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ + __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ + uint8_t RESERVED_0[4]; + __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ + } CHANNEL[4]; +} TMR_Type; + +/* ---------------------------------------------------------------------------- + -- TMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Register_Masks TMR Register Masks + * @{ + */ + +/*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ +#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) +#define TMR_COMP1_COMPARISON_1_SHIFT (0U) +#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ + +/* The count of TMR_COMP1 */ +#define TMR_COMP1_COUNT (4U) + +/*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ +#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) +#define TMR_COMP2_COMPARISON_2_SHIFT (0U) +#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ + +/* The count of TMR_COMP2 */ +#define TMR_COMP2_COUNT (4U) + +/*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ +#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) +#define TMR_CAPT_CAPTURE_SHIFT (0U) +#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ + +/* The count of TMR_CAPT */ +#define TMR_CAPT_COUNT (4U) + +/*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ +#define TMR_LOAD_LOAD_MASK (0xFFFFU) +#define TMR_LOAD_LOAD_SHIFT (0U) +#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ + +/* The count of TMR_LOAD */ +#define TMR_LOAD_COUNT (4U) + +/*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ +#define TMR_HOLD_HOLD_MASK (0xFFFFU) +#define TMR_HOLD_HOLD_SHIFT (0U) +#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ + +/* The count of TMR_HOLD */ +#define TMR_HOLD_COUNT (4U) + +/*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ +#define TMR_CNTR_COUNTER_MASK (0xFFFFU) +#define TMR_CNTR_COUNTER_SHIFT (0U) +#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ + +/* The count of TMR_CNTR */ +#define TMR_CNTR_COUNT (4U) + +/*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ +#define TMR_CTRL_OUTMODE_MASK (0x7U) +#define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ +#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) +#define TMR_CTRL_COINIT_MASK (0x8U) +#define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ +#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) +#define TMR_CTRL_DIR_MASK (0x10U) +#define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ +#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) +#define TMR_CTRL_LENGTH_MASK (0x20U) +#define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter + * reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. + * When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful + * comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 + * value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ +#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) +#define TMR_CTRL_ONCE_MASK (0x40U) +#define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a + * COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When + * output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to + * the COMP2 value, and then stops. + */ +#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) +#define TMR_CTRL_SCS_MASK (0x180U) +#define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ +#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) +#define TMR_CTRL_PCS_MASK (0x1E00U) +#define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ +#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) +#define TMR_CTRL_CM_MASK (0xE000U) +#define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges + * are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising + * edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only + * when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ +#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ + +/* The count of TMR_CTRL */ +#define TMR_CTRL_COUNT (4U) + +/*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ +#define TMR_SCTRL_OEN_MASK (0x1U) +#define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as + * their input see the driven value. The polarity of the signal is determined by OPS. + */ +#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) +#define TMR_SCTRL_OPS_MASK (0x2U) +#define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ +#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) +#define TMR_SCTRL_FORCE_MASK (0x4U) +#define TMR_SCTRL_FORCE_SHIFT (2U) +#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) +#define TMR_SCTRL_VAL_MASK (0x8U) +#define TMR_SCTRL_VAL_SHIFT (3U) +#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) +#define TMR_SCTRL_EEOF_MASK (0x10U) +#define TMR_SCTRL_EEOF_SHIFT (4U) +#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) +#define TMR_SCTRL_MSTR_MASK (0x20U) +#define TMR_SCTRL_MSTR_SHIFT (5U) +#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) +#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) +#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ +#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) +#define TMR_SCTRL_INPUT_MASK (0x100U) +#define TMR_SCTRL_INPUT_SHIFT (8U) +#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) +#define TMR_SCTRL_IPS_MASK (0x200U) +#define TMR_SCTRL_IPS_SHIFT (9U) +#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) +#define TMR_SCTRL_IEFIE_MASK (0x400U) +#define TMR_SCTRL_IEFIE_SHIFT (10U) +#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) +#define TMR_SCTRL_IEF_MASK (0x800U) +#define TMR_SCTRL_IEF_SHIFT (11U) +#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) +#define TMR_SCTRL_TOFIE_MASK (0x1000U) +#define TMR_SCTRL_TOFIE_SHIFT (12U) +#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) +#define TMR_SCTRL_TOF_MASK (0x2000U) +#define TMR_SCTRL_TOF_SHIFT (13U) +#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) +#define TMR_SCTRL_TCFIE_MASK (0x4000U) +#define TMR_SCTRL_TCFIE_SHIFT (14U) +#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) +#define TMR_SCTRL_TCF_MASK (0x8000U) +#define TMR_SCTRL_TCF_SHIFT (15U) +#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ + +/* The count of TMR_SCTRL */ +#define TMR_SCTRL_COUNT (4U) + +/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ +#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) +#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) +#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ + +/* The count of TMR_CMPLD1 */ +#define TMR_CMPLD1_COUNT (4U) + +/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ +#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) +#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) +#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ + +/* The count of TMR_CMPLD2 */ +#define TMR_CMPLD2_COUNT (4U) + +/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ +#define TMR_CSCTRL_CL1_MASK (0x3U) +#define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) +#define TMR_CSCTRL_CL2_MASK (0xCU) +#define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) +#define TMR_CSCTRL_TCF1_MASK (0x10U) +#define TMR_CSCTRL_TCF1_SHIFT (4U) +#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) +#define TMR_CSCTRL_TCF2_MASK (0x20U) +#define TMR_CSCTRL_TCF2_SHIFT (5U) +#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) +#define TMR_CSCTRL_TCF1EN_MASK (0x40U) +#define TMR_CSCTRL_TCF1EN_SHIFT (6U) +#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) +#define TMR_CSCTRL_TCF2EN_MASK (0x80U) +#define TMR_CSCTRL_TCF2EN_SHIFT (7U) +#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) +#define TMR_CSCTRL_UP_MASK (0x200U) +#define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ +#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) +#define TMR_CSCTRL_TCI_MASK (0x400U) +#define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ +#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) +#define TMR_CSCTRL_ROC_MASK (0x800U) +#define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ +#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) +#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) +#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ +#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) +#define TMR_CSCTRL_FAULT_MASK (0x2000U) +#define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ +#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) +#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) +#define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ +#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ + +/* The count of TMR_CSCTRL */ +#define TMR_CSCTRL_COUNT (4U) + +/*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ +#define TMR_FILT_FILT_PER_MASK (0xFFU) +#define TMR_FILT_FILT_PER_SHIFT (0U) +#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) +#define TMR_FILT_FILT_CNT_MASK (0x700U) +#define TMR_FILT_FILT_CNT_SHIFT (8U) +#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of TMR_FILT */ +#define TMR_FILT_COUNT (4U) + +/*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ +#define TMR_DMA_IEFDE_MASK (0x1U) +#define TMR_DMA_IEFDE_SHIFT (0U) +#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) +#define TMR_DMA_CMPLD1DE_MASK (0x2U) +#define TMR_DMA_CMPLD1DE_SHIFT (1U) +#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) +#define TMR_DMA_CMPLD2DE_MASK (0x4U) +#define TMR_DMA_CMPLD2DE_SHIFT (2U) +#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ + +/* The count of TMR_DMA */ +#define TMR_DMA_COUNT (4U) + +/*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ +#define TMR_ENBL_ENBL_MASK (0xFU) +#define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ +#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ + +/* The count of TMR_ENBL */ +#define TMR_ENBL_COUNT (4U) + + +/*! + * @} + */ /* end of group TMR_Register_Masks */ + + +/* TMR - Peripheral instance base addresses */ +/** Peripheral TMR1 base address */ +#define TMR1_BASE (0x401DC000u) +/** Peripheral TMR1 base pointer */ +#define TMR1 ((TMR_Type *)TMR1_BASE) +/** Array initializer of TMR peripheral base addresses */ +#define TMR_BASE_ADDRS { 0u, TMR1_BASE } +/** Array initializer of TMR peripheral base pointers */ +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1 } +/** Interrupt vectors for the TMR peripheral type */ +#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn } + +/*! + * @} + */ /* end of group TMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + uint8_t RESERVED_0[64]; + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ +#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) +#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ +#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRNG_MCTL_UNUSED4_MASK (0x10U) +#define TRNG_MCTL_UNUSED4_SHIFT (4U) +#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) +#define TRNG_MCTL_TRNG_ACC_MASK (0x20U) +#define TRNG_MCTL_TRNG_ACC_SHIFT (5U) +#define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) +#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) +#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) +#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) +#define TRNG_MCTL_TST_OUT_MASK (0x800U) +#define TRNG_MCTL_TST_OUT_SHIFT (11U) +#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) +#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) +#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) +#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENT - Entropy Read Register */ +/*! @{ */ +#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENT_ENT_SHIFT (0U) +#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENT */ +#define TRNG_ENT_COUNT (16U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ +#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) +#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) +#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) +#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) +#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) +#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) +#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) +#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG base address */ +#define TRNG_BASE (0x400CC000u) +/** Peripheral TRNG base pointer */ +#define TRNG ((TRNG_Type *)TRNG_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG_IRQn } + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command Register */ +/*! @{ */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status Register */ +/*! @{ */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB base address */ +#define USB_BASE (0x402E0000u) +/** Peripheral USB base pointer */ +#define USB ((USB_Type *)USB_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn } +#define USBHS_IRQHandler USB_OTG1_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register, offset: 0x800 */ + uint8_t RESERVED_1[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register, offset: 0x818 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTG1 Control Register */ +/*! @{ */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ + +/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register */ +/*! @{ */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC base address */ +#define USBNC_BASE (0x402E0000u) +/** Peripheral USBNC base pointer */ +#define USBNC ((USBNC_Type *)USBNC_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ + +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY base address */ +#define USBPHY_BASE (0x400D9000u) +/** Peripheral USBPHY base pointer */ +#define USBPHY ((USBPHY_Type *)USBPHY_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + struct { /* offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ + } INSTANCE[1]; + uint8_t RESERVED_1[96]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (1U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (1U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (1U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (1U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (1U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (1U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (1U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (1U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (1U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (1U) + +/*! @name MISC - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (1U) + +/*! @name MISC_SET - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (1U) + +/*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (1U) + +/*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (1U) + +/*! @name DIGPROG - Chip Silicon Version */ +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011000100000000000000010..Silicon revision 1.0 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x400D8000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x400B8000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x400D0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer + * @{ + */ + +/** XBARA - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ + __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ + __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ + __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ + __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ + __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ + __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ + __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ + __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ + __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ + __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ + __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ + __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ + __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ + __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ + __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ + __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ + __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ + __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ + __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ + __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ + __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ + __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ + __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ + __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ + __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ + __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ + __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ + __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ + __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ + __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ + __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ + __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ + __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ + __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ + __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ + __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ + __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ + __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ + __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ + __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ + __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ + __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ + __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ + __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ + __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ + __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ + __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ + __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ + __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ + __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ + __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ + __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ + __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ + __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ + __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ + __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ + __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ + __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ + __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ + __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ +} XBARA_Type; + +/* ---------------------------------------------------------------------------- + -- XBARA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Register_Masks XBARA Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ +#define XBARA_SEL0_SEL0_MASK (0x7FU) +#define XBARA_SEL0_SEL0_SHIFT (0U) +#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) +#define XBARA_SEL0_SEL1_MASK (0x7F00U) +#define XBARA_SEL0_SEL1_SHIFT (8U) +#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ +#define XBARA_SEL1_SEL2_MASK (0x7FU) +#define XBARA_SEL1_SEL2_SHIFT (0U) +#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) +#define XBARA_SEL1_SEL3_MASK (0x7F00U) +#define XBARA_SEL1_SEL3_SHIFT (8U) +#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ +#define XBARA_SEL2_SEL4_MASK (0x7FU) +#define XBARA_SEL2_SEL4_SHIFT (0U) +#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) +#define XBARA_SEL2_SEL5_MASK (0x7F00U) +#define XBARA_SEL2_SEL5_SHIFT (8U) +#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ +#define XBARA_SEL3_SEL6_MASK (0x7FU) +#define XBARA_SEL3_SEL6_SHIFT (0U) +#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) +#define XBARA_SEL3_SEL7_MASK (0x7F00U) +#define XBARA_SEL3_SEL7_SHIFT (8U) +#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ +#define XBARA_SEL4_SEL8_MASK (0x7FU) +#define XBARA_SEL4_SEL8_SHIFT (0U) +#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) +#define XBARA_SEL4_SEL9_MASK (0x7F00U) +#define XBARA_SEL4_SEL9_SHIFT (8U) +#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ +#define XBARA_SEL5_SEL10_MASK (0x7FU) +#define XBARA_SEL5_SEL10_SHIFT (0U) +#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) +#define XBARA_SEL5_SEL11_MASK (0x7F00U) +#define XBARA_SEL5_SEL11_SHIFT (8U) +#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ +#define XBARA_SEL6_SEL12_MASK (0x7FU) +#define XBARA_SEL6_SEL12_SHIFT (0U) +#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) +#define XBARA_SEL6_SEL13_MASK (0x7F00U) +#define XBARA_SEL6_SEL13_SHIFT (8U) +#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ +#define XBARA_SEL7_SEL14_MASK (0x7FU) +#define XBARA_SEL7_SEL14_SHIFT (0U) +#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) +#define XBARA_SEL7_SEL15_MASK (0x7F00U) +#define XBARA_SEL7_SEL15_SHIFT (8U) +#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ + +/*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ +#define XBARA_SEL8_SEL16_MASK (0x7FU) +#define XBARA_SEL8_SEL16_SHIFT (0U) +#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) +#define XBARA_SEL8_SEL17_MASK (0x7F00U) +#define XBARA_SEL8_SEL17_SHIFT (8U) +#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ + +/*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ +#define XBARA_SEL9_SEL18_MASK (0x7FU) +#define XBARA_SEL9_SEL18_SHIFT (0U) +#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) +#define XBARA_SEL9_SEL19_MASK (0x7F00U) +#define XBARA_SEL9_SEL19_SHIFT (8U) +#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ + +/*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ +#define XBARA_SEL10_SEL20_MASK (0x7FU) +#define XBARA_SEL10_SEL20_SHIFT (0U) +#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) +#define XBARA_SEL10_SEL21_MASK (0x7F00U) +#define XBARA_SEL10_SEL21_SHIFT (8U) +#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ + +/*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ +#define XBARA_SEL11_SEL22_MASK (0x7FU) +#define XBARA_SEL11_SEL22_SHIFT (0U) +#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) +#define XBARA_SEL11_SEL23_MASK (0x7F00U) +#define XBARA_SEL11_SEL23_SHIFT (8U) +#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ + +/*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ +#define XBARA_SEL12_SEL24_MASK (0x7FU) +#define XBARA_SEL12_SEL24_SHIFT (0U) +#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) +#define XBARA_SEL12_SEL25_MASK (0x7F00U) +#define XBARA_SEL12_SEL25_SHIFT (8U) +#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ + +/*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ +#define XBARA_SEL13_SEL26_MASK (0x7FU) +#define XBARA_SEL13_SEL26_SHIFT (0U) +#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) +#define XBARA_SEL13_SEL27_MASK (0x7F00U) +#define XBARA_SEL13_SEL27_SHIFT (8U) +#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ + +/*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ +#define XBARA_SEL14_SEL28_MASK (0x7FU) +#define XBARA_SEL14_SEL28_SHIFT (0U) +#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) +#define XBARA_SEL14_SEL29_MASK (0x7F00U) +#define XBARA_SEL14_SEL29_SHIFT (8U) +#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ + +/*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ +#define XBARA_SEL15_SEL30_MASK (0x7FU) +#define XBARA_SEL15_SEL30_SHIFT (0U) +#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) +#define XBARA_SEL15_SEL31_MASK (0x7F00U) +#define XBARA_SEL15_SEL31_SHIFT (8U) +#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ + +/*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ +#define XBARA_SEL16_SEL32_MASK (0x7FU) +#define XBARA_SEL16_SEL32_SHIFT (0U) +#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) +#define XBARA_SEL16_SEL33_MASK (0x7F00U) +#define XBARA_SEL16_SEL33_SHIFT (8U) +#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ + +/*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ +#define XBARA_SEL17_SEL34_MASK (0x7FU) +#define XBARA_SEL17_SEL34_SHIFT (0U) +#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) +#define XBARA_SEL17_SEL35_MASK (0x7F00U) +#define XBARA_SEL17_SEL35_SHIFT (8U) +#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ + +/*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ +#define XBARA_SEL18_SEL36_MASK (0x7FU) +#define XBARA_SEL18_SEL36_SHIFT (0U) +#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) +#define XBARA_SEL18_SEL37_MASK (0x7F00U) +#define XBARA_SEL18_SEL37_SHIFT (8U) +#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ + +/*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ +#define XBARA_SEL19_SEL38_MASK (0x7FU) +#define XBARA_SEL19_SEL38_SHIFT (0U) +#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) +#define XBARA_SEL19_SEL39_MASK (0x7F00U) +#define XBARA_SEL19_SEL39_SHIFT (8U) +#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ + +/*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ +#define XBARA_SEL20_SEL40_MASK (0x7FU) +#define XBARA_SEL20_SEL40_SHIFT (0U) +#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) +#define XBARA_SEL20_SEL41_MASK (0x7F00U) +#define XBARA_SEL20_SEL41_SHIFT (8U) +#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ + +/*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ +#define XBARA_SEL21_SEL42_MASK (0x7FU) +#define XBARA_SEL21_SEL42_SHIFT (0U) +#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) +#define XBARA_SEL21_SEL43_MASK (0x7F00U) +#define XBARA_SEL21_SEL43_SHIFT (8U) +#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ + +/*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ +#define XBARA_SEL22_SEL44_MASK (0x7FU) +#define XBARA_SEL22_SEL44_SHIFT (0U) +#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) +#define XBARA_SEL22_SEL45_MASK (0x7F00U) +#define XBARA_SEL22_SEL45_SHIFT (8U) +#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ + +/*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ +#define XBARA_SEL23_SEL46_MASK (0x7FU) +#define XBARA_SEL23_SEL46_SHIFT (0U) +#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) +#define XBARA_SEL23_SEL47_MASK (0x7F00U) +#define XBARA_SEL23_SEL47_SHIFT (8U) +#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ + +/*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ +#define XBARA_SEL24_SEL48_MASK (0x7FU) +#define XBARA_SEL24_SEL48_SHIFT (0U) +#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) +#define XBARA_SEL24_SEL49_MASK (0x7F00U) +#define XBARA_SEL24_SEL49_SHIFT (8U) +#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ + +/*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ +#define XBARA_SEL25_SEL50_MASK (0x7FU) +#define XBARA_SEL25_SEL50_SHIFT (0U) +#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) +#define XBARA_SEL25_SEL51_MASK (0x7F00U) +#define XBARA_SEL25_SEL51_SHIFT (8U) +#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ + +/*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ +#define XBARA_SEL26_SEL52_MASK (0x7FU) +#define XBARA_SEL26_SEL52_SHIFT (0U) +#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) +#define XBARA_SEL26_SEL53_MASK (0x7F00U) +#define XBARA_SEL26_SEL53_SHIFT (8U) +#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ + +/*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ +#define XBARA_SEL27_SEL54_MASK (0x7FU) +#define XBARA_SEL27_SEL54_SHIFT (0U) +#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) +#define XBARA_SEL27_SEL55_MASK (0x7F00U) +#define XBARA_SEL27_SEL55_SHIFT (8U) +#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ + +/*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ +#define XBARA_SEL28_SEL56_MASK (0x7FU) +#define XBARA_SEL28_SEL56_SHIFT (0U) +#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) +#define XBARA_SEL28_SEL57_MASK (0x7F00U) +#define XBARA_SEL28_SEL57_SHIFT (8U) +#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ + +/*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ +#define XBARA_SEL29_SEL58_MASK (0x7FU) +#define XBARA_SEL29_SEL58_SHIFT (0U) +#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) +#define XBARA_SEL29_SEL59_MASK (0x7F00U) +#define XBARA_SEL29_SEL59_SHIFT (8U) +#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ + +/*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ +#define XBARA_SEL30_SEL60_MASK (0x7FU) +#define XBARA_SEL30_SEL60_SHIFT (0U) +#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) +#define XBARA_SEL30_SEL61_MASK (0x7F00U) +#define XBARA_SEL30_SEL61_SHIFT (8U) +#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ + +/*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ +#define XBARA_SEL31_SEL62_MASK (0x7FU) +#define XBARA_SEL31_SEL62_SHIFT (0U) +#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) +#define XBARA_SEL31_SEL63_MASK (0x7F00U) +#define XBARA_SEL31_SEL63_SHIFT (8U) +#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ + +/*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ +#define XBARA_SEL32_SEL64_MASK (0x7FU) +#define XBARA_SEL32_SEL64_SHIFT (0U) +#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) +#define XBARA_SEL32_SEL65_MASK (0x7F00U) +#define XBARA_SEL32_SEL65_SHIFT (8U) +#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ + +/*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ +#define XBARA_SEL33_SEL66_MASK (0x7FU) +#define XBARA_SEL33_SEL66_SHIFT (0U) +#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) +#define XBARA_SEL33_SEL67_MASK (0x7F00U) +#define XBARA_SEL33_SEL67_SHIFT (8U) +#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ + +/*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ +#define XBARA_SEL34_SEL68_MASK (0x7FU) +#define XBARA_SEL34_SEL68_SHIFT (0U) +#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) +#define XBARA_SEL34_SEL69_MASK (0x7F00U) +#define XBARA_SEL34_SEL69_SHIFT (8U) +#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ + +/*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ +#define XBARA_SEL35_SEL70_MASK (0x7FU) +#define XBARA_SEL35_SEL70_SHIFT (0U) +#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) +#define XBARA_SEL35_SEL71_MASK (0x7F00U) +#define XBARA_SEL35_SEL71_SHIFT (8U) +#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ + +/*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ +#define XBARA_SEL36_SEL72_MASK (0x7FU) +#define XBARA_SEL36_SEL72_SHIFT (0U) +#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) +#define XBARA_SEL36_SEL73_MASK (0x7F00U) +#define XBARA_SEL36_SEL73_SHIFT (8U) +#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ + +/*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ +#define XBARA_SEL37_SEL74_MASK (0x7FU) +#define XBARA_SEL37_SEL74_SHIFT (0U) +#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) +#define XBARA_SEL37_SEL75_MASK (0x7F00U) +#define XBARA_SEL37_SEL75_SHIFT (8U) +#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ + +/*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ +#define XBARA_SEL38_SEL76_MASK (0x7FU) +#define XBARA_SEL38_SEL76_SHIFT (0U) +#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) +#define XBARA_SEL38_SEL77_MASK (0x7F00U) +#define XBARA_SEL38_SEL77_SHIFT (8U) +#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ + +/*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ +#define XBARA_SEL39_SEL78_MASK (0x7FU) +#define XBARA_SEL39_SEL78_SHIFT (0U) +#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) +#define XBARA_SEL39_SEL79_MASK (0x7F00U) +#define XBARA_SEL39_SEL79_SHIFT (8U) +#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ + +/*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ +#define XBARA_SEL40_SEL80_MASK (0x7FU) +#define XBARA_SEL40_SEL80_SHIFT (0U) +#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) +#define XBARA_SEL40_SEL81_MASK (0x7F00U) +#define XBARA_SEL40_SEL81_SHIFT (8U) +#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ + +/*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ +#define XBARA_SEL41_SEL82_MASK (0x7FU) +#define XBARA_SEL41_SEL82_SHIFT (0U) +#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) +#define XBARA_SEL41_SEL83_MASK (0x7F00U) +#define XBARA_SEL41_SEL83_SHIFT (8U) +#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ + +/*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ +#define XBARA_SEL42_SEL84_MASK (0x7FU) +#define XBARA_SEL42_SEL84_SHIFT (0U) +#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) +#define XBARA_SEL42_SEL85_MASK (0x7F00U) +#define XBARA_SEL42_SEL85_SHIFT (8U) +#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ + +/*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ +#define XBARA_SEL43_SEL86_MASK (0x7FU) +#define XBARA_SEL43_SEL86_SHIFT (0U) +#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) +#define XBARA_SEL43_SEL87_MASK (0x7F00U) +#define XBARA_SEL43_SEL87_SHIFT (8U) +#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ + +/*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ +#define XBARA_SEL44_SEL88_MASK (0x7FU) +#define XBARA_SEL44_SEL88_SHIFT (0U) +#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) +#define XBARA_SEL44_SEL89_MASK (0x7F00U) +#define XBARA_SEL44_SEL89_SHIFT (8U) +#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ + +/*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ +#define XBARA_SEL45_SEL90_MASK (0x7FU) +#define XBARA_SEL45_SEL90_SHIFT (0U) +#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) +#define XBARA_SEL45_SEL91_MASK (0x7F00U) +#define XBARA_SEL45_SEL91_SHIFT (8U) +#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ + +/*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ +#define XBARA_SEL46_SEL92_MASK (0x7FU) +#define XBARA_SEL46_SEL92_SHIFT (0U) +#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) +#define XBARA_SEL46_SEL93_MASK (0x7F00U) +#define XBARA_SEL46_SEL93_SHIFT (8U) +#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ + +/*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ +#define XBARA_SEL47_SEL94_MASK (0x7FU) +#define XBARA_SEL47_SEL94_SHIFT (0U) +#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) +#define XBARA_SEL47_SEL95_MASK (0x7F00U) +#define XBARA_SEL47_SEL95_SHIFT (8U) +#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ + +/*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ +#define XBARA_SEL48_SEL96_MASK (0x7FU) +#define XBARA_SEL48_SEL96_SHIFT (0U) +#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) +#define XBARA_SEL48_SEL97_MASK (0x7F00U) +#define XBARA_SEL48_SEL97_SHIFT (8U) +#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ + +/*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ +#define XBARA_SEL49_SEL98_MASK (0x7FU) +#define XBARA_SEL49_SEL98_SHIFT (0U) +#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) +#define XBARA_SEL49_SEL99_MASK (0x7F00U) +#define XBARA_SEL49_SEL99_SHIFT (8U) +#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ + +/*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ +#define XBARA_SEL50_SEL100_MASK (0x7FU) +#define XBARA_SEL50_SEL100_SHIFT (0U) +#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) +#define XBARA_SEL50_SEL101_MASK (0x7F00U) +#define XBARA_SEL50_SEL101_SHIFT (8U) +#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ + +/*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ +#define XBARA_SEL51_SEL102_MASK (0x7FU) +#define XBARA_SEL51_SEL102_SHIFT (0U) +#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) +#define XBARA_SEL51_SEL103_MASK (0x7F00U) +#define XBARA_SEL51_SEL103_SHIFT (8U) +#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ + +/*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ +#define XBARA_SEL52_SEL104_MASK (0x7FU) +#define XBARA_SEL52_SEL104_SHIFT (0U) +#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) +#define XBARA_SEL52_SEL105_MASK (0x7F00U) +#define XBARA_SEL52_SEL105_SHIFT (8U) +#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ + +/*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ +#define XBARA_SEL53_SEL106_MASK (0x7FU) +#define XBARA_SEL53_SEL106_SHIFT (0U) +#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) +#define XBARA_SEL53_SEL107_MASK (0x7F00U) +#define XBARA_SEL53_SEL107_SHIFT (8U) +#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ + +/*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ +#define XBARA_SEL54_SEL108_MASK (0x7FU) +#define XBARA_SEL54_SEL108_SHIFT (0U) +#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) +#define XBARA_SEL54_SEL109_MASK (0x7F00U) +#define XBARA_SEL54_SEL109_SHIFT (8U) +#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ + +/*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ +#define XBARA_SEL55_SEL110_MASK (0x7FU) +#define XBARA_SEL55_SEL110_SHIFT (0U) +#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) +#define XBARA_SEL55_SEL111_MASK (0x7F00U) +#define XBARA_SEL55_SEL111_SHIFT (8U) +#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ + +/*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ +#define XBARA_SEL56_SEL112_MASK (0x7FU) +#define XBARA_SEL56_SEL112_SHIFT (0U) +#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) +#define XBARA_SEL56_SEL113_MASK (0x7F00U) +#define XBARA_SEL56_SEL113_SHIFT (8U) +#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ + +/*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ +#define XBARA_SEL57_SEL114_MASK (0x7FU) +#define XBARA_SEL57_SEL114_SHIFT (0U) +#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) +#define XBARA_SEL57_SEL115_MASK (0x7F00U) +#define XBARA_SEL57_SEL115_SHIFT (8U) +#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ + +/*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ +#define XBARA_SEL58_SEL116_MASK (0x7FU) +#define XBARA_SEL58_SEL116_SHIFT (0U) +#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) +#define XBARA_SEL58_SEL117_MASK (0x7F00U) +#define XBARA_SEL58_SEL117_SHIFT (8U) +#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ + +/*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ +#define XBARA_SEL59_SEL118_MASK (0x7FU) +#define XBARA_SEL59_SEL118_SHIFT (0U) +#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) +#define XBARA_SEL59_SEL119_MASK (0x7F00U) +#define XBARA_SEL59_SEL119_SHIFT (8U) +#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ + +/*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ +#define XBARA_SEL60_SEL120_MASK (0x7FU) +#define XBARA_SEL60_SEL120_SHIFT (0U) +#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) +#define XBARA_SEL60_SEL121_MASK (0x7F00U) +#define XBARA_SEL60_SEL121_SHIFT (8U) +#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ + +/*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ +#define XBARA_SEL61_SEL122_MASK (0x7FU) +#define XBARA_SEL61_SEL122_SHIFT (0U) +#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) +#define XBARA_SEL61_SEL123_MASK (0x7F00U) +#define XBARA_SEL61_SEL123_SHIFT (8U) +#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ + +/*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ +#define XBARA_SEL62_SEL124_MASK (0x7FU) +#define XBARA_SEL62_SEL124_SHIFT (0U) +#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) +#define XBARA_SEL62_SEL125_MASK (0x7F00U) +#define XBARA_SEL62_SEL125_SHIFT (8U) +#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ + +/*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ +#define XBARA_SEL63_SEL126_MASK (0x7FU) +#define XBARA_SEL63_SEL126_SHIFT (0U) +#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) +#define XBARA_SEL63_SEL127_MASK (0x7F00U) +#define XBARA_SEL63_SEL127_SHIFT (8U) +#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ + +/*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ +#define XBARA_SEL64_SEL128_MASK (0x7FU) +#define XBARA_SEL64_SEL128_SHIFT (0U) +#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) +#define XBARA_SEL64_SEL129_MASK (0x7F00U) +#define XBARA_SEL64_SEL129_SHIFT (8U) +#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ + +/*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ +#define XBARA_SEL65_SEL130_MASK (0x7FU) +#define XBARA_SEL65_SEL130_SHIFT (0U) +#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) +#define XBARA_SEL65_SEL131_MASK (0x7F00U) +#define XBARA_SEL65_SEL131_SHIFT (8U) +#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ + +/*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ +#define XBARA_CTRL0_DEN0_MASK (0x1U) +#define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) +#define XBARA_CTRL0_IEN0_MASK (0x2U) +#define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) +#define XBARA_CTRL0_EDGE0_MASK (0xCU) +#define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ +#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) +#define XBARA_CTRL0_STS0_MASK (0x10U) +#define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ +#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) +#define XBARA_CTRL0_DEN1_MASK (0x100U) +#define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) +#define XBARA_CTRL0_IEN1_MASK (0x200U) +#define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) +#define XBARA_CTRL0_EDGE1_MASK (0xC00U) +#define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ +#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) +#define XBARA_CTRL0_STS1_MASK (0x1000U) +#define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ +#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ + +/*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ +#define XBARA_CTRL1_DEN2_MASK (0x1U) +#define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) +#define XBARA_CTRL1_IEN2_MASK (0x2U) +#define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) +#define XBARA_CTRL1_EDGE2_MASK (0xCU) +#define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ +#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) +#define XBARA_CTRL1_STS2_MASK (0x10U) +#define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ +#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) +#define XBARA_CTRL1_DEN3_MASK (0x100U) +#define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) +#define XBARA_CTRL1_IEN3_MASK (0x200U) +#define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) +#define XBARA_CTRL1_EDGE3_MASK (0xC00U) +#define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ +#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) +#define XBARA_CTRL1_STS3_MASK (0x1000U) +#define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ +#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARA_Register_Masks */ + + +/* XBARA - Peripheral instance base addresses */ +/** Peripheral XBARA base address */ +#define XBARA_BASE (0x403BC000u) +/** Peripheral XBARA base pointer */ +#define XBARA ((XBARA_Type *)XBARA_BASE) +/** Array initializer of XBARA peripheral base addresses */ +#define XBARA_BASE_ADDRS { XBARA_BASE } +/** Array initializer of XBARA peripheral base pointers */ +#define XBARA_BASE_PTRS { XBARA } + +/*! + * @} + */ /* end of group XBARA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer + * @{ + */ + +/** XBARB - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ +} XBARB_Type; + +/* ---------------------------------------------------------------------------- + -- XBARB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Register_Masks XBARB Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ +#define XBARB_SEL0_SEL0_MASK (0x3FU) +#define XBARB_SEL0_SEL0_SHIFT (0U) +#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) +#define XBARB_SEL0_SEL1_MASK (0x3F00U) +#define XBARB_SEL0_SEL1_SHIFT (8U) +#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ +#define XBARB_SEL1_SEL2_MASK (0x3FU) +#define XBARB_SEL1_SEL2_SHIFT (0U) +#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) +#define XBARB_SEL1_SEL3_MASK (0x3F00U) +#define XBARB_SEL1_SEL3_SHIFT (8U) +#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ +#define XBARB_SEL2_SEL4_MASK (0x3FU) +#define XBARB_SEL2_SEL4_SHIFT (0U) +#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) +#define XBARB_SEL2_SEL5_MASK (0x3F00U) +#define XBARB_SEL2_SEL5_SHIFT (8U) +#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ +#define XBARB_SEL3_SEL6_MASK (0x3FU) +#define XBARB_SEL3_SEL6_SHIFT (0U) +#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) +#define XBARB_SEL3_SEL7_MASK (0x3F00U) +#define XBARB_SEL3_SEL7_SHIFT (8U) +#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ +#define XBARB_SEL4_SEL8_MASK (0x3FU) +#define XBARB_SEL4_SEL8_SHIFT (0U) +#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) +#define XBARB_SEL4_SEL9_MASK (0x3F00U) +#define XBARB_SEL4_SEL9_SHIFT (8U) +#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ +#define XBARB_SEL5_SEL10_MASK (0x3FU) +#define XBARB_SEL5_SEL10_SHIFT (0U) +#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) +#define XBARB_SEL5_SEL11_MASK (0x3F00U) +#define XBARB_SEL5_SEL11_SHIFT (8U) +#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ +#define XBARB_SEL6_SEL12_MASK (0x3FU) +#define XBARB_SEL6_SEL12_SHIFT (0U) +#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) +#define XBARB_SEL6_SEL13_MASK (0x3F00U) +#define XBARB_SEL6_SEL13_SHIFT (8U) +#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ +#define XBARB_SEL7_SEL14_MASK (0x3FU) +#define XBARB_SEL7_SEL14_SHIFT (0U) +#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) +#define XBARB_SEL7_SEL15_MASK (0x3F00U) +#define XBARB_SEL7_SEL15_SHIFT (8U) +#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARB_Register_Masks */ + + +/* XBARB - Peripheral instance base addresses */ +/** Peripheral XBARB base address */ +#define XBARB_BASE (0x403C0000u) +/** Peripheral XBARB base pointer */ +#define XBARB ((XBARB_Type *)XBARB_BASE) +/** Array initializer of XBARB peripheral base addresses */ +#define XBARB_BASE_ADDRS { XBARB_BASE } +/** Array initializer of XBARB peripheral base pointers */ +#define XBARB_BASE_PTRS { XBARB } + +/*! + * @} + */ /* end of group XBARB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + uint8_t RESERVED_1[272]; + __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ + uint8_t RESERVED_2[32]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x400D8000u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMXRT1015_H_ */ + diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.xml b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.xml new file mode 100644 index 0000000000000..dccf918064c7a --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.xml @@ -0,0 +1,130321 @@ + + + nxp.com + MIMXRT1015 + 1.0 + MIMXRT1015DAF5A + +Copyright 2016-2019 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM7 + r0p1 + little + true + true + true + 4 + false + + 8 + 32 + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + AIPSTZ + 0x4007C000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT5 + Master 5 Priviledge, Buffer, Read, Write Control. + 8 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 16 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 20 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 24 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 28 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC6 + Off-platform Peripheral Access Control 6 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC5 + Off-platform Peripheral Access Control 5 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC4 + Off-platform Peripheral Access Control 4 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC3 + Off-platform Peripheral Access Control 3 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC2 + Off-platform Peripheral Access Control 2 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC1 + Off-platform Peripheral Access Control 1 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC0 + Off-platform Peripheral Access Control 0 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC14 + Off-platform Peripheral Access Control 14 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC13 + Off-platform Peripheral Access Control 13 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC12 + Off-platform Peripheral Access Control 12 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC11 + Off-platform Peripheral Access Control 11 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC10 + Off-platform Peripheral Access Control 10 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC9 + Off-platform Peripheral Access Control 9 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC8 + Off-platform Peripheral Access Control 8 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC22 + Off-platform Peripheral Access Control 22 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC21 + Off-platform Peripheral Access Control 21 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC20 + Off-platform Peripheral Access Control 20 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC19 + Off-platform Peripheral Access Control 19 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC18 + Off-platform Peripheral Access Control 18 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC17 + Off-platform Peripheral Access Control 17 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC16 + Off-platform Peripheral Access Control 16 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC30 + Off-platform Peripheral Access Control 30 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC29 + Off-platform Peripheral Access Control 29 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC28 + Off-platform Peripheral Access Control 28 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC27 + Off-platform Peripheral Access Control 27 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC26 + Off-platform Peripheral Access Control 26 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC25 + Off-platform Peripheral Access Control 25 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC24 + Off-platform Peripheral Access Control 24 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC32 + Off-platform Peripheral Access Control 32 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x4017C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x4027C000 + + 0 + 0x54 + registers + + + + AIPSTZ4 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ4_ + 0x4037C000 + + 0 + 0x54 + registers + + + + DCDC + DCDC + DCDC + 0x40080000 + + 0 + 0x1000 + registers + + + DCDC + 69 + + + + REG0 + DCDC Register 0 + 0 + 32 + read-write + 0x14030111 + 0xFFFFFFFF + + + PWD_ZCD + power down the zero cross detection function for discontinuous conductor mode + 0 + 1 + read-write + + + DISABLE_AUTO_CLK_SWITCH + Disable automatic clock switch from internal osc to xtal clock. + 1 + 1 + read-write + + + SEL_CLK + select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set. + 2 + 1 + read-write + + + PWD_OSC_INT + Power down internal osc. Only set this bit, when 24 MHz crystal osc is available + 3 + 1 + read-write + + + PWD_CUR_SNS_CMP + The power down signal of the current detector. + 4 + 1 + read-write + + + CUR_SNS_THRSH + Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert + 5 + 3 + read-write + + + PWD_OVERCUR_DET + power down overcurrent detection comparator + 8 + 1 + read-write + + + OVERCUR_TRIG_ADJ + The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0 + 9 + 2 + read-write + + + PWD_CMP_BATT_DET + set to "1" to power down the low voltage detection comparator + 11 + 1 + read-write + + + ADJ_POSLIMIT_BUCK + adjust value to poslimit_buck register + 12 + 4 + read-write + + + EN_LP_OVERLOAD_SNS + enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically + 16 + 1 + read-write + + + PWD_HIGH_VOLT_DET + power down overvoltage detection comparator + 17 + 1 + read-write + + + LP_OVERLOAD_THRSH + the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode + 18 + 2 + read-write + + + LP_OVERLOAD_FREQ_SEL + the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle + 20 + 1 + read-write + + + LP_HIGH_HYS + Adjust hysteretic value in low power from 12.5mV to 25mV + 21 + 1 + read-write + + + PWD_CMP_OFFSET + power down output range comparator + 26 + 1 + read-write + + + XTALOK_DISABLE + 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit + 27 + 1 + read-write + + + CURRENT_ALERT_RESET + reset current alert signal + 28 + 1 + read-write + + + XTAL_24M_OK + set to 1 to switch internal ring osc to xtal 24M + 29 + 1 + read-write + + + STS_DC_OK + Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling + 31 + 1 + read-only + + + + + REG1 + DCDC Register 1 + 0x4 + 32 + read-write + 0x111BA29C + 0xFFFFFFFF + + + REG_FBK_SEL + select the feedback point of the internal regulator + 7 + 2 + read-write + + + REG_RLOAD_SW + control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor + 9 + 1 + read-write + + + LP_CMP_ISRC_SEL + set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA + 12 + 2 + read-write + + + LOOPCTRL_HST_THRESH + increase the threshold detection for common mode analog comparator + 21 + 1 + read-write + + + LOOPCTRL_EN_HYST + Enable hysteresis in switching converter common mode analog comparators + 23 + 1 + read-write + + + VBG_TRIM + trim bandgap voltage + 24 + 5 + read-write + + + + + REG2 + DCDC Register 2 + 0x8 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + LOOPCTRL_DC_C + Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response + 0 + 2 + read-write + + + LOOPCTRL_DC_R + Magnitude of proportional control parameter in the switching DC-DC converter control loop. + 2 + 4 + read-write + + + LOOPCTRL_DC_FF + Two's complement feed forward step in duty cycle in the switching DC-DC converter + 6 + 3 + read-write + + + LOOPCTRL_EN_RCSCALE + Enable analog circuit of DC-DC converter to respond faster under transient load conditions. + 9 + 3 + read-write + + + LOOPCTRL_RCSCALE_THRSH + Increase the threshold detection for RC scale circuit. + 12 + 1 + read-write + + + LOOPCTRL_HYST_SIGN + Invert the sign of the hysteresis in DC-DC analog comparators. + 13 + 1 + read-write + + + BATTMONITOR_EN_BATADJ + This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field + 15 + 1 + read-write + + + DISABLE_PULSE_SKIP + Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in + 27 + 1 + read-write + + + DCM_SET_CTRL + Set high to improve the transition from heavy load to light load + 28 + 1 + read-write + + + + + REG3 + DCDC Register 3 + 0xC + 32 + read-write + 0x10E + 0xFFFFFFFF + + + TRG + Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V + 0 + 5 + read-write + + + TARGET_LP + Target value of standby (low power) mode 0x0: 0 + 8 + 3 + read-write + + + MINPWR_DC_HALFCLK + Set DCDC clock to half freqeuncy for continuous mode + 24 + 1 + read-write + + + MISC_DELAY_TIMING + Ajust delay to reduce ground noise + 27 + 1 + read-write + + + MISC_DISABLEFET_LOGIC + Reserved + 28 + 1 + read-write + + + DISABLE_STEP + Disable stepping for the output VDD_SOC of DCDC + 30 + 1 + read-write + + + + + + + PIT + PIT + PIT + 0x40084000 + + 0 + 0x140 + registers + + + PIT + 122 + + + + MCR + PIT Module Control Register + 0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + FRZ + Freeze + 0 + 1 + read-write + + + FRZ_0 + Timers continue to run in Debug mode. + 0 + + + FRZ_1 + Timers are stopped in Debug mode. + 0x1 + + + + + MDIS + Module Disable - (PIT section) + 1 + 1 + read-write + + + MDIS_0 + Clock for standard PIT timers is enabled. + 0 + + + MDIS_1 + Clock for standard PIT timers is disabled. + 0x1 + + + + + + + LTMR64H + PIT Upper Lifetime Timer Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTH + Life Timer value + 0 + 32 + read-only + + + + + LTMR64L + PIT Lower Lifetime Timer Register + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTL + Life Timer value + 0 + 32 + read-only + + + + + 4 + 0x10 + TIMER[%s] + no description available + 0x100 + + LDVAL + Timer Load Value Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 24 + read-write + + + + + CVAL + Current Timer Value Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL + Timer Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + TEN_0 + Timer n is disabled. + 0 + + + TEN_1 + Timer n is enabled. + 0x1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + TIE_0 + Interrupt requests from Timer n are disabled. + 0 + + + TIE_1 + Interrupt will be requested whenever TIF is set. + 0x1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + CHN_0 + Timer is not chained. + 0 + + + CHN_1 + Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + 0x1 + + + + + + + TFLG + Timer Flag Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + oneToClear + + + TIF_0 + Timeout has not yet occurred. + 0 + + + TIF_1 + Timeout has occurred. + 0x1 + + + + + + + + + + IOMUXC_SNVS_GPR + IOMUXC + IOMUXC_SNVS_GPR + IOMUXC_SNVS_GPR_ + 0x400A4000 + + 0 + 0x10 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + LPSR_MODE_ENABLE + Set to enable LPSR mode. + 0 + 1 + read-write + + + DCDC_STATUS_CAPT_CLR + DCDC captured status clear + 1 + 1 + read-write + + + POR_PULL_TYPE + POR_B pad control + 2 + 2 + read-write + + + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. + 16 + 1 + read-only + + + DCDC_OVER_CUR + DCDC output over current alert + 17 + 1 + read-only + + + DCDC_OVER_VOL + DCDC output over voltage alert + 18 + 1 + read-only + + + DCDC_STS_DC_OK + DCDC status OK + 19 + 1 + read-only + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x400A8000 + + 0 + 0x20 + registers + + + + SW_MUX_CTL_PAD_PMIC_ON_REQ + SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_ON_REQ + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0xC + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x10 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x14 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_ON_REQ + SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register + 0x1C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + + + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR_ + 0x400AC000 + + 0 + 0x68 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SAI1_MCLK1_SEL + SAI1 MCLK1 source select + 0 + 3 + read-write + + + SAI1_MCLK1_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK1_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK1_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK1_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK1_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK1_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK2_SEL + SAI1 MCLK2 source select + 3 + 3 + read-write + + + SAI1_MCLK2_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK2_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK2_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK2_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK2_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK2_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK3_SEL + SAI1 MCLK3 source select + 6 + 2 + read-write + + + SAI1_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI1_MCLK3_SEL_1 + SPDIF_EXT_CLK + 0x1 + + + SAI1_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI1_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI2_MCLK3_SEL + SAI2 MCLK3 source select + 8 + 2 + read-write + + + SAI2_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI2_MCLK3_SEL_1 + SPDIF_EXT_CLK + 0x1 + + + SAI2_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI2_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI3_MCLK3_SEL + SAI3 MCLK3 source select + 10 + 2 + read-write + + + SAI3_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI3_MCLK3_SEL_1 + SPDIF_EXT_CLK + 0x1 + + + SAI3_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI3_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + GINT + Global Interrupt + 12 + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted. + 0 + + + GINT_1 + Global interrupt request is asserted. + 0x1 + + + + + SAI1_MCLK_DIR + sai1.MCLK signal direction control + 19 + 1 + read-write + + + SAI1_MCLK_DIR_0 + sai1.MCLK is input signal + 0 + + + SAI1_MCLK_DIR_1 + sai1.MCLK is output signal + 0x1 + + + + + SAI2_MCLK_DIR + sai2.MCLK signal direction control + 20 + 1 + read-write + + + SAI2_MCLK_DIR_0 + sai2.MCLK is input signal + 0 + + + SAI2_MCLK_DIR_1 + sai2.MCLK is output signal + 0x1 + + + + + SAI3_MCLK_DIR + sai3.MCLK signal direction control + 21 + 1 + read-write + + + SAI3_MCLK_DIR_0 + sai3.MCLK is input signal + 0 + + + SAI3_MCLK_DIR_1 + sai3.MCLK is output signal + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 22 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response + 0x1 + + + + + CM7_FORCE_HCLK_EN + ARM CM7 platform AHB clock enable + 31 + 1 + read-write + + + CM7_FORCE_HCLK_EN_0 + AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible. + 0 + + + CM7_FORCE_HCLK_EN_1 + AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible. + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + L2_MEM_EN_POWERSAVING + Enable power saving features on L2 memory + 12 + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + Enters power saving mode only when chip is in SUSPEND mode + 0 + + + L2_MEM_EN_POWERSAVING_1 + Controlled by L2_MEM_DEEPSLEEP bitfield + 0x1 + + + + + RAM_AUTO_CLK_GATING_EN + Automatically gate off RAM clock when RAM is not accessed. + 13 + 1 + read-write + + + RAM_AUTO_CLK_GATING_EN_0 + disable automatically gate off RAM clock + 0 + + + RAM_AUTO_CLK_GATING_EN_1 + enable automatically gate off RAM clock + 0x1 + + + + + L2_MEM_DEEPSLEEP + This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low + 14 + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode) + 0 + + + L2_MEM_DEEPSLEEP_1 + Force memory into deep sleep mode (OCRAM in power saving mode) + 0x1 + + + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 16 + 8 + read-write + + + DIVIDE_1 + mclk frequency = 1/1 * hmclk frequency + 0 + + + DIVIDE_2 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + DIVIDE_3 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + DIVIDE_4 + mclk frequency = 1/4 * hmclk frequency + 0x3 + + + DIVIDE_5 + mclk frequency = 1/5 * hmclk frequency + 0x4 + + + DIVIDE_6 + mclk frequency = 1/6 * hmclk frequency + 0x5 + + + DIVIDE_7 + mclk frequency = 1/7 * hmclk frequency + 0x6 + + + DIVIDE_8 + mclk frequency = 1/8 * hmclk frequency + 0x7 + + + DIVIDE_9 + mclk frequency = 1/9 * hmclk frequency + 0x8 + + + DIVIDE_10 + mclk frequency = 1/10 * hmclk frequency + 0x9 + + + DIVIDE_11 + mclk frequency = 1/11 * hmclk frequency + 0xA + + + DIVIDE_12 + mclk frequency = 1/12 * hmclk frequency + 0xB + + + DIVIDE_13 + mclk frequency = 1/13 * hmclk frequency + 0xC + + + DIVIDE_14 + mclk frequency = 1/14 * hmclk frequency + 0xD + + + DIVIDE_15 + mclk frequency = 1/15 * hmclk frequency + 0xE + + + DIVIDE_16 + mclk frequency = 1/16 * hmclk frequency + 0xF + + + DIVIDE_17 + mclk frequency = 1/17 * hmclk frequency + 0x10 + + + DIVIDE_18 + mclk frequency = 1/18 * hmclk frequency + 0x11 + + + DIVIDE_19 + mclk frequency = 1/19 * hmclk frequency + 0x12 + + + DIVIDE_20 + mclk frequency = 1/20 * hmclk frequency + 0x13 + + + DIVIDE_21 + mclk frequency = 1/21 * hmclk frequency + 0x14 + + + DIVIDE_22 + mclk frequency = 1/22 * hmclk frequency + 0x15 + + + DIVIDE_23 + mclk frequency = 1/23 * hmclk frequency + 0x16 + + + DIVIDE_24 + mclk frequency = 1/24 * hmclk frequency + 0x17 + + + DIVIDE_25 + mclk frequency = 1/25 * hmclk frequency + 0x18 + + + DIVIDE_26 + mclk frequency = 1/26 * hmclk frequency + 0x19 + + + DIVIDE_27 + mclk frequency = 1/27 * hmclk frequency + 0x1A + + + DIVIDE_28 + mclk frequency = 1/28 * hmclk frequency + 0x1B + + + DIVIDE_29 + mclk frequency = 1/29 * hmclk frequency + 0x1C + + + DIVIDE_30 + mclk frequency = 1/30 * hmclk frequency + 0x1D + + + DIVIDE_31 + mclk frequency = 1/31 * hmclk frequency + 0x1E + + + DIVIDE_32 + mclk frequency = 1/32 * hmclk frequency + 0x1F + + + DIVIDE_33 + mclk frequency = 1/33 * hmclk frequency + 0x20 + + + DIVIDE_34 + mclk frequency = 1/34 * hmclk frequency + 0x21 + + + DIVIDE_35 + mclk frequency = 1/35 * hmclk frequency + 0x22 + + + DIVIDE_36 + mclk frequency = 1/36 * hmclk frequency + 0x23 + + + DIVIDE_37 + mclk frequency = 1/37 * hmclk frequency + 0x24 + + + DIVIDE_38 + mclk frequency = 1/38 * hmclk frequency + 0x25 + + + DIVIDE_39 + mclk frequency = 1/39 * hmclk frequency + 0x26 + + + DIVIDE_40 + mclk frequency = 1/40 * hmclk frequency + 0x27 + + + DIVIDE_41 + mclk frequency = 1/41 * hmclk frequency + 0x28 + + + DIVIDE_42 + mclk frequency = 1/42 * hmclk frequency + 0x29 + + + DIVIDE_43 + mclk frequency = 1/43 * hmclk frequency + 0x2A + + + DIVIDE_44 + mclk frequency = 1/44 * hmclk frequency + 0x2B + + + DIVIDE_45 + mclk frequency = 1/45 * hmclk frequency + 0x2C + + + DIVIDE_46 + mclk frequency = 1/46 * hmclk frequency + 0x2D + + + DIVIDE_47 + mclk frequency = 1/47 * hmclk frequency + 0x2E + + + DIVIDE_48 + mclk frequency = 1/48 * hmclk frequency + 0x2F + + + DIVIDE_49 + mclk frequency = 1/49 * hmclk frequency + 0x30 + + + DIVIDE_50 + mclk frequency = 1/50 * hmclk frequency + 0x31 + + + DIVIDE_51 + mclk frequency = 1/51 * hmclk frequency + 0x32 + + + DIVIDE_52 + mclk frequency = 1/52 * hmclk frequency + 0x33 + + + DIVIDE_53 + mclk frequency = 1/53 * hmclk frequency + 0x34 + + + DIVIDE_54 + mclk frequency = 1/54 * hmclk frequency + 0x35 + + + DIVIDE_55 + mclk frequency = 1/55 * hmclk frequency + 0x36 + + + DIVIDE_56 + mclk frequency = 1/56 * hmclk frequency + 0x37 + + + DIVIDE_57 + mclk frequency = 1/57 * hmclk frequency + 0x38 + + + DIVIDE_58 + mclk frequency = 1/58 * hmclk frequency + 0x39 + + + DIVIDE_59 + mclk frequency = 1/59 * hmclk frequency + 0x3A + + + DIVIDE_60 + mclk frequency = 1/60 * hmclk frequency + 0x3B + + + DIVIDE_61 + mclk frequency = 1/61 * hmclk frequency + 0x3C + + + DIVIDE_62 + mclk frequency = 1/62 * hmclk frequency + 0x3D + + + DIVIDE_63 + mclk frequency = 1/63 * hmclk frequency + 0x3E + + + DIVIDE_64 + mclk frequency = 1/64 * hmclk frequency + 0x3F + + + DIVIDE_65 + mclk frequency = 1/65 * hmclk frequency + 0x40 + + + DIVIDE_66 + mclk frequency = 1/66 * hmclk frequency + 0x41 + + + DIVIDE_67 + mclk frequency = 1/67 * hmclk frequency + 0x42 + + + DIVIDE_68 + mclk frequency = 1/68 * hmclk frequency + 0x43 + + + DIVIDE_69 + mclk frequency = 1/69 * hmclk frequency + 0x44 + + + DIVIDE_70 + mclk frequency = 1/70 * hmclk frequency + 0x45 + + + DIVIDE_71 + mclk frequency = 1/71 * hmclk frequency + 0x46 + + + DIVIDE_72 + mclk frequency = 1/72 * hmclk frequency + 0x47 + + + DIVIDE_73 + mclk frequency = 1/73 * hmclk frequency + 0x48 + + + DIVIDE_74 + mclk frequency = 1/74 * hmclk frequency + 0x49 + + + DIVIDE_75 + mclk frequency = 1/75 * hmclk frequency + 0x4A + + + DIVIDE_76 + mclk frequency = 1/76 * hmclk frequency + 0x4B + + + DIVIDE_77 + mclk frequency = 1/77 * hmclk frequency + 0x4C + + + DIVIDE_78 + mclk frequency = 1/78 * hmclk frequency + 0x4D + + + DIVIDE_79 + mclk frequency = 1/79 * hmclk frequency + 0x4E + + + DIVIDE_80 + mclk frequency = 1/80 * hmclk frequency + 0x4F + + + DIVIDE_81 + mclk frequency = 1/81 * hmclk frequency + 0x50 + + + DIVIDE_82 + mclk frequency = 1/82 * hmclk frequency + 0x51 + + + DIVIDE_83 + mclk frequency = 1/83 * hmclk frequency + 0x52 + + + DIVIDE_84 + mclk frequency = 1/84 * hmclk frequency + 0x53 + + + DIVIDE_85 + mclk frequency = 1/85 * hmclk frequency + 0x54 + + + DIVIDE_86 + mclk frequency = 1/86 * hmclk frequency + 0x55 + + + DIVIDE_87 + mclk frequency = 1/87 * hmclk frequency + 0x56 + + + DIVIDE_88 + mclk frequency = 1/88 * hmclk frequency + 0x57 + + + DIVIDE_89 + mclk frequency = 1/89 * hmclk frequency + 0x58 + + + DIVIDE_90 + mclk frequency = 1/90 * hmclk frequency + 0x59 + + + DIVIDE_91 + mclk frequency = 1/91 * hmclk frequency + 0x5A + + + DIVIDE_92 + mclk frequency = 1/92 * hmclk frequency + 0x5B + + + DIVIDE_93 + mclk frequency = 1/93 * hmclk frequency + 0x5C + + + DIVIDE_94 + mclk frequency = 1/94 * hmclk frequency + 0x5D + + + DIVIDE_95 + mclk frequency = 1/95 * hmclk frequency + 0x5E + + + DIVIDE_96 + mclk frequency = 1/96 * hmclk frequency + 0x5F + + + DIVIDE_97 + mclk frequency = 1/97 * hmclk frequency + 0x60 + + + DIVIDE_98 + mclk frequency = 1/98 * hmclk frequency + 0x61 + + + DIVIDE_99 + mclk frequency = 1/99 * hmclk frequency + 0x62 + + + DIVIDE_100 + mclk frequency = 1/100 * hmclk frequency + 0x63 + + + DIVIDE_101 + mclk frequency = 1/101 * hmclk frequency + 0x64 + + + DIVIDE_102 + mclk frequency = 1/102 * hmclk frequency + 0x65 + + + DIVIDE_103 + mclk frequency = 1/103 * hmclk frequency + 0x66 + + + DIVIDE_104 + mclk frequency = 1/104 * hmclk frequency + 0x67 + + + DIVIDE_105 + mclk frequency = 1/105 * hmclk frequency + 0x68 + + + DIVIDE_106 + mclk frequency = 1/106 * hmclk frequency + 0x69 + + + DIVIDE_107 + mclk frequency = 1/107 * hmclk frequency + 0x6A + + + DIVIDE_108 + mclk frequency = 1/108 * hmclk frequency + 0x6B + + + DIVIDE_109 + mclk frequency = 1/109 * hmclk frequency + 0x6C + + + DIVIDE_110 + mclk frequency = 1/110 * hmclk frequency + 0x6D + + + DIVIDE_111 + mclk frequency = 1/111 * hmclk frequency + 0x6E + + + DIVIDE_112 + mclk frequency = 1/112 * hmclk frequency + 0x6F + + + DIVIDE_113 + mclk frequency = 1/113 * hmclk frequency + 0x70 + + + DIVIDE_114 + mclk frequency = 1/114 * hmclk frequency + 0x71 + + + DIVIDE_115 + mclk frequency = 1/115 * hmclk frequency + 0x72 + + + DIVIDE_116 + mclk frequency = 1/116 * hmclk frequency + 0x73 + + + DIVIDE_117 + mclk frequency = 1/117 * hmclk frequency + 0x74 + + + DIVIDE_118 + mclk frequency = 1/118 * hmclk frequency + 0x75 + + + DIVIDE_119 + mclk frequency = 1/119 * hmclk frequency + 0x76 + + + DIVIDE_120 + mclk frequency = 1/120 * hmclk frequency + 0x77 + + + DIVIDE_121 + mclk frequency = 1/121 * hmclk frequency + 0x78 + + + DIVIDE_122 + mclk frequency = 1/122 * hmclk frequency + 0x79 + + + DIVIDE_123 + mclk frequency = 1/123 * hmclk frequency + 0x7A + + + DIVIDE_124 + mclk frequency = 1/124 * hmclk frequency + 0x7B + + + DIVIDE_125 + mclk frequency = 1/125 * hmclk frequency + 0x7C + + + DIVIDE_126 + mclk frequency = 1/126 * hmclk frequency + 0x7D + + + DIVIDE_127 + mclk frequency = 1/127 * hmclk frequency + 0x7E + + + DIVIDE_128 + mclk frequency = 1/128 * hmclk frequency + 0x7F + + + DIVIDE_129 + mclk frequency = 1/129 * hmclk frequency + 0x80 + + + DIVIDE_130 + mclk frequency = 1/130 * hmclk frequency + 0x81 + + + DIVIDE_131 + mclk frequency = 1/131 * hmclk frequency + 0x82 + + + DIVIDE_132 + mclk frequency = 1/132 * hmclk frequency + 0x83 + + + DIVIDE_133 + mclk frequency = 1/133 * hmclk frequency + 0x84 + + + DIVIDE_134 + mclk frequency = 1/134 * hmclk frequency + 0x85 + + + DIVIDE_135 + mclk frequency = 1/135 * hmclk frequency + 0x86 + + + DIVIDE_136 + mclk frequency = 1/136 * hmclk frequency + 0x87 + + + DIVIDE_137 + mclk frequency = 1/137 * hmclk frequency + 0x88 + + + DIVIDE_138 + mclk frequency = 1/138 * hmclk frequency + 0x89 + + + DIVIDE_139 + mclk frequency = 1/139 * hmclk frequency + 0x8A + + + DIVIDE_140 + mclk frequency = 1/140 * hmclk frequency + 0x8B + + + DIVIDE_141 + mclk frequency = 1/141 * hmclk frequency + 0x8C + + + DIVIDE_142 + mclk frequency = 1/142 * hmclk frequency + 0x8D + + + DIVIDE_143 + mclk frequency = 1/143 * hmclk frequency + 0x8E + + + DIVIDE_144 + mclk frequency = 1/144 * hmclk frequency + 0x8F + + + DIVIDE_145 + mclk frequency = 1/145 * hmclk frequency + 0x90 + + + DIVIDE_146 + mclk frequency = 1/146 * hmclk frequency + 0x91 + + + DIVIDE_147 + mclk frequency = 1/147 * hmclk frequency + 0x92 + + + DIVIDE_148 + mclk frequency = 1/148 * hmclk frequency + 0x93 + + + DIVIDE_149 + mclk frequency = 1/149 * hmclk frequency + 0x94 + + + DIVIDE_150 + mclk frequency = 1/150 * hmclk frequency + 0x95 + + + DIVIDE_151 + mclk frequency = 1/151 * hmclk frequency + 0x96 + + + DIVIDE_152 + mclk frequency = 1/152 * hmclk frequency + 0x97 + + + DIVIDE_153 + mclk frequency = 1/153 * hmclk frequency + 0x98 + + + DIVIDE_154 + mclk frequency = 1/154 * hmclk frequency + 0x99 + + + DIVIDE_155 + mclk frequency = 1/155 * hmclk frequency + 0x9A + + + DIVIDE_156 + mclk frequency = 1/156 * hmclk frequency + 0x9B + + + DIVIDE_157 + mclk frequency = 1/157 * hmclk frequency + 0x9C + + + DIVIDE_158 + mclk frequency = 1/158 * hmclk frequency + 0x9D + + + DIVIDE_159 + mclk frequency = 1/159 * hmclk frequency + 0x9E + + + DIVIDE_160 + mclk frequency = 1/160 * hmclk frequency + 0x9F + + + DIVIDE_161 + mclk frequency = 1/161 * hmclk frequency + 0xA0 + + + DIVIDE_162 + mclk frequency = 1/162 * hmclk frequency + 0xA1 + + + DIVIDE_163 + mclk frequency = 1/163 * hmclk frequency + 0xA2 + + + DIVIDE_164 + mclk frequency = 1/164 * hmclk frequency + 0xA3 + + + DIVIDE_165 + mclk frequency = 1/165 * hmclk frequency + 0xA4 + + + DIVIDE_166 + mclk frequency = 1/166 * hmclk frequency + 0xA5 + + + DIVIDE_167 + mclk frequency = 1/167 * hmclk frequency + 0xA6 + + + DIVIDE_168 + mclk frequency = 1/168 * hmclk frequency + 0xA7 + + + DIVIDE_169 + mclk frequency = 1/169 * hmclk frequency + 0xA8 + + + DIVIDE_170 + mclk frequency = 1/170 * hmclk frequency + 0xA9 + + + DIVIDE_171 + mclk frequency = 1/171 * hmclk frequency + 0xAA + + + DIVIDE_172 + mclk frequency = 1/172 * hmclk frequency + 0xAB + + + DIVIDE_173 + mclk frequency = 1/173 * hmclk frequency + 0xAC + + + DIVIDE_174 + mclk frequency = 1/174 * hmclk frequency + 0xAD + + + DIVIDE_175 + mclk frequency = 1/175 * hmclk frequency + 0xAE + + + DIVIDE_176 + mclk frequency = 1/176 * hmclk frequency + 0xAF + + + DIVIDE_177 + mclk frequency = 1/177 * hmclk frequency + 0xB0 + + + DIVIDE_178 + mclk frequency = 1/178 * hmclk frequency + 0xB1 + + + DIVIDE_179 + mclk frequency = 1/179 * hmclk frequency + 0xB2 + + + DIVIDE_180 + mclk frequency = 1/180 * hmclk frequency + 0xB3 + + + DIVIDE_181 + mclk frequency = 1/181 * hmclk frequency + 0xB4 + + + DIVIDE_182 + mclk frequency = 1/182 * hmclk frequency + 0xB5 + + + DIVIDE_183 + mclk frequency = 1/183 * hmclk frequency + 0xB6 + + + DIVIDE_184 + mclk frequency = 1/184 * hmclk frequency + 0xB7 + + + DIVIDE_185 + mclk frequency = 1/185 * hmclk frequency + 0xB8 + + + DIVIDE_186 + mclk frequency = 1/186 * hmclk frequency + 0xB9 + + + DIVIDE_187 + mclk frequency = 1/187 * hmclk frequency + 0xBA + + + DIVIDE_188 + mclk frequency = 1/188 * hmclk frequency + 0xBB + + + DIVIDE_189 + mclk frequency = 1/189 * hmclk frequency + 0xBC + + + DIVIDE_190 + mclk frequency = 1/190 * hmclk frequency + 0xBD + + + DIVIDE_191 + mclk frequency = 1/191 * hmclk frequency + 0xBE + + + DIVIDE_192 + mclk frequency = 1/192 * hmclk frequency + 0xBF + + + DIVIDE_193 + mclk frequency = 1/193 * hmclk frequency + 0xC0 + + + DIVIDE_194 + mclk frequency = 1/194 * hmclk frequency + 0xC1 + + + DIVIDE_195 + mclk frequency = 1/195 * hmclk frequency + 0xC2 + + + DIVIDE_196 + mclk frequency = 1/196 * hmclk frequency + 0xC3 + + + DIVIDE_197 + mclk frequency = 1/197 * hmclk frequency + 0xC4 + + + DIVIDE_198 + mclk frequency = 1/198 * hmclk frequency + 0xC5 + + + DIVIDE_199 + mclk frequency = 1/199 * hmclk frequency + 0xC6 + + + DIVIDE_200 + mclk frequency = 1/200 * hmclk frequency + 0xC7 + + + DIVIDE_201 + mclk frequency = 1/201 * hmclk frequency + 0xC8 + + + DIVIDE_202 + mclk frequency = 1/202 * hmclk frequency + 0xC9 + + + DIVIDE_203 + mclk frequency = 1/203 * hmclk frequency + 0xCA + + + DIVIDE_204 + mclk frequency = 1/204 * hmclk frequency + 0xCB + + + DIVIDE_205 + mclk frequency = 1/205 * hmclk frequency + 0xCC + + + DIVIDE_206 + mclk frequency = 1/206 * hmclk frequency + 0xCD + + + DIVIDE_207 + mclk frequency = 1/207 * hmclk frequency + 0xCE + + + DIVIDE_208 + mclk frequency = 1/208 * hmclk frequency + 0xCF + + + DIVIDE_209 + mclk frequency = 1/209 * hmclk frequency + 0xD0 + + + DIVIDE_210 + mclk frequency = 1/210 * hmclk frequency + 0xD1 + + + DIVIDE_211 + mclk frequency = 1/211 * hmclk frequency + 0xD2 + + + DIVIDE_212 + mclk frequency = 1/212 * hmclk frequency + 0xD3 + + + DIVIDE_213 + mclk frequency = 1/213 * hmclk frequency + 0xD4 + + + DIVIDE_214 + mclk frequency = 1/214 * hmclk frequency + 0xD5 + + + DIVIDE_215 + mclk frequency = 1/215 * hmclk frequency + 0xD6 + + + DIVIDE_216 + mclk frequency = 1/216 * hmclk frequency + 0xD7 + + + DIVIDE_217 + mclk frequency = 1/217 * hmclk frequency + 0xD8 + + + DIVIDE_218 + mclk frequency = 1/218 * hmclk frequency + 0xD9 + + + DIVIDE_219 + mclk frequency = 1/219 * hmclk frequency + 0xDA + + + DIVIDE_220 + mclk frequency = 1/220 * hmclk frequency + 0xDB + + + DIVIDE_221 + mclk frequency = 1/221 * hmclk frequency + 0xDC + + + DIVIDE_222 + mclk frequency = 1/222 * hmclk frequency + 0xDD + + + DIVIDE_223 + mclk frequency = 1/223 * hmclk frequency + 0xDE + + + DIVIDE_224 + mclk frequency = 1/224 * hmclk frequency + 0xDF + + + DIVIDE_225 + mclk frequency = 1/225 * hmclk frequency + 0xE0 + + + DIVIDE_226 + mclk frequency = 1/226 * hmclk frequency + 0xE1 + + + DIVIDE_227 + mclk frequency = 1/227 * hmclk frequency + 0xE2 + + + DIVIDE_228 + mclk frequency = 1/228 * hmclk frequency + 0xE3 + + + DIVIDE_229 + mclk frequency = 1/229 * hmclk frequency + 0xE4 + + + DIVIDE_230 + mclk frequency = 1/230 * hmclk frequency + 0xE5 + + + DIVIDE_231 + mclk frequency = 1/231 * hmclk frequency + 0xE6 + + + DIVIDE_232 + mclk frequency = 1/232 * hmclk frequency + 0xE7 + + + DIVIDE_233 + mclk frequency = 1/233 * hmclk frequency + 0xE8 + + + DIVIDE_234 + mclk frequency = 1/234 * hmclk frequency + 0xE9 + + + DIVIDE_235 + mclk frequency = 1/235 * hmclk frequency + 0xEA + + + DIVIDE_236 + mclk frequency = 1/236 * hmclk frequency + 0xEB + + + DIVIDE_237 + mclk frequency = 1/237 * hmclk frequency + 0xEC + + + DIVIDE_238 + mclk frequency = 1/238 * hmclk frequency + 0xED + + + DIVIDE_239 + mclk frequency = 1/239 * hmclk frequency + 0xEE + + + DIVIDE_240 + mclk frequency = 1/240 * hmclk frequency + 0xEF + + + DIVIDE_241 + mclk frequency = 1/241 * hmclk frequency + 0xF0 + + + DIVIDE_242 + mclk frequency = 1/242 * hmclk frequency + 0xF1 + + + DIVIDE_243 + mclk frequency = 1/243 * hmclk frequency + 0xF2 + + + DIVIDE_244 + mclk frequency = 1/244 * hmclk frequency + 0xF3 + + + DIVIDE_245 + mclk frequency = 1/245 * hmclk frequency + 0xF4 + + + DIVIDE_246 + mclk frequency = 1/246 * hmclk frequency + 0xF5 + + + DIVIDE_247 + mclk frequency = 1/247 * hmclk frequency + 0xF6 + + + DIVIDE_248 + mclk frequency = 1/248 * hmclk frequency + 0xF7 + + + DIVIDE_249 + mclk frequency = 1/249 * hmclk frequency + 0xF8 + + + DIVIDE_250 + mclk frequency = 1/250 * hmclk frequency + 0xF9 + + + DIVIDE_251 + mclk frequency = 1/251 * hmclk frequency + 0xFA + + + DIVIDE_252 + mclk frequency = 1/252 * hmclk frequency + 0xFB + + + DIVIDE_253 + mclk frequency = 1/253 * hmclk frequency + 0xFC + + + DIVIDE_254 + mclk frequency = 1/254 * hmclk frequency + 0xFD + + + DIVIDE_255 + mclk frequency = 1/255 * hmclk frequency + 0xFE + + + DIVIDE_256 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset + 24 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 25 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Medium Quality Sound (MQS) Oversample + 26 + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + QTIMER1_TMR_CNTS_FREEZE + QTIMER1 timer counter freeze + 28 + 1 + read-write + + + QTIMER1_TMR_CNTS_FREEZE_0 + Timer counter works normally + 0 + + + QTIMER1_TMR_CNTS_FREEZE_1 + Reset counter and ouput flags + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xFFF0 + 0xFFFFFFFF + + + DCP_KEY_SEL + Select 128-bit DCP key from 256-bit key from SNVS/OCOTP + 4 + 1 + read-write + + + DCP_KEY_SEL_0 + Select [127:0] from SNVS/OCOTP key as DCP key + 0 + + + DCP_KEY_SEL_1 + Select [255:128] from SNVS/OCOTP key as DCP key + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDMA_STOP_REQ + EDMA stop request. + 0 + 1 + read-write + + + EDMA_STOP_REQ_0 + stop request off + 0 + + + EDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + TRNG_STOP_REQ + TRNG stop request. + 3 + 1 + read-write + + + TRNG_STOP_REQ_0 + stop request off + 0 + + + TRNG_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request. + 5 + 1 + read-write + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request. + 6 + 1 + read-write + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request. + 7 + 1 + read-write + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + PIT_STOP_REQ + PIT stop request. + 10 + 1 + read-write + + + PIT_STOP_REQ_0 + stop request off + 0 + + + PIT_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXSPI_STOP_REQ + FlexSPI stop request. + 11 + 1 + read-write + + + FLEXSPI_STOP_REQ_0 + stop request off + 0 + + + FLEXSPI_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO1_STOP_REQ + FlexIO1 stop request. + 12 + 1 + read-write + + + FLEXIO1_STOP_REQ_0 + stop request off + 0 + + + FLEXIO1_STOP_REQ_1 + stop request on + 0x1 + + + + + EDMA_STOP_ACK + EDMA stop acknowledge. This is a status (read-only) bit + 16 + 1 + read-only + + + EDMA_STOP_ACK_0 + EDMA stop acknowledge is not asserted + 0 + + + EDMA_STOP_ACK_1 + EDMA stop acknowledge is asserted (EDMA is in STOP mode). + 0x1 + + + + + TRNG_STOP_ACK + TRNG stop acknowledge + 19 + 1 + read-only + + + TRNG_STOP_ACK_0 + TRNG stop acknowledge is not asserted + 0 + + + TRNG_STOP_ACK_1 + TRNG stop acknowledge is asserted + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge + 21 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge + 22 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge + 23 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted + 0x1 + + + + + PIT_STOP_ACK + PIT stop acknowledge + 26 + 1 + read-only + + + PIT_STOP_ACK_0 + PIT stop acknowledge is not asserted + 0 + + + PIT_STOP_ACK_1 + PIT stop acknowledge is asserted + 0x1 + + + + + FLEXSPI_STOP_ACK + FLEXSPI stop acknowledge + 27 + 1 + read-only + + + FLEXSPI_STOP_ACK_0 + FLEXSPI stop acknowledge is not asserted + 0 + + + FLEXSPI_STOP_ACK_1 + FLEXSPI stop acknowledge is asserted + 0x1 + + + + + FLEXIO1_STOP_ACK + FLEXIO1 stop acknowledge + 28 + 1 + read-only + + + FLEXIO1_STOP_ACK_0 + FLEXIO1 stop acknowledge is not asserted + 0 + + + FLEXIO1_STOP_ACK_1 + FLEXIO1 stop acknowledge is asserted + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 23 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from GPT2_CAPTURE1 + 0 + + + GPT2_CAPIN1_SEL_1 + source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 28 + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 29 + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + + + GPR6 + GPR6 General Purpose Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + QTIMER1_TRM0_INPUT_SEL + QTIMER1 TMR0 input select + 0 + 1 + read-write + + + QTIMER1_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM1_INPUT_SEL + QTIMER1 TMR1 input select + 1 + 1 + read-write + + + QTIMER1_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM2_INPUT_SEL + QTIMER1 TMR2 input select + 2 + 1 + read-write + + + QTIMER1_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM3_INPUT_SEL + QTIMER1 TMR3 input select + 3 + 1 + read-write + + + QTIMER1_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_4 + IOMUXC XBAR_INOUT4 function direction select + 16 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_4_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_4_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_5 + IOMUXC XBAR_INOUT5 function direction select + 17 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_5_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_5_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_6 + IOMUXC XBAR_INOUT6 function direction select + 18 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_6_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_6_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_7 + IOMUXC XBAR_INOUT7 function direction select + 19 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_7_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_7_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_8 + IOMUXC XBAR_INOUT8 function direction select + 20 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_8_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_8_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_9 + IOMUXC XBAR_INOUT9 function direction select + 21 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_9_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_9_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_10 + IOMUXC XBAR_INOUT10 function direction select + 22 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_10_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_10_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_11 + IOMUXC XBAR_INOUT11 function direction select + 23 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_11_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_11_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_12 + IOMUXC XBAR_INOUT12 function direction select + 24 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_12_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_12_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_13 + IOMUXC XBAR_INOUT13 function direction select + 25 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_13_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_13_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_14 + IOMUXC XBAR_INOUT14 function direction select + 26 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_14_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_14_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_15 + IOMUXC XBAR_INOUT15 function direction select + 27 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_15_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_15_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_16 + IOMUXC XBAR_INOUT16 function direction select + 28 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_16_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_16_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_17 + IOMUXC XBAR_INOUT17 function direction select + 29 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_17_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_17_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_18 + IOMUXC XBAR_INOUT18 function direction select + 30 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_18_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_18_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_19 + IOMUXC XBAR_INOUT19 function direction select + 31 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_19_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_19_1 + XBAR_INOUT as output + 0x1 + + + + + + + GPR7 + GPR7 General Purpose Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_STOP_REQ + LPI2C1 stop request + 0 + 1 + read-write + + + LPI2C1_STOP_REQ_0 + stop request off + 0 + + + LPI2C1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C2_STOP_REQ + LPI2C2 stop request + 1 + 1 + read-write + + + LPI2C2_STOP_REQ_0 + stop request off + 0 + + + LPI2C2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI1_STOP_REQ + LPSPI1 stop request + 4 + 1 + read-write + + + LPSPI1_STOP_REQ_0 + stop request off + 0 + + + LPSPI1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI2_STOP_REQ + LPSPI2 stop request + 5 + 1 + read-write + + + LPSPI2_STOP_REQ_0 + stop request off + 0 + + + LPSPI2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART1_STOP_REQ + LPUART1 stop request + 8 + 1 + read-write + + + LPUART1_STOP_REQ_0 + stop request off + 0 + + + LPUART1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART2_STOP_REQ + LPUART1 stop request + 9 + 1 + read-write + + + LPUART2_STOP_REQ_0 + stop request off + 0 + + + LPUART2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART3_STOP_REQ + LPUART3 stop request + 10 + 1 + read-write + + + LPUART3_STOP_REQ_0 + stop request off + 0 + + + LPUART3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART4_STOP_REQ + LPUART4 stop request + 11 + 1 + read-write + + + LPUART4_STOP_REQ_0 + stop request off + 0 + + + LPUART4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C1_STOP_ACK + LPI2C1 stop acknowledge + 16 + 1 + read-only + + + LPI2C1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C1_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + LPI2C2_STOP_ACK + LPI2C2 stop acknowledge + 17 + 1 + read-only + + + LPI2C2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI1_STOP_ACK + LPSPI1 stop acknowledge + 20 + 1 + read-only + + + LPSPI1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI2_STOP_ACK + LPSPI2 stop acknowledge + 21 + 1 + read-only + + + LPSPI2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART1_STOP_ACK + LPUART1 stop acknowledge + 24 + 1 + read-only + + + LPUART1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART2_STOP_ACK + LPUART1 stop acknowledge + 25 + 1 + read-only + + + LPUART2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART3_STOP_ACK + LPUART3 stop acknowledge + 26 + 1 + read-only + + + LPUART3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART4_STOP_ACK + LPUART4 stop acknowledge + 27 + 1 + read-only + + + LPUART4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + + + GPR8 + GPR8 General Purpose Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_IPG_STOP_MODE + LPI2C1 stop mode selection, cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + LPI2C1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C1_IPG_DOZE + LPI2C1 ipg_doze mode + 1 + 1 + read-write + + + LPI2C1_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C2_IPG_STOP_MODE + LPI2C2 stop mode selection, cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + LPI2C2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C2_IPG_DOZE + LPI2C2 ipg_doze mode + 3 + 1 + read-write + + + LPI2C2_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI1_IPG_STOP_MODE + LPSPI1 stop mode selection, cannot change when ipg_stop is asserted. + 8 + 1 + read-write + + + LPSPI1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI1_IPG_DOZE + LPSPI1 ipg_doze mode + 9 + 1 + read-write + + + LPSPI1_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI2_IPG_STOP_MODE + LPSPI2 stop mode selection, cannot change when ipg_stop is asserted. + 10 + 1 + read-write + + + LPSPI2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI2_IPG_DOZE + LPSPI2 ipg_doze mode + 11 + 1 + read-write + + + LPSPI2_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART1_IPG_STOP_MODE + LPUART1 stop mode selection, cannot change when ipg_stop is asserted. + 16 + 1 + read-write + + + LPUART1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART1_IPG_DOZE + LPUART1 ipg_doze mode + 17 + 1 + read-write + + + LPUART1_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART2_IPG_STOP_MODE + LPUART2 stop mode selection, cannot change when ipg_stop is asserted. + 18 + 1 + read-write + + + LPUART2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART2_IPG_DOZE + LPUART2 ipg_doze mode + 19 + 1 + read-write + + + LPUART2_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART3_IPG_STOP_MODE + LPUART3 stop mode selection, cannot change when ipg_stop is asserted. + 20 + 1 + read-write + + + LPUART3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART3_IPG_DOZE + LPUART3 ipg_doze mode + 21 + 1 + read-write + + + LPUART3_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART4_IPG_STOP_MODE + LPUART4 stop mode selection, cannot change when ipg_stop is asserted. + 22 + 1 + read-write + + + LPUART4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART4_IPG_DOZE + LPUART4 ipg_doze mode + 23 + 1 + read-write + + + LPUART4_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + NIDEN + ARM non-secure (non-invasive) debug enable + 0 + 1 + read-write + + + NIDEN_0 + Debug turned off. + 0 + + + NIDEN_1 + Debug enabled (default). + 0x1 + + + + + DBG_EN + ARM invasive debug enable + 1 + 1 + read-write + + + DBG_EN_0 + Debug turned off. + 0 + + + DBG_EN_1 + Debug enabled (default). + 0x1 + + + + + SEC_ERR_RESP + Security error response enable for all security gaskets (on both AHB and AXI buses) + 2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + DCPKEY_OCOTP_OR_KEYMUX + DCP Key selection bit. + 4 + 1 + read-write + + + DCPKEY_OCOTP_OR_KEYMUX_0 + Select key from Key MUX (SNVS/OTPMK). + 0 + + + DCPKEY_OCOTP_OR_KEYMUX_1 + Select key from OCOTP (SW_GP2). + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 8 + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 9 + 6 + read-write + + + LOCK_NIDEN + Lock NIDEN field for changes + 16 + 1 + read-write + + + LOCK_NIDEN_0 + Field is not locked + 0 + + + LOCK_NIDEN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DBG_EN + Lock DBG_EN field for changes + 17 + 1 + read-write + + + LOCK_DBG_EN_0 + Field is not locked + 0 + + + LOCK_DBG_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_SEC_ERR_RESP + Lock SEC_ERR_RESP field for changes + 18 + 1 + read-write + + + LOCK_SEC_ERR_RESP_0 + Field is not locked + 0 + + + LOCK_SEC_ERR_RESP_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX + Lock DCP Key OCOTP/Key MUX selection bit + 20 + 1 + read-write + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_0 + Field is not locked + 0 + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_EN + Lock OCRAM_TZ_EN field for changes + 24 + 1 + read-write + + + LOCK_OCRAM_TZ_EN_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_ADDR + Lock OCRAM_TZ_ADDR field for changes + 25 + 7 + read-write + + + LOCK_OCRAM_TZ_ADDR_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_ADDR_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR11 + GPR11 General Purpose Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + M7_APC_AC_R0_CTRL + Access control of memory region-0 + 0 + 2 + read-write + + + M7_APC_AC_R0_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R0_CTRL_1 + M7 debug protection enabled + 0x1 + + + + + M7_APC_AC_R1_CTRL + Access control of memory region-1 + 2 + 2 + read-write + + + M7_APC_AC_R1_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R1_CTRL_1 + M7 debug protection enabled + 0x1 + + + + + M7_APC_AC_R2_CTRL + Access control of memory region-2 + 4 + 2 + read-write + + + M7_APC_AC_R2_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R2_CTRL_1 + M7 debug protection enabled + 0x1 + + + + + M7_APC_AC_R3_CTRL + Access control of memory region-3 + 6 + 2 + read-write + + + M7_APC_AC_R3_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R3_CTRL_1 + M7 debug protection enabled + 0x1 + + + + + BEE_DE_RX_EN + BEE data decryption of memory region-n (n = 3 to 0) + 8 + 4 + read-write + + + LOCK_M7_APC_AC_R0_CTRL + Lock M7_APC_AC_R0_CTRL field for changes + 16 + 2 + read-write + + + LOCK_M7_APC_AC_R1_CTRL + Lock M7_APC_AC_R1_CTRL field for changes + 18 + 2 + read-write + + + LOCK_M7_APC_AC_R2_CTRL + Lock M7_APC_AC_R2_CTRL field for changes + 20 + 2 + read-write + + + LOCK_M7_APC_AC_R3_CTRL + Lock M7_APC_AC_R3_CTRL field for changes + 22 + 2 + read-write + + + LOCK_BEE_DE_RX_EN + Lock BEE_DE_RX_EN[n] (n = 3 to 0) field for changes + 24 + 4 + read-write + + + + + GPR12 + GPR12 General Purpose Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXIO1_IPG_STOP_MODE + FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + FLEXIO1_IPG_STOP_MODE_0 + FlexIO1 is functional in Stop mode. + 0 + + + FLEXIO1_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + 0x1 + + + + + FLEXIO1_IPG_DOZE + FLEXIO1 ipg_doze mode + 1 + 1 + read-write + + + FLEXIO1_IPG_DOZE_0 + FLEXIO1 is not in doze mode + 0 + + + FLEXIO1_IPG_DOZE_1 + FLEXIO1 is in doze mode + 0x1 + + + + + + + GPR13 + GPR13 General Purpose Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARCACHE_USDHC + uSDHC block cacheable attribute value of AXI read transactions + 0 + 1 + read-write + + + ARCACHE_USDHC_0 + Cacheable attribute is off for read transactions. + 0 + + + ARCACHE_USDHC_1 + Cacheable attribute is on for read transactions. + 0x1 + + + + + AWCACHE_USDHC + uSDHC block cacheable attribute value of AXI write transactions + 1 + 1 + read-write + + + AWCACHE_USDHC_0 + Cacheable attribute is off for write transactions. + 0 + + + AWCACHE_USDHC_1 + Cacheable attribute is on for write transactions. + 0x1 + + + + + CACHE_USB + USB block cacheable attribute value of AXI transactions + 13 + 1 + read-write + + + CACHE_USB_0 + Cacheable attribute is off for read/write transactions. + 0 + + + CACHE_USB_1 + Cacheable attribute is on for read/write transactions. + 0x1 + + + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CM7_CFGITCMSZ + ITCM total size configuration + 16 + 4 + read-write + + + CM7_CFGITCMSZ_0 + 0 KB (No ITCM) + 0 + + + CM7_CFGITCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGITCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGITCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGITCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGITCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGITCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGITCMSZ_9 + 256 KB + 0x9 + + + + + CM7_CFGDTCMSZ + DTCM total size configuration + 20 + 4 + read-write + + + CM7_CFGDTCMSZ_0 + 0 KB (No DTCM) + 0 + + + CM7_CFGDTCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGDTCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGDTCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGDTCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGDTCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGDTCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGDTCMSZ_9 + 256 KB + 0x9 + + + + + + + GPR15 + GPR15 General Purpose Register + 0x3C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + GPR16 + GPR16 General Purpose Register + 0x40 + 32 + read-write + 0x200003 + 0xFFFFFFFF + + + INIT_ITCM_EN + ITCM enable initialization out of reset + 0 + 1 + read-write + + + INIT_ITCM_EN_0 + ITCM is disabled + 0 + + + INIT_ITCM_EN_1 + ITCM is enabled + 0x1 + + + + + INIT_DTCM_EN + DTCM enable initialization out of reset + 1 + 1 + read-write + + + INIT_DTCM_EN_0 + DTCM is disabled + 0 + + + INIT_DTCM_EN_1 + DTCM is enabled + 0x1 + + + + + FLEXRAM_BANK_CFG_SEL + FlexRAM bank config source select + 2 + 1 + read-write + + + FLEXRAM_BANK_CFG_SEL_0 + use fuse value to config + 0 + + + FLEXRAM_BANK_CFG_SEL_1 + use FLEXRAM_BANK_CFG to config + 0x1 + + + + + + + GPR17 + GPR17 General Purpose Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXRAM_BANK_CFG + FlexRAM bank config value + 0 + 8 + read-write + + + + + GPR18 + GPR18 General Purpose Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_BOT + lock M7_APC_AC_R0_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_BOT + APC end address of memory region-0 + 3 + 29 + read-write + + + + + GPR19 + GPR19 General Purpose Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_TOP + lock M7_APC_AC_R0_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_TOP + APC start address of memory region-0 + 3 + 29 + read-write + + + + + GPR20 + GPR20 General Purpose Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_BOT + lock M7_APC_AC_R1_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_BOT + APC end address of memory region-1 + 3 + 29 + read-write + + + + + GPR21 + GPR21 General Purpose Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_TOP + lock M7_APC_AC_R1_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_TOP + APC start address of memory region-1 + 3 + 29 + read-write + + + + + GPR22 + GPR22 General Purpose Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_BOT + lock M7_APC_AC_R2_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R2_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_BOT + APC end address of memory region-2 + 3 + 29 + read-write + + + + + GPR23 + GPR23 General Purpose Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_TOP + lock M7_APC_AC_R2_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R2_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_TOP + APC start address of memory region-2 + 3 + 29 + read-write + + + + + GPR24 + GPR24 General Purpose Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_BOT + lock M7_APC_AC_R3_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_BOT + APC end address of memory region-3 + 3 + 29 + read-write + + + + + GPR25 + GPR25 General Purpose Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_TOP + lock M7_APC_AC_R3_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_TOP + APC start address of memory region-3 + 3 + 29 + read-write + + + + + + + FLEXRAM + FLEXRAM + FLEXRAM + 0x400B0000 + + 0 + 0x1000 + registers + + + FLEXRAM + 38 + + + + TCM_CTRL + TCM CRTL Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCM_WWAIT_EN + TCM Write Wait Mode Enable + 0 + 1 + read-write + + + TCM_WWAIT_EN_0 + TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_WWAIT_EN_1 + TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + TCM_RWAIT_EN + TCM Read Wait Mode Enable + 1 + 1 + read-write + + + TCM_RWAIT_EN_0 + TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_RWAIT_EN_1 + TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + FORCE_CLK_ON + Force RAM Clock Always On + 2 + 1 + read-write + + + + + INT_STATUS + Interrupt Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STATUS + ITCM Access Error Status + 3 + 1 + read-write + oneToClear + + + ITCM_ERR_STATUS_0 + ITCM access error does not happen + 0 + + + ITCM_ERR_STATUS_1 + ITCM access error happens. + 0x1 + + + + + DTCM_ERR_STATUS + DTCM Access Error Status + 4 + 1 + read-write + oneToClear + + + DTCM_ERR_STATUS_0 + DTCM access error does not happen + 0 + + + DTCM_ERR_STATUS_1 + DTCM access error happens. + 0x1 + + + + + OCRAM_ERR_STATUS + OCRAM Access Error Status + 5 + 1 + read-write + oneToClear + + + OCRAM_ERR_STATUS_0 + OCRAM access error does not happen + 0 + + + OCRAM_ERR_STATUS_1 + OCRAM access error happens. + 0x1 + + + + + + + INT_STAT_EN + Interrupt Status Enable Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STAT_EN + ITCM Access Error Status Enable + 3 + 1 + read-write + + + ITCM_ERR_STAT_EN_0 + Masked + 0 + + + ITCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_STAT_EN + DTCM Access Error Status Enable + 4 + 1 + read-write + + + DTCM_ERR_STAT_EN_0 + Masked + 0 + + + DTCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_STAT_EN + OCRAM Access Error Status Enable + 5 + 1 + read-write + + + OCRAM_ERR_STAT_EN_0 + Masked + 0 + + + OCRAM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + + + INT_SIG_EN + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_SIG_EN + ITCM Access Error Interrupt Enable + 3 + 1 + read-write + + + ITCM_ERR_SIG_EN_0 + Masked + 0 + + + ITCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_SIG_EN + DTCM Access Error Interrupt Enable + 4 + 1 + read-write + + + DTCM_ERR_SIG_EN_0 + Masked + 0 + + + DTCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_SIG_EN + OCRAM Access Error Interrupt Enable + 5 + 1 + read-write + + + OCRAM_ERR_SIG_EN_0 + Masked + 0 + + + OCRAM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + + + + + EWM + EWM + EWM + 0x400B4000 + + 0 + 0x6 + registers + + + EWM + 94 + + + + CTRL + Control Register + 0 + 8 + read-write + 0 + 0xFF + + + EWMEN + EWM enable. + 0 + 1 + read-writeOnce + + + ASSIN + EWM_in's Assertion State Select. + 1 + 1 + read-writeOnce + + + INEN + Input Enable. + 2 + 1 + read-writeOnce + + + INTEN + Interrupt Enable. + 3 + 1 + read-write + + + + + SERV + Service Register + 0x1 + 8 + read-write + 0 + 0xFF + + + SERVICE + SERVICE + 0 + 8 + read-write + + + + + CMPL + Compare Low Register + 0x2 + 8 + read-writeOnce + 0 + 0xFF + + + COMPAREL + COMPAREL + 0 + 8 + read-writeOnce + + + + + CMPH + Compare High Register + 0x3 + 8 + read-writeOnce + 0xFF + 0xFF + + + COMPAREH + COMPAREH + 0 + 8 + read-writeOnce + + + + + CLKCTRL + Clock Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + CLKSEL + CLKSEL + 0 + 2 + read-writeOnce + + + + + CLKPRESCALER + Clock Prescaler Register + 0x5 + 8 + read-writeOnce + 0 + 0xFF + + + CLK_DIV + CLK_DIV + 0 + 8 + read-writeOnce + + + + + + + WDOG1 + WDOG + WDOG + WDOG + 0x400B8000 + + 0 + 0xA + registers + + + WDOG1 + 92 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + WDZST + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + WDBG + 1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + WDE + 2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDT + 3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + SRS + 4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDA + 5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + WDW + 7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + WT + 8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + WSR + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + SFTW + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + TOUT + 1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + POR + 4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + WICT + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + WTIS + 14 + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + WIE + 15 + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + PDE + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + 0x400D0000 + + 0 + 0xA + registers + + + WDOG2 + 45 + + + + RTWDOG + WDOG + RTWDOG + 0x400BC000 + + 0 + 0x10 + registers + + + RTWDOG + 93 + + + + CS + Watchdog Control and Status Register + 0 + 32 + read-write + 0x2980 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + STOP_0 + Watchdog disabled in chip stop mode. + 0 + + + STOP_1 + Watchdog enabled in chip stop mode. + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + WAIT_0 + Watchdog disabled in chip wait mode. + 0 + + + WAIT_1 + Watchdog enabled in chip wait mode. + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DBG_0 + Watchdog disabled in chip debug mode. + 0 + + + DBG_1 + Watchdog enabled in chip debug mode. + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + TST_0 + Watchdog test mode disabled. + 0 + + + TST_1 + Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + 0x1 + + + TST_2 + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + TST_3 + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + UPDATE_0 + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + UPDATE_1 + Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + INT_0 + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + INT_1 + Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + EN_0 + Watchdog disabled. + 0 + + + EN_1 + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + CLK_0 + Bus clock + 0 + + + CLK_1 + LPO clock + 0x1 + + + CLK_2 + INTCLK (internal clock) + 0x2 + + + CLK_3 + ERCLK (external reference clock) + 0x3 + + + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RCS_0 + Reconfiguring WDOG. + 0 + + + RCS_1 + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + ULK_0 + WDOG is locked. + 0 + + + ULK_1 + WDOG is unlocked. + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + PRES_0 + 256 prescaler disabled. + 0 + + + PRES_1 + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + CMD32EN_0 + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + CMD32EN_1 + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + FLG_0 + No interrupt occurred. + 0 + + + FLG_1 + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + WIN_0 + Window mode disabled. + 0 + + + WIN_1 + Window mode enabled. + 0x1 + + + + + + + CNT + Watchdog Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Watchdog Timeout Value Register + 0x8 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Watchdog Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + 0x400C4000 + + 0 + 0x5C + registers + + + ADC1 + 67 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + R%s + Data result register for HW triggers + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x44 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 10 + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 11 + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 13 + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 14 + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 16 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 7 + 1 + read-write + + + + + GS + General status register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynchronous wake up interrupt occurred in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 16 + 12 + read-write + + + + + OFS + Offset correction value register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 12 + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + TRNG + TRNG + TRNG + 0x400CC000 + + 0 + 0xFF + registers + + + TRNG + 53 + + + + MCTL + Miscellaneous Control Register + 0 + 32 + read-write + 0x12001 + 0xFFFFFFFF + + + SAMP_MODE + Sample Mode + 0 + 2 + read-write + + + SAMP_MODE_0 + use Von Neumann data into both Entropy shifter and Statistical Checker + 0 + + + SAMP_MODE_1 + use raw data into both Entropy shifter and Statistical Checker + 0x1 + + + SAMP_MODE_2 + use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + 0x2 + + + SAMP_MODE_3 + undefined/reserved. + 0x3 + + + + + OSC_DIV + Oscillator Divide + 2 + 2 + read-write + + + OSC_DIV_0 + use ring oscillator with no divide + 0 + + + OSC_DIV_1 + use ring oscillator divided-by-2 + 0x1 + + + OSC_DIV_2 + use ring oscillator divided-by-4 + 0x2 + + + OSC_DIV_3 + use ring oscillator divided-by-8 + 0x3 + + + + + UNUSED4 + This bit is unused. Always reads zero. + 4 + 1 + read-only + + + TRNG_ACC + TRNG Access Mode + 5 + 1 + read-write + + + RST_DEF + Reset Defaults + 6 + 1 + write-only + + + FOR_SCLK + Force System Clock + 7 + 1 + read-write + + + FCT_FAIL + Read only: Frequency Count Fail + 8 + 1 + read-only + + + FCT_VAL + Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. + 9 + 1 + read-only + + + ENT_VAL + Read only: Entropy Valid + 10 + 1 + read-only + + + TST_OUT + Read only: Test point inside ring oscillator. + 11 + 1 + read-only + + + ERR + Read: Error status + 12 + 1 + read-write + oneToClear + + + TSTOP_OK + TRNG_OK_TO_STOP + 13 + 1 + read-only + + + LRUN_CONT + Long run count continues between entropy generations + 14 + 1 + read-write + + + PRGM + Programming Mode Select + 16 + 1 + read-write + + + + + SCMISC + Statistical Check Miscellaneous Register + 0x4 + 32 + read-write + 0x10022 + 0xFFFFFFFF + + + LRUN_MAX + LONG RUN MAX LIMIT + 0 + 8 + read-write + + + RTY_CT + RETRY COUNT + 16 + 4 + read-write + + + + + PKRRNG + Poker Range Register + 0x8 + 32 + read-write + 0x9A3 + 0xFFFFFFFF + + + PKR_RNG + Poker Range + 0 + 16 + read-write + + + + + PKRMAX + Poker Maximum Limit Register + MAX_SQ + 0xC + 32 + read-write + 0x6920 + 0xFFFFFFFF + + + PKR_MAX + Poker Maximum Limit. + 0 + 24 + read-write + + + + + PKRSQ + Poker Square Calculation Result Register + MAX_SQ + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_SQ + Poker Square Calculation Result. + 0 + 24 + read-only + + + + + SDCTL + Seed Control Register + 0x10 + 32 + read-write + 0xC8009C4 + 0xFFFFFFFF + + + SAMP_SIZE + Sample Size + 0 + 16 + read-write + + + ENT_DLY + Entropy Delay + 16 + 16 + read-write + + + + + SBLIM + Sparse Bit Limit Register + SBLIM_TOTSAM + 0x14 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + SB_LIM + Sparse Bit Limit + 0 + 10 + read-write + + + + + TOTSAM + Total Samples Register + SBLIM_TOTSAM + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOT_SAM + Total Samples + 0 + 20 + read-only + + + + + FRQMIN + Frequency Count Minimum Limit Register + 0x18 + 32 + read-write + 0x640 + 0xFFFFFFFF + + + FRQ_MIN + Frequency Count Minimum Limit + 0 + 22 + read-write + + + + + FRQCNT + Frequency Count Register + MAX_CNT + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FRQ_CT + Frequency Count + 0 + 22 + read-only + + + + + FRQMAX + Frequency Count Maximum Limit Register + MAX_CNT + 0x1C + 32 + read-write + 0x6400 + 0xFFFFFFFF + + + FRQ_MAX + Frequency Counter Maximum Limit + 0 + 22 + read-write + + + + + SCMC + Statistical Check Monobit Count Register + SCML_MC + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + MONO_CT + Monobit Count + 0 + 16 + read-only + + + + + SCML + Statistical Check Monobit Limit Register + SCML_MC + 0x20 + 32 + read-write + 0x10C0568 + 0xFFFFFFFF + + + MONO_MAX + Monobit Maximum Limit + 0 + 16 + read-write + + + MONO_RNG + Monobit Range + 16 + 16 + read-write + + + + + SCR1C + Statistical Check Run Length 1 Count Register + SCR1L_1C + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + R1_0_CT + Runs of Zero, Length 1 Count + 0 + 15 + read-only + + + R1_1_CT + Runs of One, Length 1 Count + 16 + 15 + read-only + + + + + SCR1L + Statistical Check Run Length 1 Limit Register + SCR1L_1C + 0x24 + 32 + read-write + 0xB20195 + 0xFFFFFFFF + + + RUN1_MAX + Run Length 1 Maximum Limit + 0 + 15 + read-write + + + RUN1_RNG + Run Length 1 Range + 16 + 15 + read-write + + + + + SCR2C + Statistical Check Run Length 2 Count Register + SCR2L_2C + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + R2_0_CT + Runs of Zero, Length 2 Count + 0 + 14 + read-only + + + R2_1_CT + Runs of One, Length 2 Count + 16 + 14 + read-only + + + + + SCR2L + Statistical Check Run Length 2 Limit Register + SCR2L_2C + 0x28 + 32 + read-write + 0x7A00DC + 0xFFFFFFFF + + + RUN2_MAX + Run Length 2 Maximum Limit + 0 + 14 + read-write + + + RUN2_RNG + Run Length 2 Range + 16 + 14 + read-write + + + + + SCR3C + Statistical Check Run Length 3 Count Register + SCR3L_3C + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + R3_0_CT + Runs of Zeroes, Length 3 Count + 0 + 13 + read-only + + + R3_1_CT + Runs of Ones, Length 3 Count + 16 + 13 + read-only + + + + + SCR3L + Statistical Check Run Length 3 Limit Register + SCR3L_3C + 0x2C + 32 + read-write + 0x58007D + 0xFFFFFFFF + + + RUN3_MAX + Run Length 3 Maximum Limit + 0 + 13 + read-write + + + RUN3_RNG + Run Length 3 Range + 16 + 13 + read-write + + + + + SCR4C + Statistical Check Run Length 4 Count Register + SCR4L_4C + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + R4_0_CT + Runs of Zero, Length 4 Count + 0 + 12 + read-only + + + R4_1_CT + Runs of One, Length 4 Count + 16 + 12 + read-only + + + + + SCR4L + Statistical Check Run Length 4 Limit Register + SCR4L_4C + 0x30 + 32 + read-write + 0x40004B + 0xFFFFFFFF + + + RUN4_MAX + Run Length 4 Maximum Limit + 0 + 12 + read-write + + + RUN4_RNG + Run Length 4 Range + 16 + 12 + read-write + + + + + SCR5C + Statistical Check Run Length 5 Count Register + SCR5L_5C + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + R5_0_CT + Runs of Zero, Length 5 Count + 0 + 11 + read-only + + + R5_1_CT + Runs of One, Length 5 Count + 16 + 11 + read-only + + + + + SCR5L + Statistical Check Run Length 5 Limit Register + SCR5L_5C + 0x34 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN5_MAX + Run Length 5 Maximum Limit + 0 + 11 + read-write + + + RUN5_RNG + Run Length 5 Range + 16 + 11 + read-write + + + + + SCR6PC + Statistical Check Run Length 6+ Count Register + SCR6PL_PC + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + R6P_0_CT + Runs of Zero, Length 6+ Count + 0 + 11 + read-only + + + R6P_1_CT + Runs of One, Length 6+ Count + 16 + 11 + read-only + + + + + SCR6PL + Statistical Check Run Length 6+ Limit Register + SCR6PL_PC + 0x38 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN6P_MAX + Run Length 6+ Maximum Limit + 0 + 11 + read-write + + + RUN6P_RNG + Run Length 6+ Range + 16 + 11 + read-write + + + + + STATUS + Status Register + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TF1BR0 + Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. + 0 + 1 + read-only + + + TF1BR1 + Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. + 1 + 1 + read-only + + + TF2BR0 + Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. + 2 + 1 + read-only + + + TF2BR1 + Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. + 3 + 1 + read-only + + + TF3BR0 + Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. + 4 + 1 + read-only + + + TF3BR1 + Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. + 5 + 1 + read-only + + + TF4BR0 + Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. + 6 + 1 + read-only + + + TF4BR1 + Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. + 7 + 1 + read-only + + + TF5BR0 + Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. + 8 + 1 + read-only + + + TF5BR1 + Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. + 9 + 1 + read-only + + + TF6PBR0 + Test Fail, 6 Plus Bit Run, Sampling 0s + 10 + 1 + read-only + + + TF6PBR1 + Test Fail, 6 Plus Bit Run, Sampling 1s + 11 + 1 + read-only + + + TFSB + Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. + 12 + 1 + read-only + + + TFLR + Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. + 13 + 1 + read-only + + + TFP + Test Fail, Poker. If TFP=1, the Poker Test has failed. + 14 + 1 + read-only + + + TFMB + Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. + 15 + 1 + read-only + + + RETRY_CT + RETRY COUNT + 16 + 4 + read-only + + + + + 16 + 0x4 + ENT[%s] + Entropy Read Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + PKRCNT10 + Statistical Check Poker Count 1 and 0 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_0_CT + Poker 0h Count + 0 + 16 + read-only + + + PKR_1_CT + Poker 1h Count + 16 + 16 + read-only + + + + + PKRCNT32 + Statistical Check Poker Count 3 and 2 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_2_CT + Poker 2h Count + 0 + 16 + read-only + + + PKR_3_CT + Poker 3h Count + 16 + 16 + read-only + + + + + PKRCNT54 + Statistical Check Poker Count 5 and 4 Register + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_4_CT + Poker 4h Count + 0 + 16 + read-only + + + PKR_5_CT + Poker 5h Count + 16 + 16 + read-only + + + + + PKRCNT76 + Statistical Check Poker Count 7 and 6 Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_6_CT + Poker 6h Count + 0 + 16 + read-only + + + PKR_7_CT + Poker 7h Count + 16 + 16 + read-only + + + + + PKRCNT98 + Statistical Check Poker Count 9 and 8 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_8_CT + Poker 8h Count + 0 + 16 + read-only + + + PKR_9_CT + Poker 9h Count + 16 + 16 + read-only + + + + + PKRCNTBA + Statistical Check Poker Count B and A Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_A_CT + Poker Ah Count + 0 + 16 + read-only + + + PKR_B_CT + Poker Bh Count + 16 + 16 + read-only + + + + + PKRCNTDC + Statistical Check Poker Count D and C Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_C_CT + Poker Ch Count + 0 + 16 + read-only + + + PKR_D_CT + Poker Dh Count + 16 + 16 + read-only + + + + + PKRCNTFE + Statistical Check Poker Count F and E Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_E_CT + Poker Eh Count + 0 + 16 + read-only + + + PKR_F_CT + Poker Fh Count + 16 + 16 + read-only + + + + + SEC_CFG + Security Configuration Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + UNUSED0 + This bit is unused. Ignore. + 0 + 1 + read-write + + + NO_PRGM + If set, the TRNG registers cannot be programmed + 1 + 1 + read-write + + + NO_PRGM_0 + Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + 0 + + + NO_PRGM_1 + Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + 0x1 + + + + + UNUSED2 + This bit is unused. Ignore. + 2 + 1 + read-write + + + + + INT_CTRL + Interrupt Control Register + 0xA4 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding bit of INT_STATUS register cleared. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS register active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_MASK + Mask Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding interrupt of INT_STATUS is masked. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS is active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_STATUS + Interrupt Status Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_ERR + Read: Error status + 0 + 1 + read-only + + + HW_ERR_0 + no error + 0 + + + HW_ERR_1 + error detected. + 0x1 + + + + + ENT_VAL + Read only: Entropy Valid + 1 + 1 + read-only + + + ENT_VAL_0 + Busy generation entropy. Any value read is invalid. + 0 + + + ENT_VAL_1 + TRNG can be stopped and entropy is valid if read. + 0x1 + + + + + FRQ_CT_FAIL + Read only: Frequency Count Fail + 2 + 1 + read-only + + + FRQ_CT_FAIL_0 + No hardware nor self test frequency errors. + 0 + + + FRQ_CT_FAIL_1 + The frequency counter has detected a failure. + 0x1 + + + + + + + VID1 + Version ID Register (MS) + 0xF0 + 32 + read-only + 0x300301 + 0xFFFFFFFF + + + MIN_REV + Shows the IP's Minor revision of the TRNG. + 0 + 8 + read-only + + + MIN_REV_0 + Minor revision number for TRNG. + 0 + + + + + MAJ_REV + Shows the IP's Major revision of the TRNG. + 8 + 8 + read-only + + + MAJ_REV_1 + Major revision number for TRNG. + 0x1 + + + + + IP_ID + Shows the IP ID. + 16 + 16 + read-only + + + IP_ID_48 + ID for TRNG. + 0x30 + + + + + + + VID2 + Version ID Register (LS) + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + Shows the IP's Configuaration options for the TRNG. + 0 + 8 + read-only + + + CONFIG_OPT_0 + TRNG_CONFIG_OPT for TRNG. + 0 + + + + + ECO_REV + Shows the IP's ECO revision of the TRNG. + 8 + 8 + read-only + + + ECO_REV_0 + TRNG_ECO_REV for TRNG. + 0 + + + + + INTG_OPT + Shows the integration options for the TRNG. + 16 + 8 + read-only + + + INTG_OPT_0 + INTG_OPT for TRNG. + 0 + + + + + ERA + Shows the compile options for the TRNG. + 24 + 8 + read-only + + + ERA_0 + COMPILE_OPT for TRNG. + 0 + + + + + + + + + SNVS + SNVS + SNVS + 0x400D4000 + + 0 + 0x10000 + registers + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WSL + Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WSL_0 + Write access is allowed + 0 + + + ZMK_WSL_1 + Write access is not allowed + 0x1 + + + + + ZMK_RSL + Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RSL_0 + Read access is allowed (only in software Programming mode) + 0 + + + ZMK_RSL_1 + Read access is not allowed + 0x1 + + + + + SRTC_SL + Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_SL_0 + Write access is allowed + 0 + + + SRTC_SL_1 + Write access is not allowed + 0x1 + + + + + LPCALB_SL + LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_SL_0 + Write access is allowed + 0 + + + LPCALB_SL_1 + Write access is not allowed + 0x1 + + + + + MC_SL + Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_SL_0 + Write access (increment) is allowed + 0 + + + MC_SL_1 + Write access (increment) is not allowed + 0x1 + + + + + GPR_SL + General Purpose Register Soft Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_SL_0 + Write access is allowed + 0 + + + GPR_SL_1 + Write access is not allowed + 0x1 + + + + + LPSVCR_SL + LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_SL_0 + Write access is allowed + 0 + + + LPSVCR_SL_1 + Write access is not allowed + 0x1 + + + + + LPTDCR_SL + LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_SL_0 + Write access is allowed + 0 + + + LPTDCR_SL_1 + Write access is not allowed + 0x1 + + + + + MKS_SL + Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR + 9 + 1 + read-write + + + MKS_SL_0 + Write access is allowed + 0 + + + MKS_SL_1 + Write access is not allowed + 0x1 + + + + + HPSVCR_L + HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR + 16 + 1 + read-write + + + HPSVCR_L_0 + Write access is allowed + 0 + + + HPSVCR_L_1 + Write access is not allowed + 0x1 + + + + + HPSICR_L + HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR + 17 + 1 + read-write + + + HPSICR_L_0 + Write access is allowed + 0 + + + HPSICR_L_1 + Write access is not allowed + 0x1 + + + + + HAC_L + High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR + 18 + 1 + read-write + + + HAC_L_0 + Write access is allowed + 0 + + + HAC_L_1 + Write access is not allowed + 0x1 + + + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSM_ST + SSM State Transition Transition state of the system security monitor + 0 + 1 + write-only + + + SSM_ST_DIS + SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state + 1 + 1 + read-write + + + SSM_ST_DIS_0 + Secure to Trusted State transition is enabled + 0 + + + SSM_ST_DIS_1 + Secure to Trusted State transition is disabled + 0x1 + + + + + SSM_SFNS_DIS + SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state + 2 + 1 + read-write + + + SSM_SFNS_DIS_0 + Soft Fail to Non-Secure State transition is enabled + 0 + + + SSM_SFNS_DIS_1 + Soft Fail to Non-Secure State transition is disabled + 0x1 + + + + + LP_SWR + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set + 4 + 1 + write-only + + + LP_SWR_0 + No Action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, disables the LP software reset + 5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled + 0x1 + + + + + SW_SV + Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation + 8 + 1 + read-write + + + SW_FSV + Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation + 9 + 1 + read-write + + + SW_LPSV + LP Software Security Violation When set, SNVS_LP treats this bit as a security violation + 10 + 1 + read-write + + + PROG_ZMK + Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism + 12 + 1 + write-only + + + PROG_ZMK_0 + No Action + 0 + + + PROG_ZMK_1 + Activate hardware key programming mechanism + 0x1 + + + + + MKS_EN + Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default + 13 + 1 + read-write + + + MKS_EN_0 + OTP master key is selected as an SNVS master key + 0 + + + MKS_EN_1 + SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + 0x1 + + + + + HAC_EN + High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state + 16 + 1 + read-write + + + HAC_EN_0 + High Assurance Counter is disabled + 0 + + + HAC_EN_1 + High Assurance Counter is enabled + 0x1 + + + + + HAC_LOAD + High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register + 17 + 1 + write-only + + + HAC_LOAD_0 + No Action + 0 + + + HAC_LOAD_1 + Load the HAC + 0x1 + + + + + HAC_CLEAR + High Assurance Counter Clear When set, it clears the High Assurance Counter Register + 18 + 1 + write-only + + + HAC_CLEAR_0 + No Action + 0 + + + HAC_CLEAR_1 + Clear the HAC + 0x1 + + + + + HAC_STOP + High Assurance Counter Stop This bit can be set only when SSM is in soft fail state + 19 + 1 + read-write + + + NPSWA_EN + Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled + 0 + + + RTC_EN_1 + RTC is enabled + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter + 1 + 1 + read-write + + + HPTA_EN_0 + HP Time Alarm Interrupt is disabled + 0 + + + HPTA_EN_1 + HP Time Alarm Interrupt is enabled + 0x1 + + + + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled + 3 + 1 + read-write + + + PI_EN_0 + HP Periodic Interrupt is disabled + 0 + + + PI_EN_1 + HP Periodic Interrupt is enabled + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines frequency of the periodic interrupt + 4 + 4 + read-write + + + PI_FREQ_0 + - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + 0 + + + PI_FREQ_1 + - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + 0x1 + + + PI_FREQ_2 + - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + 0x2 + + + PI_FREQ_3 + - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + 0x3 + + + PI_FREQ_4 + - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + 0x4 + + + PI_FREQ_5 + - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + 0x5 + + + PI_FREQ_6 + - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + 0x6 + + + PI_FREQ_7 + - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + 0x7 + + + PI_FREQ_8 + - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + 0x8 + + + PI_FREQ_9 + - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + 0x9 + + + PI_FREQ_10 + - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + 0xA + + + PI_FREQ_11 + - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + 0xB + + + PI_FREQ_12 + - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + 0xC + + + PI_FREQ_13 + - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + 0xD + + + PI_FREQ_14 + - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + 0xE + + + PI_FREQ_15 + - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + 0xF + + + + + HPCALB_EN + HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. + 8 + 1 + read-write + + + HPCALB_EN_0 + HP Timer calibration disabled + 0 + + + HPCALB_EN_1 + HP Timer calibration enabled + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines signed calibration value for the HP Real Time Counter + 10 + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + HP_TS + HP Time Synchronize + 16 + 1 + read-write + + + HP_TS_0 + No Action + 0 + + + HP_TS_1 + Synchronize the HP Time Counter to the LP Time Counter + 0x1 + + + + + BTN_CONFIG + Button Configuration + 24 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 27 + 1 + read-write + + + + + HPSICR + SNVS_HP Security Interrupt Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 Interrupt is Disabled + 0 + + + SV0_EN_1 + Security Violation 0 Interrupt is Enabled + 0x1 + + + + + SV1_EN + Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 Interrupt is Disabled + 0 + + + SV1_EN_1 + Security Violation 1 Interrupt is Enabled + 0x1 + + + + + SV2_EN + Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 Interrupt is Disabled + 0 + + + SV2_EN_1 + Security Violation 2 Interrupt is Enabled + 0x1 + + + + + SV3_EN + Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 Interrupt is Disabled + 0 + + + SV3_EN_1 + Security Violation 3 Interrupt is Enabled + 0x1 + + + + + SV4_EN + Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 Interrupt is Disabled + 0 + + + SV4_EN_1 + Security Violation 4 Interrupt is Enabled + 0x1 + + + + + SV5_EN + Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 Interrupt is Disabled + 0 + + + SV5_EN_1 + Security Violation 5 Interrupt is Enabled + 0x1 + + + + + LPSVI_EN + LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section + 31 + 1 + read-write + + + LPSVI_EN_0 + LP Security Violation Interrupt is Disabled + 0 + + + LPSVI_EN_1 + LP Security Violation Interrupt is Enabled + 0x1 + + + + + + + HPSVCR + SNVS_HP Security Violation Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_CFG + Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input + 0 + 1 + read-write + + + SV0_CFG_0 + Security Violation 0 is a non-fatal violation + 0 + + + SV0_CFG_1 + Security Violation 0 is a fatal violation + 0x1 + + + + + SV1_CFG + Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input + 1 + 1 + read-write + + + SV1_CFG_0 + Security Violation 1 is a non-fatal violation + 0 + + + SV1_CFG_1 + Security Violation 1 is a fatal violation + 0x1 + + + + + SV2_CFG + Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input + 2 + 1 + read-write + + + SV2_CFG_0 + Security Violation 2 is a non-fatal violation + 0 + + + SV2_CFG_1 + Security Violation 2 is a fatal violation + 0x1 + + + + + SV3_CFG + Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input + 3 + 1 + read-write + + + SV3_CFG_0 + Security Violation 3 is a non-fatal violation + 0 + + + SV3_CFG_1 + Security Violation 3 is a fatal violation + 0x1 + + + + + SV4_CFG + Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input + 4 + 1 + read-write + + + SV4_CFG_0 + Security Violation 4 is a non-fatal violation + 0 + + + SV4_CFG_1 + Security Violation 4 is a fatal violation + 0x1 + + + + + SV5_CFG + Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input + 5 + 2 + read-write + + + SV5_CFG_0 + Security Violation 5 is disabled + 0 + + + SV5_CFG_1 + Security Violation 5 is a non-fatal violation + 0x1 + + + SV5_CFG_2 + Security Violation 5 is a fatal violation + #1x + + + + + LPSV_CFG + LP Security Violation Configuration This field configures the LP security violation source. + 30 + 2 + read-write + + + LPSV_CFG_0 + LP security violation is disabled + 0 + + + LPSV_CFG_1 + LP security violation is a non-fatal violation + 0x1 + + + LPSV_CFG_2 + LP security violation is a fatal violation + #1x + + + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x80003000 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. + 0 + 1 + read-write + oneToClear + + + HPTA_0 + No time alarm interrupt occurred. + 0 + + + HPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + PI + Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. + 1 + 1 + read-write + oneToClear + + + PI_0 + No periodic interrupt occurred. + 0 + + + PI_1 + A periodic interrupt occurred. + 0x1 + + + + + LPDIS + Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS + 4 + 1 + read-only + + + BTN + Button Value of the BTN input + 6 + 1 + read-only + + + BI + Button Interrupt Signal ipi_snvs_btn_int_b was asserted. + 7 + 1 + read-write + oneToClear + + + SSM_STATE + System Security Monitor State This field contains the encoded state of the SSM's state machine + 8 + 4 + read-only + + + SSM_STATE_0 + Init + 0 + + + SSM_STATE_1 + Hard Fail + 0x1 + + + SSM_STATE_3 + Soft Fail + 0x3 + + + SSM_STATE_8 + Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + 0x8 + + + SSM_STATE_9 + Check + 0x9 + + + SSM_STATE_11 + Non-Secure + 0xB + + + SSM_STATE_13 + Trusted + 0xD + + + SSM_STATE_15 + Secure + 0xF + + + + + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS + 12 + 4 + read-only + + + FAB_CONFIG + FAB configuration + 0 + + + OPEN_CONFIG + OPEN configuration + 0x1 + + + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration + 0x3 + + + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB + + + + + OTPMK_SYNDROME + One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location + 16 + 9 + read-only + + + OTPMK_ZERO + One Time Programmable Master Key is Equal to Zero + 27 + 1 + read-only + + + OTPMK_ZERO_0 + The OTPMK is not zero. + 0 + + + OTPMK_ZERO_1 + The OTPMK is zero. + 0x1 + + + + + ZMK_ZERO + Zeroizable Master Key is Equal to Zero + 31 + 1 + read-only + + + ZMK_ZERO_0 + The ZMK is not zero. + 0 + + + ZMK_ZERO_1 + The ZMK is zero. + 0x1 + + + + + + + HPSVSR + SNVS_HP Security Violation Status Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + SV0 + Security Violation 0 security violation was detected. + 0 + 1 + read-write + oneToClear + + + SV0_0 + No Security Violation 0 security violation was detected. + 0 + + + SV0_1 + Security Violation 0 security violation was detected. + 0x1 + + + + + SV1 + Security Violation 1 security violation was detected. + 1 + 1 + read-write + oneToClear + + + SV1_0 + No Security Violation 1 security violation was detected. + 0 + + + SV1_1 + Security Violation 1 security violation was detected. + 0x1 + + + + + SV2 + Security Violation 2 security violation was detected. + 2 + 1 + read-write + oneToClear + + + SV2_0 + No Security Violation 2 security violation was detected. + 0 + + + SV2_1 + Security Violation 2 security violation was detected. + 0x1 + + + + + SV3 + Security Violation 3 security violation was detected. + 3 + 1 + read-write + oneToClear + + + SV3_0 + No Security Violation 3 security violation was detected. + 0 + + + SV3_1 + Security Violation 3 security violation was detected. + 0x1 + + + + + SV4 + Security Violation 4 security violation was detected. + 4 + 1 + read-write + oneToClear + + + SV4_0 + No Security Violation 4 security violation was detected. + 0 + + + SV4_1 + Security Violation 4 security violation was detected. + 0x1 + + + + + SV5 + Security Violation 5 security violation was detected. + 5 + 1 + read-write + oneToClear + + + SV5_0 + No Security Violation 5 security violation was detected. + 0 + + + SV5_1 + Security Violation 5 security violation was detected. + 0x1 + + + + + SW_SV + Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register + 13 + 1 + read-only + + + SW_FSV + Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register + 14 + 1 + read-only + + + SW_LPSV + LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register + 15 + 1 + read-only + + + ZMK_SYNDROME + Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register + 16 + 9 + read-only + + + ZMK_ECC_FAIL + Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data + 27 + 1 + read-write + oneToClear + + + ZMK_ECC_FAIL_0 + ZMK ECC Failure was not detected. + 0 + + + ZMK_ECC_FAIL_1 + ZMK ECC Failure was detected. + 0x1 + + + + + LP_SEC_VIO + LP Security Violation A security volation was detected in the SNVS low power section. + 31 + 1 + read-only + + + + + HPHACIVR + SNVS_HP High Assurance Counter IV Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAC_COUNTER_IV + High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter + 0 + 32 + read-write + + + + + HPHACR + SNVS_HP High Assurance Counter Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + HAC_COUNTER + High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock + 0 + 32 + read-only + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter The most-significant 15 bits of the RTC + 0 + 15 + read-write + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter least-significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_MS + HP Time Alarm, most-significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_LS + HP Time Alarm, 32 least-significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WHL + Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WHL_0 + Write access is allowed. + 0 + + + ZMK_WHL_1 + Write access is not allowed. + 0x1 + + + + + ZMK_RHL + Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RHL_0 + Read access is allowed (only in software programming mode). + 0 + + + ZMK_RHL_1 + Read access is not allowed. + 0x1 + + + + + SRTC_HL + Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_HL_0 + Write access is allowed. + 0 + + + SRTC_HL_1 + Write access is not allowed. + 0x1 + + + + + LPCALB_HL + LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_HL_0 + Write access is allowed. + 0 + + + LPCALB_HL_1 + Write access is not allowed. + 0x1 + + + + + MC_HL + Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General Purpose Register Hard Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPSVCR_HL + LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_HL_0 + Write access is allowed. + 0 + + + LPSVCR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPTDCR_HL + LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_HL_0 + Write access is allowed. + 0 + + + LPTDCR_HL_1 + Write access is not allowed. + 0x1 + + + + + MKS_HL + Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register + 9 + 1 + read-write + + + MKS_HL_0 + Write access is allowed. + 0 + + + MKS_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + SRTC_ENV + Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational + 0 + 1 + read-write + + + SRTC_ENV_0 + SRTC is disabled or invalid. + 0 + + + SRTC_ENV_1 + SRTC is enabled and valid. + 0x1 + + + + + LPTA_EN + LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter + 1 + 1 + read-write + + + LPTA_EN_0 + LP time alarm interrupt is disabled. + 0 + + + LPTA_EN_1 + LP time alarm interrupt is enabled. + 0x1 + + + + + MC_ENV + Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) + 2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + LPWUI_EN + LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) + 3 + 1 + read-write + + + SRTC_INV_EN + If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) + 4 + 1 + read-write + + + SRTC_INV_EN_0 + SRTC stays valid in the case of security violation. + 0 + + + SRTC_INV_EN_1 + SRTC is invalidated in the case of security violation. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, software can control the system power + 5 + 1 + read-write + + + DP_EN_0 + Smart PMIC enabled. + 0 + + + DP_EN_1 + Dumb PMIC enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power + 6 + 1 + read-write + + + TOP_0 + Leave system power on. + 0 + + + TOP_1 + Turn off system power. + 0x1 + + + + + PWR_GLITCH_EN + Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 7 + 1 + read-write + + + LPCALB_EN + LP Calibration Enable When set, enables the SRTC calibration mechanism + 8 + 1 + read-write + + + LPCALB_EN_0 + SRTC Time calibration is disabled. + 0 + + + LPCALB_EN_1 + SRTC Time calibration is enabled. + 0x1 + + + + + LPCALB_VAL + LP Calibration Value Defines signed calibration value for SRTC + 10 + 5 + read-write + + + LPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter clock + 0 + + + LPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter clock + 0x1 + + + LPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter clock + 0x2 + + + LPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter clock + 0xF + + + LPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter clock + 0x10 + + + LPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter clock + 0x11 + + + LPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter clock + 0x1E + + + LPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter clock + 0x1F + + + + + BTN_PRESS_TIME + This field configures the button press time out values for the PMIC Logic + 16 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 18 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power + 20 + 2 + read-write + + + PK_EN + PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en + 22 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override + 23 + 1 + read-write + + + GPR_Z_DIS + General Purpose Registers Zeroization Disable + 24 + 1 + read-write + + + + + LPMKCR + SNVS_LP Master Key Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER_KEY_SEL + Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR + 0 + 2 + read-write + + + MASTER_KEY_SEL_0 + Select one time programmable master key. + #0x + + + MASTER_KEY_SEL_2 + Select zeroizable master key when MKS_EN bit is set . + 0x2 + + + MASTER_KEY_SEL_3 + Select combined master key when MKS_EN bit is set . + 0x3 + + + + + ZMK_HWP + Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it + 2 + 1 + read-write + + + ZMK_HWP_0 + ZMK is in the software programming mode. + 0 + + + ZMK_HWP_1 + ZMK is in the hardware programming mode. + 0x1 + + + + + ZMK_VAL + Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules + 3 + 1 + read-write + + + ZMK_VAL_0 + ZMK is not valid. + 0 + + + ZMK_VAL_1 + ZMK is valid. + 0x1 + + + + + ZMK_ECC_EN + Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register + 4 + 1 + read-write + + + ZMK_ECC_EN_0 + ZMK ECC check is disabled. + 0 + + + ZMK_ECC_EN_1 + ZMK ECC check is enabled. + 0x1 + + + + + ZMK_ECC_VALUE + Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register + 7 + 9 + read-only + + + + + LPSVCR + SNVS_LP Security Violation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Enable This bit enables Security Violation 0 Input + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 is disabled in the LP domain. + 0 + + + SV0_EN_1 + Security Violation 0 is enabled in the LP domain. + 0x1 + + + + + SV1_EN + Security Violation 1 Enable This bit enables Security Violation 1 Input + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 is disabled in the LP domain. + 0 + + + SV1_EN_1 + Security Violation 1 is enabled in the LP domain. + 0x1 + + + + + SV2_EN + Security Violation 2 Enable This bit enables Security Violation 2 Input + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 is disabled in the LP domain. + 0 + + + SV2_EN_1 + Security Violation 2 is enabled in the LP domain. + 0x1 + + + + + SV3_EN + Security Violation 3 Enable This bit enables Security Violation 3 Input + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 is disabled in the LP domain. + 0 + + + SV3_EN_1 + Security Violation 3 is enabled in the LP domain. + 0x1 + + + + + SV4_EN + Security Violation 4 Enable This bit enables Security Violation 4 Input + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 is disabled in the LP domain. + 0 + + + SV4_EN_1 + Security Violation 4 is enabled in the LP domain. + 0x1 + + + + + SV5_EN + Security Violation 5 Enable This bit enables Security Violation 5 Input + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 is disabled in the LP domain. + 0 + + + SV5_EN_1 + Security Violation 5 is enabled in the LP domain. + 0x1 + + + + + + + LPTDCR + SNVS_LP Tamper Detectors Configuration Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTCR_EN + SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. + 1 + 1 + read-write + + + SRTCR_EN_0 + SRTC rollover is disabled. + 0 + + + SRTCR_EN_1 + SRTC rollover is enabled. + 0x1 + + + + + MCR_EN + MC Rollover Enable When set, an MC Rollover event generates an LP security violation. + 2 + 1 + read-write + + + MCR_EN_0 + MC rollover is disabled. + 0 + + + MCR_EN_1 + MC rollover is enabled. + 0x1 + + + + + ET1_EN + External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation + 9 + 1 + read-write + + + ET1_EN_0 + External tamper 1 is disabled. + 0 + + + ET1_EN_1 + External tamper 1 is enabled. + 0x1 + + + + + ET1P + External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. + 11 + 1 + read-write + + + ET1P_0 + External tamper 1 is active low. + 0 + + + ET1P_1 + External tamper 1 is active high. + 0x1 + + + + + PFD_OBSERV + System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) + 14 + 1 + read-write + + + POR_OBSERV + Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS + 15 + 1 + read-write + + + OSCB + Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted + 28 + 1 + read-write + + + OSCB_0 + Normal SRTC clock oscillator not bypassed. + 0 + + + OSCB_1 + Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + 0x1 + + + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + LP Time Alarm + 0 + 1 + read-write + oneToClear + + + LPTA_0 + No time alarm interrupt occurred. + 0 + + + LPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + SRTCR + Secure Real Time Counter Rollover + 1 + 1 + read-write + oneToClear + + + SRTCR_0 + SRTC has not reached its maximum value. + 0 + + + SRTCR_1 + SRTC has reached its maximum value. + 0x1 + + + + + MCR + Monotonic Counter Rollover + 2 + 1 + read-write + oneToClear + + + MCR_0 + MC has not reached its maximum value. + 0 + + + MCR_1 + MC has reached its maximum value. + 0x1 + + + + + PGD + Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected. + 3 + 1 + read-write + oneToClear + + + ET1D + External Tampering 1 Detected + 9 + 1 + read-write + oneToClear + + + ET1D_0 + External tampering 1 not detected. + 0 + + + ET1D_1 + External tampering 1 detected. + 0x1 + + + + + ESVD + External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports + 16 + 1 + read-write + oneToClear + + + ESVD_0 + No external security violation. + 0 + + + ESVD_1 + External security violation is detected. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 17 + 1 + read-write + oneToClear + + + EO_0 + Emergency off was not detected. + 0 + + + EO_1 + Emergency off was detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time + 18 + 1 + read-write + oneToClear + + + SPO_0 + Set Power Off was not detected. + 0 + + + SPO_1 + Set Power Off was detected. + 0x1 + + + + + SED + Scan Exit Detected + 20 + 1 + read-write + oneToClear + + + SED_0 + Scan exit was not detected. + 0 + + + SED_1 + Scan exit was detected. + 0x1 + + + + + LPNS + LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state + 30 + 1 + read-only + + + LPNS_0 + LP section was not programmed in the non-secure state. + 0 + + + LPNS_1 + LP section was programmed in the non-secure state. + 0x1 + + + + + LPS + LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state + 31 + 1 + read-only + + + LPS_0 + LP section was not programmed in secure or trusted state. + 0 + + + LPS_1 + LP section was programmed in secure or trusted state. + 0x1 + + + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter The most-significant 15 bits of the SRTC + 0 + 15 + read-write + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected + 0 + 16 + read-only + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses + 16 + 16 + read-only + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected + 0 + 32 + read-only + + + + + LPPGDR + SNVS_LP Power Glitch Detector Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PGD + Power Glitch Detector Value + 0 + 32 + read-write + + + + + LPGPR0_legacy_alias + SNVS_LP General Purpose Register 0 (legacy alias) + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPZMKR[%s] + SNVS_LP Zeroizable Master Key Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK + Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR_alias[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0104 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 8 + 8 + read-only + + + IP_ID + SNVS block ID + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Options + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 8 + 8 + read-only + + + INTG_OPT + SNVS Integration Options + 16 + 8 + read-only + + + IP_ERA + IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 + 24 + 8 + read-only + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x400D8000 + + 0 + 0x180 + registers + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + Enable bit + 15 + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 16 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_500M_REF_EN + Enable the PLL providing ENET 500 MHz reference clock + 22 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_500M_REF_EN + Enable the PLL providing ENET 500 MHz reference clock + 22 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_500M_REF_EN + Enable the PLL providing ENET 500 MHz reference clock + 22 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET_500M_REF_EN + Enable the PLL providing ENET 500 MHz reference clock + 22 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + + + PMU + PMU + CCM_ANALOG + PMU + PMU_ + 0x400D8000 + + 0 + 0x180 + registers + + + PMU + 61 + + + + REG_1P1 + Regulator 1P1 Register + 0x110 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_SET + Regulator 1P1 Register + 0x114 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_CLR + Regulator 1P1 Register + 0x118 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_TOG + Regulator 1P1 Register + 0x11C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x120 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_SET + Regulator 3P0 Register + 0x124 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_CLR + Regulator 3P0 Register + 0x128 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_TOG + Regulator 3P0 Register + 0x12C + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x130 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_SET + Regulator 2P5 Register + 0x134 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_CLR + Regulator 2P5 Register + 0x138 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_TOG + Regulator 2P5 Register + 0x13C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x140 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_SET + Digital Regulator Core Register + 0x144 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_CLR + Digital Regulator Core Register + 0x148 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_TOG + Digital Regulator Core Register + 0x14C + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + + + + + TEMPMON + Temperature Monitor + CCM_ANALOG + TEMPMON + TEMPMON_ + 0x400D8000 + + 0 + 0x2A0 + registers + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0x180 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x184 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x188 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0x18C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x190 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x194 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x198 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x19C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + CCM_ANALOG + USB_ANALOG + USB_ANALOG_ + 0x400D8000 + + 0 + 0x264 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0x1A0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x1A4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x1A8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x1AC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x1C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x1D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB1_MISC + USB Misc Register + 0x1F0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x1F4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x1F8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x1FC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0x260 + 32 + read-only + 0x620002 + 0xFFFFFFFF + + + SILICON_REVISION + Chip silicon revision + 0 + 32 + read-only + + + SILICON_REVISION_6422530 + Silicon revision 1.0 + 0x620002 + + + + + + + + + XTALOSC24M + XTALOSC24M + CCM_ANALOG + XTALOSC24M + XTALOSC24M_ + 0x400D8000 + + 0 + 0x2D0 + registers + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + LOWPWR_CTRL + XTAL OSC (LP) Control Register + 0x270 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_SET + XTAL OSC (LP) Control Register + 0x274 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + XTAL OSC (LP) Control Register + 0x278 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + XTAL OSC (LP) Control Register + 0x27C + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0x2A0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x2A4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x2A8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0x2AC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x2B0 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x2B4 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x2B8 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x2BC + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x2C0 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x2C4 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x2C8 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2CC + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + + + USBPHY + USBPHY Register Reference Index + USBPHY + USBPHY_ + 0x400D9000 + + 0 + 0x84 + registers + + + USB_PHY + 65 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 3 + 1 + read-only + + + RSVD1 + Reserved. + 4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 6 + 1 + read-only + + + RSVD2 + Reserved. + 7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 8 + 1 + read-write + + + RSVD3 + Reserved. + 9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 10 + 1 + read-only + + + RSVD4 + Reserved. + 11 + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 16 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 26 + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4030000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + + + CSU + CSU registers + CSU + CSU_ + 0x400DC000 + + 0 + 0x35C + registers + + + CSU + 49 + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + CSL%s + Config security level register + 0 + 32 + read-write + 0x330033 + 0xFFFFFFFF + + + SUR_S2 + Secure user read access control for the second slave + 0 + 1 + read-write + + + SUR_S2_0 + The secure user read access is disabled for the second slave. + 0 + + + SUR_S2_1 + The secure user read access is enabled for the second slave. + 0x1 + + + + + SSR_S2 + Secure supervisor read access control for the second slave + 1 + 1 + read-write + + + SSR_S2_0 + The secure supervisor read access is disabled for the second slave. + 0 + + + SSR_S2_1 + The secure supervisor read access is enabled for the second slave. + 0x1 + + + + + NUR_S2 + Non-secure user read access control for the second slave + 2 + 1 + read-write + + + NUR_S2_0 + The non-secure user read access is disabled for the second slave. + 0 + + + NUR_S2_1 + The non-secure user read access is enabled for the second slave. + 0x1 + + + + + NSR_S2 + Non-secure supervisor read access control for the second slave + 3 + 1 + read-write + + + NSR_S2_0 + The non-secure supervisor read access is disabled for the second slave. + 0 + + + NSR_S2_1 + The non-secure supervisor read access is enabled for the second slave. + 0x1 + + + + + SUW_S2 + Secure user write access control for the second slave + 4 + 1 + read-write + + + SUW_S2_0 + The secure user write access is disabled for the second slave. + 0 + + + SUW_S2_1 + The secure user write access is enabled for the second slave. + 0x1 + + + + + SSW_S2 + Secure supervisor write access control for the second slave + 5 + 1 + read-write + + + SSW_S2_0 + The secure supervisor write access is disabled for the second slave. + 0 + + + SSW_S2_1 + The secure supervisor write access is enabled for the second slave. + 0x1 + + + + + NUW_S2 + Non-secure user write access control for the second slave + 6 + 1 + read-write + + + NUW_S2_0 + The non-secure user write access is disabled for the second slave. + 0 + + + NUW_S2_1 + The non-secure user write access is enabled for the second slave. + 0x1 + + + + + NSW_S2 + Non-secure supervisor write access control for the second slave + 7 + 1 + read-write + + + NSW_S2_0 + The non-secure supervisor write access is disabled for the second slave. + 0 + + + NSW_S2_1 + The non-secure supervisor write access is enabled for the second slave. + 0x1 + + + + + LOCK_S2 + The lock bit corresponding to the second slave. It is written by the secure software. + 8 + 1 + read-write + + + LOCK_S2_0 + Not locked. Bits 7-0 can be written by the software. + 0 + + + LOCK_S2_1 + Bits 7-0 are locked and cannot be written by the software + 0x1 + + + + + SUR_S1 + Secure user read access control for the first slave + 16 + 1 + read-write + + + SUR_S1_0 + The secure user read access is disabled for the first slave. + 0 + + + SUR_S1_1 + The secure user read access is enabled for the first slave. + 0x1 + + + + + SSR_S1 + Secure supervisor read access control for the first slave + 17 + 1 + read-write + + + SSR_S1_0 + The secure supervisor read access is disabled for the first slave. + 0 + + + SSR_S1_1 + The secure supervisor read access is enabled for the first slave. + 0x1 + + + + + NUR_S1 + Non-secure user read access control for the first slave + 18 + 1 + read-write + + + NUR_S1_0 + The non-secure user read access is disabled for the first slave. + 0 + + + NUR_S1_1 + The non-secure user read access is enabled for the first slave. + 0x1 + + + + + NSR_S1 + Non-secure supervisor read access control for the first slave + 19 + 1 + read-write + + + NSR_S1_0 + The non-secure supervisor read access is disabled for the first slave. + 0 + + + NSR_S1_1 + The non-secure supervisor read access is enabled for the first slave. + 0x1 + + + + + SUW_S1 + Secure user write access control for the first slave + 20 + 1 + read-write + + + SUW_S1_0 + The secure user write access is disabled for the first slave. + 0 + + + SUW_S1_1 + The secure user write access is enabled for the first slave. + 0x1 + + + + + SSW_S1 + Secure supervisor write access control for the first slave + 21 + 1 + read-write + + + SSW_S1_0 + The secure supervisor write access is disabled for the first slave. + 0 + + + SSW_S1_1 + The secure supervisor write access is enabled for the first slave. + 0x1 + + + + + NUW_S1 + Non-secure user write access control for the first slave + 22 + 1 + read-write + + + NUW_S1_0 + The non-secure user write access is disabled for the first slave. + 0 + + + NUW_S1_1 + The non-secure user write access is enabled for the first slave. + 0x1 + + + + + NSW_S1 + Non-secure supervisor write access control for the first slave + 23 + 1 + read-write + + + NSW_S1_0 + The non-secure supervisor write access is disabled for the first slave. + 0 + + + NSW_S1_1 + The non-secure supervisor write access is enabled for the first slave + 0x1 + + + + + LOCK_S1 + The lock bit corresponding to the first slave. It is written by the secure software. + 24 + 1 + read-write + + + LOCK_S1_0 + Not locked. The bits 16-23 can be written by the software. + 0 + + + LOCK_S1_1 + The bits 16-23 are locked and can't be written by the software. + 0x1 + + + + + + + HP0 + HP0 register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_DMA + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA + 2 + 1 + read-write + + + HP_DMA_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DMA_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_LCDIF + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF + 4 + 1 + read-write + + + HP_LCDIF_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_LCDIF_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_CSI + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI + 6 + 1 + read-write + + + HP_CSI_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_CSI_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_PXP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP + 8 + 1 + read-write + + + HP_PXP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_PXP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_DCP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP + 10 + 1 + read-write + + + HP_DCP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DCP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit cannot be written by the software. + 0x1 + + + + + HP_ENET + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET + 14 + 1 + read-write + + + HP_ENET_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_ENET_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC1 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1 + 16 + 1 + read-write + + + HP_USDHC1_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC1_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC2 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2 + 18 + 1 + read-write + + + HP_USDHC2_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC2_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_TPSMP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP + 20 + 1 + read-write + + + HP_TPSMP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_TPSMP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USB + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB + 22 + 1 + read-write + + + HP_USB_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USB_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + SA + Secure access register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSA_DMA + Non-secure access policy indicator bit + 2 + 1 + read-write + + + NSA_DMA_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DMA_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_LCDIF + Non-secure access policy indicator bit + 4 + 1 + read-write + + + NSA_LCDIF_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_LCDIF_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_CSI + Non-secure access policy indicator bit + 6 + 1 + read-write + + + NSA_CSI_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_CSI_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_PXP + Non-Secure Access Policy indicator bit + 8 + 1 + read-write + + + NSA_PXP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_PXP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_DCP + Non-secure access policy indicator bit + 10 + 1 + read-write + + + NSA_DCP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DCP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_ENET + Non-secure access policy indicator bit + 14 + 1 + read-write + + + NSA_ENET_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_ENET_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET1 and ENET2 + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC1 + Non-secure access policy indicator bit + 16 + 1 + read-write + + + NSA_USDHC1_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC1_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC2 + Non-secure access policy indicator bit + 18 + 1 + read-write + + + NSA_USDHC2_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC2_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_TPSMP + Non-secure access policy indicator bit + 20 + 1 + read-write + + + NSA_TPSMP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_TPSMP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USB + Non-secure access policy indicator bit + 22 + 1 + read-write + + + NSA_USB_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USB_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + HPCONTROL0 + HPCONTROL0 register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_DMA + Indicates the privilege/user mode for the eDMA + 2 + 1 + read-write + + + HPC_DMA_0 + User mode for the corresponding master + 0 + + + HPC_DMA_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_LCDIF + Indicates the privilege/user mode for the LCDIF + 4 + 1 + read-write + + + HPC_LCDIF_0 + User mode for the corresponding master + 0 + + + HPC_LCDIF_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_CSI + Indicates the privilege/user mode for the CSI + 6 + 1 + read-write + + + HPC_CSI_0 + User mode for the corresponding master + 0 + + + HPC_CSI_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_PXP + Indicates the privilege/user mode for the PXP + 8 + 1 + read-write + + + HPC_PXP_0 + User mode for the corresponding master + 0 + + + HPC_PXP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_DCP + Indicates the privilege/user mode for the DCP + 10 + 1 + read-write + + + HPC_DCP_0 + User mode for the corresponding master + 0 + + + HPC_DCP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_ENET + Indicates the privilege/user mode for the ENET + 14 + 1 + read-write + + + HPC_ENET_0 + User mode for the corresponding master + 0 + + + HPC_ENET_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC1 + Indicates the privilege/user mode for the USDHC1 + 16 + 1 + read-write + + + HPC_USDHC1_0 + User mode for the corresponding master + 0 + + + HPC_USDHC1_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC2 + Indicates the privilege/user mode for the USDHC2 + 18 + 1 + read-write + + + HPC_USDHC2_0 + User mode for the corresponding master + 0 + + + HPC_USDHC2_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2. + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_TPSMP + Indicates the privilege/user mode for the TPSMP + 20 + 1 + read-write + + + HPC_TPSMP_0 + User mode for the corresponding master + 0 + + + HPC_TPSMP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP. + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USB + Indicates the privilege/user mode for the USB + 22 + 1 + read-write + + + HPC_USB_0 + User mode for the corresponding master + 0 + + + HPC_USB_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB. + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + + + DMA0 + DMA + DMA + 0x400E8000 + + 0 + 0x1400 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + + CR + Control Register + 0 + 32 + read-write + 0x400 + 0x80FFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + EDBG_0 + When in debug mode, the DMA continues to operate. + 0 + + + EDBG_1 + When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + 0x1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + ERCA_0 + Fixed priority arbitration is used for channel selection within each group. + 0 + + + ERCA_1 + Round robin arbitration is used for channel selection within each group. + 0x1 + + + + + ERGA + Enable Round Robin Group Arbitration + 3 + 1 + read-write + + + ERGA_0 + Fixed priority arbitration is used for selection among the groups. + 0 + + + ERGA_1 + Round robin arbitration is used for selection among the groups. + 0x1 + + + + + HOE + Halt On Error + 4 + 1 + read-write + + + HOE_0 + Normal operation + 0 + + + HOE_1 + Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + 0x1 + + + + + HALT + Halt DMA Operations + 5 + 1 + read-write + + + HALT_0 + Normal operation + 0 + + + HALT_1 + Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + 0x1 + + + + + CLM + Continuous Link Mode + 6 + 1 + read-write + + + CLM_0 + A minor loop channel link made to itself goes through channel arbitration before being activated again. + 0 + + + CLM_1 + A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + 0x1 + + + + + EMLM + Enable Minor Loop Mapping + 7 + 1 + read-write + + + EMLM_0 + Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + 0 + + + EMLM_1 + Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + 0x1 + + + + + GRP0PRI + Channel Group 0 Priority + 8 + 1 + read-write + + + GRP1PRI + Channel Group 1 Priority + 10 + 1 + read-write + + + ECX + Error Cancel Transfer + 16 + 1 + read-write + + + ECX_0 + Normal operation + 0 + + + ECX_1 + Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + 0x1 + + + + + CX + Cancel Transfer + 17 + 1 + read-write + + + CX_0 + Normal operation + 0 + + + CX_1 + Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + 0x1 + + + + + ACTIVE + DMA Active Status + 31 + 1 + read-only + + + ACTIVE_0 + eDMA is idle. + 0 + + + ACTIVE_1 + eDMA is executing a channel. + 0x1 + + + + + + + ES + Error Status Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + DBE_0 + No destination bus error + 0 + + + DBE_1 + The last recorded error was a bus error on a destination write + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + SBE_0 + No source bus error + 0 + + + SBE_1 + The last recorded error was a bus error on a source read + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + SGE_0 + No scatter/gather configuration error + 0 + + + SGE_1 + The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NCE_0 + No NBYTES/CITER configuration error + 0 + + + NCE_1 + The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + DOE_0 + No destination offset configuration error + 0 + + + DOE_1 + The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + DAE_0 + No destination address configuration error + 0 + + + DAE_1 + The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + SOE_0 + No source offset configuration error + 0 + + + SOE_1 + The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + SAE_0 + No source address configuration error. + 0 + + + SAE_1 + The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 8 + 5 + read-only + + + CPE + Channel Priority Error + 14 + 1 + read-only + + + CPE_0 + No channel priority error + 0 + + + CPE_1 + The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + 0x1 + + + + + GPE + Group Priority Error + 15 + 1 + read-only + + + GPE_0 + No group priority error + 0 + + + GPE_1 + The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + 0x1 + + + + + ECX + Transfer Canceled + 16 + 1 + read-only + + + ECX_0 + No canceled transfers + 0 + + + ECX_1 + The last recorded entry was a canceled transfer by the error cancel transfer input + 0x1 + + + + + VLD + VLD + 31 + 1 + read-only + + + VLD_0 + No ERR bits are set. + 0 + + + VLD_1 + At least one ERR bit is set indicating a valid error exists that has not been cleared. + 0x1 + + + + + + + ERQ + Enable Request Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ0 + Enable DMA Request 0 + 0 + 1 + read-write + + + ERQ0_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ0_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ1 + Enable DMA Request 1 + 1 + 1 + read-write + + + ERQ1_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ1_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ2 + Enable DMA Request 2 + 2 + 1 + read-write + + + ERQ2_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ2_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ3 + Enable DMA Request 3 + 3 + 1 + read-write + + + ERQ3_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ3_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ4 + Enable DMA Request 4 + 4 + 1 + read-write + + + ERQ4_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ4_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ5 + Enable DMA Request 5 + 5 + 1 + read-write + + + ERQ5_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ5_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ6 + Enable DMA Request 6 + 6 + 1 + read-write + + + ERQ6_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ6_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ7 + Enable DMA Request 7 + 7 + 1 + read-write + + + ERQ7_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ7_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ8 + Enable DMA Request 8 + 8 + 1 + read-write + + + ERQ8_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ8_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ9 + Enable DMA Request 9 + 9 + 1 + read-write + + + ERQ9_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ9_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ10 + Enable DMA Request 10 + 10 + 1 + read-write + + + ERQ10_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ10_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ11 + Enable DMA Request 11 + 11 + 1 + read-write + + + ERQ11_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ11_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ12 + Enable DMA Request 12 + 12 + 1 + read-write + + + ERQ12_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ12_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ13 + Enable DMA Request 13 + 13 + 1 + read-write + + + ERQ13_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ13_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ14 + Enable DMA Request 14 + 14 + 1 + read-write + + + ERQ14_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ14_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ15 + Enable DMA Request 15 + 15 + 1 + read-write + + + ERQ15_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ15_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ16 + Enable DMA Request 16 + 16 + 1 + read-write + + + ERQ16_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ16_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ17 + Enable DMA Request 17 + 17 + 1 + read-write + + + ERQ17_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ17_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ18 + Enable DMA Request 18 + 18 + 1 + read-write + + + ERQ18_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ18_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ19 + Enable DMA Request 19 + 19 + 1 + read-write + + + ERQ19_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ19_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ20 + Enable DMA Request 20 + 20 + 1 + read-write + + + ERQ20_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ20_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ21 + Enable DMA Request 21 + 21 + 1 + read-write + + + ERQ21_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ21_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ22 + Enable DMA Request 22 + 22 + 1 + read-write + + + ERQ22_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ22_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ23 + Enable DMA Request 23 + 23 + 1 + read-write + + + ERQ23_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ23_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ24 + Enable DMA Request 24 + 24 + 1 + read-write + + + ERQ24_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ24_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ25 + Enable DMA Request 25 + 25 + 1 + read-write + + + ERQ25_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ25_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ26 + Enable DMA Request 26 + 26 + 1 + read-write + + + ERQ26_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ26_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ27 + Enable DMA Request 27 + 27 + 1 + read-write + + + ERQ27_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ27_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ28 + Enable DMA Request 28 + 28 + 1 + read-write + + + ERQ28_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ28_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ29 + Enable DMA Request 29 + 29 + 1 + read-write + + + ERQ29_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ29_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ30 + Enable DMA Request 30 + 30 + 1 + read-write + + + ERQ30_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ30_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ31 + Enable DMA Request 31 + 31 + 1 + read-write + + + ERQ31_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ31_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + + + EEI + Enable Error Interrupt Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + EEI0 + Enable Error Interrupt 0 + 0 + 1 + read-write + + + EEI0_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI0_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI1 + Enable Error Interrupt 1 + 1 + 1 + read-write + + + EEI1_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI1_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI2 + Enable Error Interrupt 2 + 2 + 1 + read-write + + + EEI2_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI2_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI3 + Enable Error Interrupt 3 + 3 + 1 + read-write + + + EEI3_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI3_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI4 + Enable Error Interrupt 4 + 4 + 1 + read-write + + + EEI4_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI4_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI5 + Enable Error Interrupt 5 + 5 + 1 + read-write + + + EEI5_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI5_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI6 + Enable Error Interrupt 6 + 6 + 1 + read-write + + + EEI6_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI6_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI7 + Enable Error Interrupt 7 + 7 + 1 + read-write + + + EEI7_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI7_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI8 + Enable Error Interrupt 8 + 8 + 1 + read-write + + + EEI8_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI8_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI9 + Enable Error Interrupt 9 + 9 + 1 + read-write + + + EEI9_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI9_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI10 + Enable Error Interrupt 10 + 10 + 1 + read-write + + + EEI10_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI10_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI11 + Enable Error Interrupt 11 + 11 + 1 + read-write + + + EEI11_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI11_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI12 + Enable Error Interrupt 12 + 12 + 1 + read-write + + + EEI12_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI12_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI13 + Enable Error Interrupt 13 + 13 + 1 + read-write + + + EEI13_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI13_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI14 + Enable Error Interrupt 14 + 14 + 1 + read-write + + + EEI14_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI14_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI15 + Enable Error Interrupt 15 + 15 + 1 + read-write + + + EEI15_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI15_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI16 + Enable Error Interrupt 16 + 16 + 1 + read-write + + + EEI16_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI16_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI17 + Enable Error Interrupt 17 + 17 + 1 + read-write + + + EEI17_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI17_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI18 + Enable Error Interrupt 18 + 18 + 1 + read-write + + + EEI18_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI18_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI19 + Enable Error Interrupt 19 + 19 + 1 + read-write + + + EEI19_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI19_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI20 + Enable Error Interrupt 20 + 20 + 1 + read-write + + + EEI20_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI20_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI21 + Enable Error Interrupt 21 + 21 + 1 + read-write + + + EEI21_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI21_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI22 + Enable Error Interrupt 22 + 22 + 1 + read-write + + + EEI22_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI22_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI23 + Enable Error Interrupt 23 + 23 + 1 + read-write + + + EEI23_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI23_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI24 + Enable Error Interrupt 24 + 24 + 1 + read-write + + + EEI24_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI24_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI25 + Enable Error Interrupt 25 + 25 + 1 + read-write + + + EEI25_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI25_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI26 + Enable Error Interrupt 26 + 26 + 1 + read-write + + + EEI26_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI26_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI27 + Enable Error Interrupt 27 + 27 + 1 + read-write + + + EEI27_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI27_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI28 + Enable Error Interrupt 28 + 28 + 1 + read-write + + + EEI28_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI28_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI29 + Enable Error Interrupt 29 + 29 + 1 + read-write + + + EEI29_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI29_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI30 + Enable Error Interrupt 30 + 30 + 1 + read-write + + + EEI30_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI30_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI31 + Enable Error Interrupt 31 + 31 + 1 + read-write + + + EEI31_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI31_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + + + CEEI + Clear Enable Error Interrupt Register + 0x18 + 8 + read-write + 0 + 0xFF + + + CEEI + Clear Enable Error Interrupt + 0 + 5 + read-write + + + CAEE + Clear All Enable Error Interrupts + 6 + 1 + read-write + + + CAEE_0 + Clear only the EEI bit specified in the CEEI field + 0 + + + CAEE_1 + Clear all bits in EEI + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SEEI + Set Enable Error Interrupt Register + 0x19 + 8 + read-write + 0 + 0xFF + + + SEEI + Set Enable Error Interrupt + 0 + 5 + read-write + + + SAEE + Sets All Enable Error Interrupts + 6 + 1 + read-write + + + SAEE_0 + Set only the EEI bit specified in the SEEI field. + 0 + + + SAEE_1 + Sets all bits in EEI + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERQ + Clear Enable Request Register + 0x1A + 8 + read-write + 0 + 0xFF + + + CERQ + Clear Enable Request + 0 + 5 + read-write + + + CAER + Clear All Enable Requests + 6 + 1 + read-write + + + CAER_0 + Clear only the ERQ bit specified in the CERQ field + 0 + + + CAER_1 + Clear all bits in ERQ + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SERQ + Set Enable Request Register + 0x1B + 8 + read-write + 0 + 0xFF + + + SERQ + Set Enable Request + 0 + 5 + read-write + + + SAER + Set All Enable Requests + 6 + 1 + read-write + + + SAER_0 + Set only the ERQ bit specified in the SERQ field + 0 + + + SAER_1 + Set all bits in ERQ + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CDNE + Clear DONE Status Bit Register + 0x1C + 8 + read-write + 0 + 0xFF + + + CDNE + Clear DONE Bit + 0 + 5 + read-write + + + CADN + Clears All DONE Bits + 6 + 1 + read-write + + + CADN_0 + Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + 0 + + + CADN_1 + Clears all bits in TCDn_CSR[DONE] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SSRT + Set START Bit Register + 0x1D + 8 + read-write + 0 + 0xFF + + + SSRT + Set START Bit + 0 + 5 + read-write + + + SAST + Set All START Bits (activates all channels) + 6 + 1 + read-write + + + SAST_0 + Set only the TCDn_CSR[START] bit specified in the SSRT field + 0 + + + SAST_1 + Set all bits in TCDn_CSR[START] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERR + Clear Error Register + 0x1E + 8 + read-write + 0 + 0xFF + + + CERR + Clear Error Indicator + 0 + 5 + read-write + + + CAEI + Clear All Error Indicators + 6 + 1 + read-write + + + CAEI_0 + Clear only the ERR bit specified in the CERR field + 0 + + + CAEI_1 + Clear all bits in ERR + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CINT + Clear Interrupt Request Register + 0x1F + 8 + read-write + 0 + 0xFF + + + CINT + Clear Interrupt Request + 0 + 5 + read-write + + + CAIR + Clear All Interrupt Requests + 6 + 1 + read-write + + + CAIR_0 + Clear only the INT bit specified in the CINT field + 0 + + + CAIR_1 + Clear all bits in INT + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + INT + Interrupt Request Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT0 + Interrupt Request 0 + 0 + 1 + read-write + oneToClear + + + INT0_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT0_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT1 + Interrupt Request 1 + 1 + 1 + read-write + oneToClear + + + INT1_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT1_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT2 + Interrupt Request 2 + 2 + 1 + read-write + oneToClear + + + INT2_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT2_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT3 + Interrupt Request 3 + 3 + 1 + read-write + oneToClear + + + INT3_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT3_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT4 + Interrupt Request 4 + 4 + 1 + read-write + oneToClear + + + INT4_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT4_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT5 + Interrupt Request 5 + 5 + 1 + read-write + oneToClear + + + INT5_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT5_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT6 + Interrupt Request 6 + 6 + 1 + read-write + oneToClear + + + INT6_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT6_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT7 + Interrupt Request 7 + 7 + 1 + read-write + oneToClear + + + INT7_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT7_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT8 + Interrupt Request 8 + 8 + 1 + read-write + oneToClear + + + INT8_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT8_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT9 + Interrupt Request 9 + 9 + 1 + read-write + oneToClear + + + INT9_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT9_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT10 + Interrupt Request 10 + 10 + 1 + read-write + oneToClear + + + INT10_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT10_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT11 + Interrupt Request 11 + 11 + 1 + read-write + oneToClear + + + INT11_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT11_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT12 + Interrupt Request 12 + 12 + 1 + read-write + oneToClear + + + INT12_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT12_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT13 + Interrupt Request 13 + 13 + 1 + read-write + oneToClear + + + INT13_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT13_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT14 + Interrupt Request 14 + 14 + 1 + read-write + oneToClear + + + INT14_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT14_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT15 + Interrupt Request 15 + 15 + 1 + read-write + oneToClear + + + INT15_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT15_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT16 + Interrupt Request 16 + 16 + 1 + read-write + oneToClear + + + INT16_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT16_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT17 + Interrupt Request 17 + 17 + 1 + read-write + oneToClear + + + INT17_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT17_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT18 + Interrupt Request 18 + 18 + 1 + read-write + oneToClear + + + INT18_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT18_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT19 + Interrupt Request 19 + 19 + 1 + read-write + oneToClear + + + INT19_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT19_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT20 + Interrupt Request 20 + 20 + 1 + read-write + oneToClear + + + INT20_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT20_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT21 + Interrupt Request 21 + 21 + 1 + read-write + oneToClear + + + INT21_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT21_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT22 + Interrupt Request 22 + 22 + 1 + read-write + oneToClear + + + INT22_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT22_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT23 + Interrupt Request 23 + 23 + 1 + read-write + oneToClear + + + INT23_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT23_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT24 + Interrupt Request 24 + 24 + 1 + read-write + oneToClear + + + INT24_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT24_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT25 + Interrupt Request 25 + 25 + 1 + read-write + oneToClear + + + INT25_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT25_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT26 + Interrupt Request 26 + 26 + 1 + read-write + oneToClear + + + INT26_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT26_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT27 + Interrupt Request 27 + 27 + 1 + read-write + oneToClear + + + INT27_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT27_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT28 + Interrupt Request 28 + 28 + 1 + read-write + oneToClear + + + INT28_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT28_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT29 + Interrupt Request 29 + 29 + 1 + read-write + oneToClear + + + INT29_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT29_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT30 + Interrupt Request 30 + 30 + 1 + read-write + oneToClear + + + INT30_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT30_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT31 + Interrupt Request 31 + 31 + 1 + read-write + oneToClear + + + INT31_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT31_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + + + ERR + Error Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR0 + Error In Channel 0 + 0 + 1 + read-write + oneToClear + + + ERR0_0 + An error in this channel has not occurred + 0 + + + ERR0_1 + An error in this channel has occurred + 0x1 + + + + + ERR1 + Error In Channel 1 + 1 + 1 + read-write + oneToClear + + + ERR1_0 + An error in this channel has not occurred + 0 + + + ERR1_1 + An error in this channel has occurred + 0x1 + + + + + ERR2 + Error In Channel 2 + 2 + 1 + read-write + oneToClear + + + ERR2_0 + An error in this channel has not occurred + 0 + + + ERR2_1 + An error in this channel has occurred + 0x1 + + + + + ERR3 + Error In Channel 3 + 3 + 1 + read-write + oneToClear + + + ERR3_0 + An error in this channel has not occurred + 0 + + + ERR3_1 + An error in this channel has occurred + 0x1 + + + + + ERR4 + Error In Channel 4 + 4 + 1 + read-write + oneToClear + + + ERR4_0 + An error in this channel has not occurred + 0 + + + ERR4_1 + An error in this channel has occurred + 0x1 + + + + + ERR5 + Error In Channel 5 + 5 + 1 + read-write + oneToClear + + + ERR5_0 + An error in this channel has not occurred + 0 + + + ERR5_1 + An error in this channel has occurred + 0x1 + + + + + ERR6 + Error In Channel 6 + 6 + 1 + read-write + oneToClear + + + ERR6_0 + An error in this channel has not occurred + 0 + + + ERR6_1 + An error in this channel has occurred + 0x1 + + + + + ERR7 + Error In Channel 7 + 7 + 1 + read-write + oneToClear + + + ERR7_0 + An error in this channel has not occurred + 0 + + + ERR7_1 + An error in this channel has occurred + 0x1 + + + + + ERR8 + Error In Channel 8 + 8 + 1 + read-write + oneToClear + + + ERR8_0 + An error in this channel has not occurred + 0 + + + ERR8_1 + An error in this channel has occurred + 0x1 + + + + + ERR9 + Error In Channel 9 + 9 + 1 + read-write + oneToClear + + + ERR9_0 + An error in this channel has not occurred + 0 + + + ERR9_1 + An error in this channel has occurred + 0x1 + + + + + ERR10 + Error In Channel 10 + 10 + 1 + read-write + oneToClear + + + ERR10_0 + An error in this channel has not occurred + 0 + + + ERR10_1 + An error in this channel has occurred + 0x1 + + + + + ERR11 + Error In Channel 11 + 11 + 1 + read-write + oneToClear + + + ERR11_0 + An error in this channel has not occurred + 0 + + + ERR11_1 + An error in this channel has occurred + 0x1 + + + + + ERR12 + Error In Channel 12 + 12 + 1 + read-write + oneToClear + + + ERR12_0 + An error in this channel has not occurred + 0 + + + ERR12_1 + An error in this channel has occurred + 0x1 + + + + + ERR13 + Error In Channel 13 + 13 + 1 + read-write + oneToClear + + + ERR13_0 + An error in this channel has not occurred + 0 + + + ERR13_1 + An error in this channel has occurred + 0x1 + + + + + ERR14 + Error In Channel 14 + 14 + 1 + read-write + oneToClear + + + ERR14_0 + An error in this channel has not occurred + 0 + + + ERR14_1 + An error in this channel has occurred + 0x1 + + + + + ERR15 + Error In Channel 15 + 15 + 1 + read-write + oneToClear + + + ERR15_0 + An error in this channel has not occurred + 0 + + + ERR15_1 + An error in this channel has occurred + 0x1 + + + + + ERR16 + Error In Channel 16 + 16 + 1 + read-write + oneToClear + + + ERR16_0 + An error in this channel has not occurred + 0 + + + ERR16_1 + An error in this channel has occurred + 0x1 + + + + + ERR17 + Error In Channel 17 + 17 + 1 + read-write + oneToClear + + + ERR17_0 + An error in this channel has not occurred + 0 + + + ERR17_1 + An error in this channel has occurred + 0x1 + + + + + ERR18 + Error In Channel 18 + 18 + 1 + read-write + oneToClear + + + ERR18_0 + An error in this channel has not occurred + 0 + + + ERR18_1 + An error in this channel has occurred + 0x1 + + + + + ERR19 + Error In Channel 19 + 19 + 1 + read-write + oneToClear + + + ERR19_0 + An error in this channel has not occurred + 0 + + + ERR19_1 + An error in this channel has occurred + 0x1 + + + + + ERR20 + Error In Channel 20 + 20 + 1 + read-write + oneToClear + + + ERR20_0 + An error in this channel has not occurred + 0 + + + ERR20_1 + An error in this channel has occurred + 0x1 + + + + + ERR21 + Error In Channel 21 + 21 + 1 + read-write + oneToClear + + + ERR21_0 + An error in this channel has not occurred + 0 + + + ERR21_1 + An error in this channel has occurred + 0x1 + + + + + ERR22 + Error In Channel 22 + 22 + 1 + read-write + oneToClear + + + ERR22_0 + An error in this channel has not occurred + 0 + + + ERR22_1 + An error in this channel has occurred + 0x1 + + + + + ERR23 + Error In Channel 23 + 23 + 1 + read-write + oneToClear + + + ERR23_0 + An error in this channel has not occurred + 0 + + + ERR23_1 + An error in this channel has occurred + 0x1 + + + + + ERR24 + Error In Channel 24 + 24 + 1 + read-write + oneToClear + + + ERR24_0 + An error in this channel has not occurred + 0 + + + ERR24_1 + An error in this channel has occurred + 0x1 + + + + + ERR25 + Error In Channel 25 + 25 + 1 + read-write + oneToClear + + + ERR25_0 + An error in this channel has not occurred + 0 + + + ERR25_1 + An error in this channel has occurred + 0x1 + + + + + ERR26 + Error In Channel 26 + 26 + 1 + read-write + oneToClear + + + ERR26_0 + An error in this channel has not occurred + 0 + + + ERR26_1 + An error in this channel has occurred + 0x1 + + + + + ERR27 + Error In Channel 27 + 27 + 1 + read-write + oneToClear + + + ERR27_0 + An error in this channel has not occurred + 0 + + + ERR27_1 + An error in this channel has occurred + 0x1 + + + + + ERR28 + Error In Channel 28 + 28 + 1 + read-write + oneToClear + + + ERR28_0 + An error in this channel has not occurred + 0 + + + ERR28_1 + An error in this channel has occurred + 0x1 + + + + + ERR29 + Error In Channel 29 + 29 + 1 + read-write + oneToClear + + + ERR29_0 + An error in this channel has not occurred + 0 + + + ERR29_1 + An error in this channel has occurred + 0x1 + + + + + ERR30 + Error In Channel 30 + 30 + 1 + read-write + oneToClear + + + ERR30_0 + An error in this channel has not occurred + 0 + + + ERR30_1 + An error in this channel has occurred + 0x1 + + + + + ERR31 + Error In Channel 31 + 31 + 1 + read-write + oneToClear + + + ERR31_0 + An error in this channel has not occurred + 0 + + + ERR31_1 + An error in this channel has occurred + 0x1 + + + + + + + HRS + Hardware Request Status Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS0 + Hardware Request Status Channel 0 + 0 + 1 + read-only + + + HRS0_0 + A hardware service request for channel 0 is not present + 0 + + + HRS0_1 + A hardware service request for channel 0 is present + 0x1 + + + + + HRS1 + Hardware Request Status Channel 1 + 1 + 1 + read-only + + + HRS1_0 + A hardware service request for channel 1 is not present + 0 + + + HRS1_1 + A hardware service request for channel 1 is present + 0x1 + + + + + HRS2 + Hardware Request Status Channel 2 + 2 + 1 + read-only + + + HRS2_0 + A hardware service request for channel 2 is not present + 0 + + + HRS2_1 + A hardware service request for channel 2 is present + 0x1 + + + + + HRS3 + Hardware Request Status Channel 3 + 3 + 1 + read-only + + + HRS3_0 + A hardware service request for channel 3 is not present + 0 + + + HRS3_1 + A hardware service request for channel 3 is present + 0x1 + + + + + HRS4 + Hardware Request Status Channel 4 + 4 + 1 + read-only + + + HRS4_0 + A hardware service request for channel 4 is not present + 0 + + + HRS4_1 + A hardware service request for channel 4 is present + 0x1 + + + + + HRS5 + Hardware Request Status Channel 5 + 5 + 1 + read-only + + + HRS5_0 + A hardware service request for channel 5 is not present + 0 + + + HRS5_1 + A hardware service request for channel 5 is present + 0x1 + + + + + HRS6 + Hardware Request Status Channel 6 + 6 + 1 + read-only + + + HRS6_0 + A hardware service request for channel 6 is not present + 0 + + + HRS6_1 + A hardware service request for channel 6 is present + 0x1 + + + + + HRS7 + Hardware Request Status Channel 7 + 7 + 1 + read-only + + + HRS7_0 + A hardware service request for channel 7 is not present + 0 + + + HRS7_1 + A hardware service request for channel 7 is present + 0x1 + + + + + HRS8 + Hardware Request Status Channel 8 + 8 + 1 + read-only + + + HRS8_0 + A hardware service request for channel 8 is not present + 0 + + + HRS8_1 + A hardware service request for channel 8 is present + 0x1 + + + + + HRS9 + Hardware Request Status Channel 9 + 9 + 1 + read-only + + + HRS9_0 + A hardware service request for channel 9 is not present + 0 + + + HRS9_1 + A hardware service request for channel 9 is present + 0x1 + + + + + HRS10 + Hardware Request Status Channel 10 + 10 + 1 + read-only + + + HRS10_0 + A hardware service request for channel 10 is not present + 0 + + + HRS10_1 + A hardware service request for channel 10 is present + 0x1 + + + + + HRS11 + Hardware Request Status Channel 11 + 11 + 1 + read-only + + + HRS11_0 + A hardware service request for channel 11 is not present + 0 + + + HRS11_1 + A hardware service request for channel 11 is present + 0x1 + + + + + HRS12 + Hardware Request Status Channel 12 + 12 + 1 + read-only + + + HRS12_0 + A hardware service request for channel 12 is not present + 0 + + + HRS12_1 + A hardware service request for channel 12 is present + 0x1 + + + + + HRS13 + Hardware Request Status Channel 13 + 13 + 1 + read-only + + + HRS13_0 + A hardware service request for channel 13 is not present + 0 + + + HRS13_1 + A hardware service request for channel 13 is present + 0x1 + + + + + HRS14 + Hardware Request Status Channel 14 + 14 + 1 + read-only + + + HRS14_0 + A hardware service request for channel 14 is not present + 0 + + + HRS14_1 + A hardware service request for channel 14 is present + 0x1 + + + + + HRS15 + Hardware Request Status Channel 15 + 15 + 1 + read-only + + + HRS15_0 + A hardware service request for channel 15 is not present + 0 + + + HRS15_1 + A hardware service request for channel 15 is present + 0x1 + + + + + HRS16 + Hardware Request Status Channel 16 + 16 + 1 + read-only + + + HRS16_0 + A hardware service request for channel 16 is not present + 0 + + + HRS16_1 + A hardware service request for channel 16 is present + 0x1 + + + + + HRS17 + Hardware Request Status Channel 17 + 17 + 1 + read-only + + + HRS17_0 + A hardware service request for channel 17 is not present + 0 + + + HRS17_1 + A hardware service request for channel 17 is present + 0x1 + + + + + HRS18 + Hardware Request Status Channel 18 + 18 + 1 + read-only + + + HRS18_0 + A hardware service request for channel 18 is not present + 0 + + + HRS18_1 + A hardware service request for channel 18 is present + 0x1 + + + + + HRS19 + Hardware Request Status Channel 19 + 19 + 1 + read-only + + + HRS19_0 + A hardware service request for channel 19 is not present + 0 + + + HRS19_1 + A hardware service request for channel 19 is present + 0x1 + + + + + HRS20 + Hardware Request Status Channel 20 + 20 + 1 + read-only + + + HRS20_0 + A hardware service request for channel 20 is not present + 0 + + + HRS20_1 + A hardware service request for channel 20 is present + 0x1 + + + + + HRS21 + Hardware Request Status Channel 21 + 21 + 1 + read-only + + + HRS21_0 + A hardware service request for channel 21 is not present + 0 + + + HRS21_1 + A hardware service request for channel 21 is present + 0x1 + + + + + HRS22 + Hardware Request Status Channel 22 + 22 + 1 + read-only + + + HRS22_0 + A hardware service request for channel 22 is not present + 0 + + + HRS22_1 + A hardware service request for channel 22 is present + 0x1 + + + + + HRS23 + Hardware Request Status Channel 23 + 23 + 1 + read-only + + + HRS23_0 + A hardware service request for channel 23 is not present + 0 + + + HRS23_1 + A hardware service request for channel 23 is present + 0x1 + + + + + HRS24 + Hardware Request Status Channel 24 + 24 + 1 + read-only + + + HRS24_0 + A hardware service request for channel 24 is not present + 0 + + + HRS24_1 + A hardware service request for channel 24 is present + 0x1 + + + + + HRS25 + Hardware Request Status Channel 25 + 25 + 1 + read-only + + + HRS25_0 + A hardware service request for channel 25 is not present + 0 + + + HRS25_1 + A hardware service request for channel 25 is present + 0x1 + + + + + HRS26 + Hardware Request Status Channel 26 + 26 + 1 + read-only + + + HRS26_0 + A hardware service request for channel 26 is not present + 0 + + + HRS26_1 + A hardware service request for channel 26 is present + 0x1 + + + + + HRS27 + Hardware Request Status Channel 27 + 27 + 1 + read-only + + + HRS27_0 + A hardware service request for channel 27 is not present + 0 + + + HRS27_1 + A hardware service request for channel 27 is present + 0x1 + + + + + HRS28 + Hardware Request Status Channel 28 + 28 + 1 + read-only + + + HRS28_0 + A hardware service request for channel 28 is not present + 0 + + + HRS28_1 + A hardware service request for channel 28 is present + 0x1 + + + + + HRS29 + Hardware Request Status Channel 29 + 29 + 1 + read-only + + + HRS29_0 + A hardware service request for channel 29 is not preset + 0 + + + HRS29_1 + A hardware service request for channel 29 is present + 0x1 + + + + + HRS30 + Hardware Request Status Channel 30 + 30 + 1 + read-only + + + HRS30_0 + A hardware service request for channel 30 is not present + 0 + + + HRS30_1 + A hardware service request for channel 30 is present + 0x1 + + + + + HRS31 + Hardware Request Status Channel 31 + 31 + 1 + read-only + + + HRS31_0 + A hardware service request for channel 31 is not present + 0 + + + HRS31_1 + A hardware service request for channel 31 is present + 0x1 + + + + + + + EARS + Enable Asynchronous Request in Stop Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDREQ_0 + Enable asynchronous DMA request in stop mode for channel 0. + 0 + 1 + read-write + + + EDREQ_0_0 + Disable asynchronous DMA request for channel 0. + 0 + + + EDREQ_0_1 + Enable asynchronous DMA request for channel 0. + 0x1 + + + + + EDREQ_1 + Enable asynchronous DMA request in stop mode for channel 1. + 1 + 1 + read-write + + + EDREQ_1_0 + Disable asynchronous DMA request for channel 1 + 0 + + + EDREQ_1_1 + Enable asynchronous DMA request for channel 1. + 0x1 + + + + + EDREQ_2 + Enable asynchronous DMA request in stop mode for channel 2. + 2 + 1 + read-write + + + EDREQ_2_0 + Disable asynchronous DMA request for channel 2. + 0 + + + EDREQ_2_1 + Enable asynchronous DMA request for channel 2. + 0x1 + + + + + EDREQ_3 + Enable asynchronous DMA request in stop mode for channel 3. + 3 + 1 + read-write + + + EDREQ_3_0 + Disable asynchronous DMA request for channel 3. + 0 + + + EDREQ_3_1 + Enable asynchronous DMA request for channel 3. + 0x1 + + + + + EDREQ_4 + Enable asynchronous DMA request in stop mode for channel 4 + 4 + 1 + read-write + + + EDREQ_4_0 + Disable asynchronous DMA request for channel 4. + 0 + + + EDREQ_4_1 + Enable asynchronous DMA request for channel 4. + 0x1 + + + + + EDREQ_5 + Enable asynchronous DMA request in stop mode for channel 5 + 5 + 1 + read-write + + + EDREQ_5_0 + Disable asynchronous DMA request for channel 5. + 0 + + + EDREQ_5_1 + Enable asynchronous DMA request for channel 5. + 0x1 + + + + + EDREQ_6 + Enable asynchronous DMA request in stop mode for channel 6 + 6 + 1 + read-write + + + EDREQ_6_0 + Disable asynchronous DMA request for channel 6. + 0 + + + EDREQ_6_1 + Enable asynchronous DMA request for channel 6. + 0x1 + + + + + EDREQ_7 + Enable asynchronous DMA request in stop mode for channel 7 + 7 + 1 + read-write + + + EDREQ_7_0 + Disable asynchronous DMA request for channel 7. + 0 + + + EDREQ_7_1 + Enable asynchronous DMA request for channel 7. + 0x1 + + + + + EDREQ_8 + Enable asynchronous DMA request in stop mode for channel 8 + 8 + 1 + read-write + + + EDREQ_8_0 + Disable asynchronous DMA request for channel 8. + 0 + + + EDREQ_8_1 + Enable asynchronous DMA request for channel 8. + 0x1 + + + + + EDREQ_9 + Enable asynchronous DMA request in stop mode for channel 9 + 9 + 1 + read-write + + + EDREQ_9_0 + Disable asynchronous DMA request for channel 9. + 0 + + + EDREQ_9_1 + Enable asynchronous DMA request for channel 9. + 0x1 + + + + + EDREQ_10 + Enable asynchronous DMA request in stop mode for channel 10 + 10 + 1 + read-write + + + EDREQ_10_0 + Disable asynchronous DMA request for channel 10. + 0 + + + EDREQ_10_1 + Enable asynchronous DMA request for channel 10. + 0x1 + + + + + EDREQ_11 + Enable asynchronous DMA request in stop mode for channel 11 + 11 + 1 + read-write + + + EDREQ_11_0 + Disable asynchronous DMA request for channel 11. + 0 + + + EDREQ_11_1 + Enable asynchronous DMA request for channel 11. + 0x1 + + + + + EDREQ_12 + Enable asynchronous DMA request in stop mode for channel 12 + 12 + 1 + read-write + + + EDREQ_12_0 + Disable asynchronous DMA request for channel 12. + 0 + + + EDREQ_12_1 + Enable asynchronous DMA request for channel 12. + 0x1 + + + + + EDREQ_13 + Enable asynchronous DMA request in stop mode for channel 13 + 13 + 1 + read-write + + + EDREQ_13_0 + Disable asynchronous DMA request for channel 13. + 0 + + + EDREQ_13_1 + Enable asynchronous DMA request for channel 13. + 0x1 + + + + + EDREQ_14 + Enable asynchronous DMA request in stop mode for channel 14 + 14 + 1 + read-write + + + EDREQ_14_0 + Disable asynchronous DMA request for channel 14. + 0 + + + EDREQ_14_1 + Enable asynchronous DMA request for channel 14. + 0x1 + + + + + EDREQ_15 + Enable asynchronous DMA request in stop mode for channel 15 + 15 + 1 + read-write + + + EDREQ_15_0 + Disable asynchronous DMA request for channel 15. + 0 + + + EDREQ_15_1 + Enable asynchronous DMA request for channel 15. + 0x1 + + + + + EDREQ_16 + Enable asynchronous DMA request in stop mode for channel 16 + 16 + 1 + read-write + + + EDREQ_16_0 + Disable asynchronous DMA request for channel 16 + 0 + + + EDREQ_16_1 + Enable asynchronous DMA request for channel 16 + 0x1 + + + + + EDREQ_17 + Enable asynchronous DMA request in stop mode for channel 17 + 17 + 1 + read-write + + + EDREQ_17_0 + Disable asynchronous DMA request for channel 17 + 0 + + + EDREQ_17_1 + Enable asynchronous DMA request for channel 17 + 0x1 + + + + + EDREQ_18 + Enable asynchronous DMA request in stop mode for channel 18 + 18 + 1 + read-write + + + EDREQ_18_0 + Disable asynchronous DMA request for channel 18 + 0 + + + EDREQ_18_1 + Enable asynchronous DMA request for channel 18 + 0x1 + + + + + EDREQ_19 + Enable asynchronous DMA request in stop mode for channel 19 + 19 + 1 + read-write + + + EDREQ_19_0 + Disable asynchronous DMA request for channel 19 + 0 + + + EDREQ_19_1 + Enable asynchronous DMA request for channel 19 + 0x1 + + + + + EDREQ_20 + Enable asynchronous DMA request in stop mode for channel 20 + 20 + 1 + read-write + + + EDREQ_20_0 + Disable asynchronous DMA request for channel 20 + 0 + + + EDREQ_20_1 + Enable asynchronous DMA request for channel 20 + 0x1 + + + + + EDREQ_21 + Enable asynchronous DMA request in stop mode for channel 21 + 21 + 1 + read-write + + + EDREQ_21_0 + Disable asynchronous DMA request for channel 21 + 0 + + + EDREQ_21_1 + Enable asynchronous DMA request for channel 21 + 0x1 + + + + + EDREQ_22 + Enable asynchronous DMA request in stop mode for channel 22 + 22 + 1 + read-write + + + EDREQ_22_0 + Disable asynchronous DMA request for channel 22 + 0 + + + EDREQ_22_1 + Enable asynchronous DMA request for channel 22 + 0x1 + + + + + EDREQ_23 + Enable asynchronous DMA request in stop mode for channel 23 + 23 + 1 + read-write + + + EDREQ_23_0 + Disable asynchronous DMA request for channel 23 + 0 + + + EDREQ_23_1 + Enable asynchronous DMA request for channel 23 + 0x1 + + + + + EDREQ_24 + Enable asynchronous DMA request in stop mode for channel 24 + 24 + 1 + read-write + + + EDREQ_24_0 + Disable asynchronous DMA request for channel 24 + 0 + + + EDREQ_24_1 + Enable asynchronous DMA request for channel 24 + 0x1 + + + + + EDREQ_25 + Enable asynchronous DMA request in stop mode for channel 25 + 25 + 1 + read-write + + + EDREQ_25_0 + Disable asynchronous DMA request for channel 25 + 0 + + + EDREQ_25_1 + Enable asynchronous DMA request for channel 25 + 0x1 + + + + + EDREQ_26 + Enable asynchronous DMA request in stop mode for channel 26 + 26 + 1 + read-write + + + EDREQ_26_0 + Disable asynchronous DMA request for channel 26 + 0 + + + EDREQ_26_1 + Enable asynchronous DMA request for channel 26 + 0x1 + + + + + EDREQ_27 + Enable asynchronous DMA request in stop mode for channel 27 + 27 + 1 + read-write + + + EDREQ_27_0 + Disable asynchronous DMA request for channel 27 + 0 + + + EDREQ_27_1 + Enable asynchronous DMA request for channel 27 + 0x1 + + + + + EDREQ_28 + Enable asynchronous DMA request in stop mode for channel 28 + 28 + 1 + read-write + + + EDREQ_28_0 + Disable asynchronous DMA request for channel 28 + 0 + + + EDREQ_28_1 + Enable asynchronous DMA request for channel 28 + 0x1 + + + + + EDREQ_29 + Enable asynchronous DMA request in stop mode for channel 29 + 29 + 1 + read-write + + + EDREQ_29_0 + Disable asynchronous DMA request for channel 29 + 0 + + + EDREQ_29_1 + Enable asynchronous DMA request for channel 29 + 0x1 + + + + + EDREQ_30 + Enable asynchronous DMA request in stop mode for channel 30 + 30 + 1 + read-write + + + EDREQ_30_0 + Disable asynchronous DMA request for channel 30 + 0 + + + EDREQ_30_1 + Enable asynchronous DMA request for channel 30 + 0x1 + + + + + EDREQ_31 + Enable asynchronous DMA request in stop mode for channel 31 + 31 + 1 + read-write + + + EDREQ_31_0 + Disable asynchronous DMA request for channel 31 + 0 + + + EDREQ_31_1 + Enable asynchronous DMA request for channel 31 + 0x1 + + + + + + + DCHPRI3 + Channel Priority Register + 0x100 + 8 + read-write + 0x3 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI2 + Channel Priority Register + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI1 + Channel Priority Register + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI0 + Channel Priority Register + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI7 + Channel Priority Register + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI6 + Channel Priority Register + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI5 + Channel Priority Register + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI4 + Channel Priority Register + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI11 + Channel Priority Register + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI10 + Channel Priority Register + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI9 + Channel Priority Register + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI8 + Channel Priority Register + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI15 + Channel Priority Register + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI14 + Channel Priority Register + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI13 + Channel Priority Register + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI12 + Channel Priority Register + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI19 + Channel Priority Register + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI18 + Channel Priority Register + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI17 + Channel Priority Register + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI16 + Channel Priority Register + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI23 + Channel Priority Register + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI22 + Channel Priority Register + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI21 + Channel Priority Register + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI20 + Channel Priority Register + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI27 + Channel Priority Register + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI26 + Channel Priority Register + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI25 + Channel Priority Register + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI24 + Channel Priority Register + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI31 + Channel Priority Register + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI30 + Channel Priority Register + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI29 + Channel Priority Register + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI28 + Channel Priority Register + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + 32 + 0x1 + DCHMID[%s] + Channel n Master ID Register + 0x140 + 8 + read-write + 0 + 0xFF + + + MID + Master ID + 0 + 4 + read-only + + + PAL + Privileged Access Level + 6 + 1 + read-only + + + PAL_0 + User protection level for DMA transfers + 0 + + + PAL_1 + Privileged protection level for DMA transfers + 0x1 + + + + + EMI + Enable Master ID replication + 7 + 1 + read-write + + + EMI_0 + Master ID replication is disabled + 0 + + + EMI_1 + Master ID replication is enabled + 0x1 + + + + + + + TCD0_SADDR + TCD Source Address + 0x1000 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD0_SOFF + TCD Signed Source Address Offset + 0x1004 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD0_ATTR + TCD Transfer Attributes + 0x1006 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD0_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD0_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_SLAST + TCD Last Source Address Adjustment + 0x100C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD0_DADDR + TCD Destination Address + 0x1010 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD0_DOFF + TCD Signed Destination Address Offset + 0x1014 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD0_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1018 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD0_CSR + TCD Control and Status + 0x101C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD0_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_SADDR + TCD Source Address + 0x1020 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD1_SOFF + TCD Signed Source Address Offset + 0x1024 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD1_ATTR + TCD Transfer Attributes + 0x1026 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD1_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD1_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_SLAST + TCD Last Source Address Adjustment + 0x102C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD1_DADDR + TCD Destination Address + 0x1030 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD1_DOFF + TCD Signed Destination Address Offset + 0x1034 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD1_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1038 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD1_CSR + TCD Control and Status + 0x103C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD1_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_SADDR + TCD Source Address + 0x1040 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD2_SOFF + TCD Signed Source Address Offset + 0x1044 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD2_ATTR + TCD Transfer Attributes + 0x1046 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD2_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD2_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_SLAST + TCD Last Source Address Adjustment + 0x104C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD2_DADDR + TCD Destination Address + 0x1050 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD2_DOFF + TCD Signed Destination Address Offset + 0x1054 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD2_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1058 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD2_CSR + TCD Control and Status + 0x105C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD2_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_SADDR + TCD Source Address + 0x1060 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD3_SOFF + TCD Signed Source Address Offset + 0x1064 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD3_ATTR + TCD Transfer Attributes + 0x1066 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD3_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD3_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_SLAST + TCD Last Source Address Adjustment + 0x106C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD3_DADDR + TCD Destination Address + 0x1070 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD3_DOFF + TCD Signed Destination Address Offset + 0x1074 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD3_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1078 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD3_CSR + TCD Control and Status + 0x107C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD3_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_SADDR + TCD Source Address + 0x1080 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD4_SOFF + TCD Signed Source Address Offset + 0x1084 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD4_ATTR + TCD Transfer Attributes + 0x1086 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD4_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD4_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_SLAST + TCD Last Source Address Adjustment + 0x108C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD4_DADDR + TCD Destination Address + 0x1090 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD4_DOFF + TCD Signed Destination Address Offset + 0x1094 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD4_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1098 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD4_CSR + TCD Control and Status + 0x109C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD4_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_SADDR + TCD Source Address + 0x10A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD5_SOFF + TCD Signed Source Address Offset + 0x10A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD5_ATTR + TCD Transfer Attributes + 0x10A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD5_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD5_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_SLAST + TCD Last Source Address Adjustment + 0x10AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD5_DADDR + TCD Destination Address + 0x10B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD5_DOFF + TCD Signed Destination Address Offset + 0x10B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD5_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD5_CSR + TCD Control and Status + 0x10BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD5_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_SADDR + TCD Source Address + 0x10C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD6_SOFF + TCD Signed Source Address Offset + 0x10C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD6_ATTR + TCD Transfer Attributes + 0x10C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD6_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD6_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_SLAST + TCD Last Source Address Adjustment + 0x10CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD6_DADDR + TCD Destination Address + 0x10D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD6_DOFF + TCD Signed Destination Address Offset + 0x10D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD6_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD6_CSR + TCD Control and Status + 0x10DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD6_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_SADDR + TCD Source Address + 0x10E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD7_SOFF + TCD Signed Source Address Offset + 0x10E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD7_ATTR + TCD Transfer Attributes + 0x10E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD7_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD7_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_SLAST + TCD Last Source Address Adjustment + 0x10EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD7_DADDR + TCD Destination Address + 0x10F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD7_DOFF + TCD Signed Destination Address Offset + 0x10F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD7_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD7_CSR + TCD Control and Status + 0x10FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD7_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_SADDR + TCD Source Address + 0x1100 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD8_SOFF + TCD Signed Source Address Offset + 0x1104 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD8_ATTR + TCD Transfer Attributes + 0x1106 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD8_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD8_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_SLAST + TCD Last Source Address Adjustment + 0x110C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD8_DADDR + TCD Destination Address + 0x1110 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD8_DOFF + TCD Signed Destination Address Offset + 0x1114 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD8_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1118 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD8_CSR + TCD Control and Status + 0x111C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD8_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_SADDR + TCD Source Address + 0x1120 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD9_SOFF + TCD Signed Source Address Offset + 0x1124 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD9_ATTR + TCD Transfer Attributes + 0x1126 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD9_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD9_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_SLAST + TCD Last Source Address Adjustment + 0x112C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD9_DADDR + TCD Destination Address + 0x1130 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD9_DOFF + TCD Signed Destination Address Offset + 0x1134 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD9_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1138 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD9_CSR + TCD Control and Status + 0x113C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD9_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_SADDR + TCD Source Address + 0x1140 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD10_SOFF + TCD Signed Source Address Offset + 0x1144 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD10_ATTR + TCD Transfer Attributes + 0x1146 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD10_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD10_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_SLAST + TCD Last Source Address Adjustment + 0x114C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD10_DADDR + TCD Destination Address + 0x1150 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD10_DOFF + TCD Signed Destination Address Offset + 0x1154 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD10_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1158 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD10_CSR + TCD Control and Status + 0x115C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD10_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_SADDR + TCD Source Address + 0x1160 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD11_SOFF + TCD Signed Source Address Offset + 0x1164 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD11_ATTR + TCD Transfer Attributes + 0x1166 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD11_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD11_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_SLAST + TCD Last Source Address Adjustment + 0x116C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD11_DADDR + TCD Destination Address + 0x1170 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD11_DOFF + TCD Signed Destination Address Offset + 0x1174 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD11_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1178 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD11_CSR + TCD Control and Status + 0x117C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD11_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_SADDR + TCD Source Address + 0x1180 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD12_SOFF + TCD Signed Source Address Offset + 0x1184 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD12_ATTR + TCD Transfer Attributes + 0x1186 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD12_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD12_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_SLAST + TCD Last Source Address Adjustment + 0x118C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD12_DADDR + TCD Destination Address + 0x1190 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD12_DOFF + TCD Signed Destination Address Offset + 0x1194 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD12_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1198 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD12_CSR + TCD Control and Status + 0x119C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD12_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_SADDR + TCD Source Address + 0x11A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD13_SOFF + TCD Signed Source Address Offset + 0x11A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD13_ATTR + TCD Transfer Attributes + 0x11A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD13_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD13_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_SLAST + TCD Last Source Address Adjustment + 0x11AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD13_DADDR + TCD Destination Address + 0x11B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD13_DOFF + TCD Signed Destination Address Offset + 0x11B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD13_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD13_CSR + TCD Control and Status + 0x11BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD13_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_SADDR + TCD Source Address + 0x11C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD14_SOFF + TCD Signed Source Address Offset + 0x11C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD14_ATTR + TCD Transfer Attributes + 0x11C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD14_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD14_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_SLAST + TCD Last Source Address Adjustment + 0x11CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD14_DADDR + TCD Destination Address + 0x11D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD14_DOFF + TCD Signed Destination Address Offset + 0x11D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD14_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD14_CSR + TCD Control and Status + 0x11DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD14_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_SADDR + TCD Source Address + 0x11E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD15_SOFF + TCD Signed Source Address Offset + 0x11E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD15_ATTR + TCD Transfer Attributes + 0x11E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD15_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD15_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_SLAST + TCD Last Source Address Adjustment + 0x11EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD15_DADDR + TCD Destination Address + 0x11F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD15_DOFF + TCD Signed Destination Address Offset + 0x11F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD15_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD15_CSR + TCD Control and Status + 0x11FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD15_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_SADDR + TCD Source Address + 0x1200 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD16_SOFF + TCD Signed Source Address Offset + 0x1204 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD16_ATTR + TCD Transfer Attributes + 0x1206 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD16_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD16_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_SLAST + TCD Last Source Address Adjustment + 0x120C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD16_DADDR + TCD Destination Address + 0x1210 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD16_DOFF + TCD Signed Destination Address Offset + 0x1214 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD16_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1218 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD16_CSR + TCD Control and Status + 0x121C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD16_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_SADDR + TCD Source Address + 0x1220 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD17_SOFF + TCD Signed Source Address Offset + 0x1224 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD17_ATTR + TCD Transfer Attributes + 0x1226 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD17_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD17_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_SLAST + TCD Last Source Address Adjustment + 0x122C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD17_DADDR + TCD Destination Address + 0x1230 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD17_DOFF + TCD Signed Destination Address Offset + 0x1234 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD17_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1238 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD17_CSR + TCD Control and Status + 0x123C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD17_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_SADDR + TCD Source Address + 0x1240 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD18_SOFF + TCD Signed Source Address Offset + 0x1244 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD18_ATTR + TCD Transfer Attributes + 0x1246 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD18_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD18_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_SLAST + TCD Last Source Address Adjustment + 0x124C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD18_DADDR + TCD Destination Address + 0x1250 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD18_DOFF + TCD Signed Destination Address Offset + 0x1254 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD18_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1258 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD18_CSR + TCD Control and Status + 0x125C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD18_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_SADDR + TCD Source Address + 0x1260 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD19_SOFF + TCD Signed Source Address Offset + 0x1264 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD19_ATTR + TCD Transfer Attributes + 0x1266 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD19_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD19_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_SLAST + TCD Last Source Address Adjustment + 0x126C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD19_DADDR + TCD Destination Address + 0x1270 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD19_DOFF + TCD Signed Destination Address Offset + 0x1274 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD19_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1278 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD19_CSR + TCD Control and Status + 0x127C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD19_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_SADDR + TCD Source Address + 0x1280 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD20_SOFF + TCD Signed Source Address Offset + 0x1284 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD20_ATTR + TCD Transfer Attributes + 0x1286 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD20_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD20_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_SLAST + TCD Last Source Address Adjustment + 0x128C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD20_DADDR + TCD Destination Address + 0x1290 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD20_DOFF + TCD Signed Destination Address Offset + 0x1294 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD20_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1298 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD20_CSR + TCD Control and Status + 0x129C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD20_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_SADDR + TCD Source Address + 0x12A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD21_SOFF + TCD Signed Source Address Offset + 0x12A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD21_ATTR + TCD Transfer Attributes + 0x12A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD21_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD21_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_SLAST + TCD Last Source Address Adjustment + 0x12AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD21_DADDR + TCD Destination Address + 0x12B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD21_DOFF + TCD Signed Destination Address Offset + 0x12B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD21_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD21_CSR + TCD Control and Status + 0x12BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD21_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_SADDR + TCD Source Address + 0x12C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD22_SOFF + TCD Signed Source Address Offset + 0x12C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD22_ATTR + TCD Transfer Attributes + 0x12C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD22_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD22_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_SLAST + TCD Last Source Address Adjustment + 0x12CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD22_DADDR + TCD Destination Address + 0x12D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD22_DOFF + TCD Signed Destination Address Offset + 0x12D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD22_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD22_CSR + TCD Control and Status + 0x12DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD22_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_SADDR + TCD Source Address + 0x12E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD23_SOFF + TCD Signed Source Address Offset + 0x12E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD23_ATTR + TCD Transfer Attributes + 0x12E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD23_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD23_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_SLAST + TCD Last Source Address Adjustment + 0x12EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD23_DADDR + TCD Destination Address + 0x12F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD23_DOFF + TCD Signed Destination Address Offset + 0x12F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD23_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD23_CSR + TCD Control and Status + 0x12FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD23_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_SADDR + TCD Source Address + 0x1300 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD24_SOFF + TCD Signed Source Address Offset + 0x1304 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD24_ATTR + TCD Transfer Attributes + 0x1306 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD24_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD24_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_SLAST + TCD Last Source Address Adjustment + 0x130C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD24_DADDR + TCD Destination Address + 0x1310 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD24_DOFF + TCD Signed Destination Address Offset + 0x1314 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD24_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1318 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD24_CSR + TCD Control and Status + 0x131C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD24_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_SADDR + TCD Source Address + 0x1320 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD25_SOFF + TCD Signed Source Address Offset + 0x1324 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD25_ATTR + TCD Transfer Attributes + 0x1326 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD25_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD25_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_SLAST + TCD Last Source Address Adjustment + 0x132C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD25_DADDR + TCD Destination Address + 0x1330 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD25_DOFF + TCD Signed Destination Address Offset + 0x1334 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD25_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1338 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD25_CSR + TCD Control and Status + 0x133C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD25_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_SADDR + TCD Source Address + 0x1340 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD26_SOFF + TCD Signed Source Address Offset + 0x1344 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD26_ATTR + TCD Transfer Attributes + 0x1346 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD26_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD26_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_SLAST + TCD Last Source Address Adjustment + 0x134C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD26_DADDR + TCD Destination Address + 0x1350 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD26_DOFF + TCD Signed Destination Address Offset + 0x1354 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD26_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1358 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD26_CSR + TCD Control and Status + 0x135C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD26_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_SADDR + TCD Source Address + 0x1360 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD27_SOFF + TCD Signed Source Address Offset + 0x1364 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD27_ATTR + TCD Transfer Attributes + 0x1366 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD27_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD27_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_SLAST + TCD Last Source Address Adjustment + 0x136C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD27_DADDR + TCD Destination Address + 0x1370 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD27_DOFF + TCD Signed Destination Address Offset + 0x1374 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD27_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1378 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD27_CSR + TCD Control and Status + 0x137C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD27_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_SADDR + TCD Source Address + 0x1380 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD28_SOFF + TCD Signed Source Address Offset + 0x1384 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD28_ATTR + TCD Transfer Attributes + 0x1386 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD28_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD28_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_SLAST + TCD Last Source Address Adjustment + 0x138C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD28_DADDR + TCD Destination Address + 0x1390 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD28_DOFF + TCD Signed Destination Address Offset + 0x1394 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD28_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1398 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD28_CSR + TCD Control and Status + 0x139C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD28_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_SADDR + TCD Source Address + 0x13A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD29_SOFF + TCD Signed Source Address Offset + 0x13A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD29_ATTR + TCD Transfer Attributes + 0x13A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD29_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD29_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_SLAST + TCD Last Source Address Adjustment + 0x13AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD29_DADDR + TCD Destination Address + 0x13B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD29_DOFF + TCD Signed Destination Address Offset + 0x13B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD29_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD29_CSR + TCD Control and Status + 0x13BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD29_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_SADDR + TCD Source Address + 0x13C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD30_SOFF + TCD Signed Source Address Offset + 0x13C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD30_ATTR + TCD Transfer Attributes + 0x13C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD30_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD30_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_SLAST + TCD Last Source Address Adjustment + 0x13CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD30_DADDR + TCD Destination Address + 0x13D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD30_DOFF + TCD Signed Destination Address Offset + 0x13D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD30_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD30_CSR + TCD Control and Status + 0x13DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD30_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_SADDR + TCD Source Address + 0x13E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD31_SOFF + TCD Signed Source Address Offset + 0x13E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD31_ATTR + TCD Transfer Attributes + 0x13E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD31_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD31_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_SLAST + TCD Last Source Address Adjustment + 0x13EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD31_DADDR + TCD Destination Address + 0x13F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD31_DOFF + TCD Signed Destination Address Offset + 0x13F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD31_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD31_CSR + TCD Control and Status + 0x13FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD31_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0x400EC000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + CHCFG[%s] + Channel 0 Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + DMA Channel Source (Slot Number) + 0 + 7 + read-write + + + A_ON + DMA Channel Always Enable + 29 + 1 + read-write + + + A_ON_0 + DMA Channel Always ON function is disabled + 0 + + + A_ON_1 + DMA Channel Always ON function is enabled + 0x1 + + + + + TRIG + DMA Channel Trigger Enable + 30 + 1 + read-write + + + TRIG_0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + 0 + + + TRIG_1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + 0x1 + + + + + ENBL + DMA Mux Channel Enable + 31 + 1 + read-write + + + ENBL_0 + DMA Mux channel is disabled + 0 + + + ENBL_1 + DMA Mux channel is enabled + 0x1 + + + + + + + + + GPC + GPC + GPC + GPC_ + 0x400F4000 + + 0 + 0x3C + registers + + + GPC + 97 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain power down request + 2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain power up request + 3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + PDRAM0_PGE + FlexRAM PDRAM0 Power Gate Enable + 22 + 1 + read-write + + + PDRAM0_PGE_0 + FlexRAM PDRAM0 domain will keep power on even if CPU core is power down. + 0 + + + PDRAM0_PGE_1 + FlexRAM PDRAM0 domain will be power down once when CPU core is power down. + 0x1 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[31:0] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + IMR5 + IRQ masking register 5 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR5 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR5 + IRQ status resister 5 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + PGC + PGC + GPC + PGC + PGC_ + 0x400F4000 + + 0 + 0x2B0 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x224 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x228 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) + 8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x2A4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + There are two different silicon revisions: 1 + 0 + 6 + read-write + + + SW2ISO + There are two different silicon revisions: 1 + 8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x2A8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating + 8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + SRC + SRC + SRC + SRC_ + 0x400F8000 + + 0 + 0x48 + registers + + + SRC + 98 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0xA0480520 + 0xFFFFFFFF + + + lockup_rst + lockup reset enable bit + 4 + 1 + read-write + + + lockup_rst_0 + disabled + 0 + + + lockup_rst_1 + enabled + 0x1 + + + + + mask_wdog_rst + Mask wdog_rst_b source + 7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + core0_rst + Software reset for core0 only + 13 + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 17 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 25 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 28 + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 16 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 24 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + lockup + Indicates a reset has been caused by CPU lockup . + 1 + 1 + read-write + oneToClear + + + lockup_0 + Reset is not a result of the mentioned case. + 0 + + + lockup_1 + Reset is a result of the mentioned case. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input. + 2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset + 6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of the mentioned case. + 0 + + + jtag_sw_rst_1 + Reset is not a result of the mentioned case. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 24 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + + + CCM + CCM + CCM + CCM_ + 0x400FC000 + + 0 + 0x8C + registers + + + CCM_1 + 95 + + + CCM_2 + 96 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401107F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened. + 0 + 8 + read-write + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 12 + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 21 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 27 + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + CAMP2_READY + Status indication of CAMP2. + 3 + 1 + read-only + + + CAMP2_READY_0 + CAMP2 is not ready. + 0 + + + CAMP2_READY_1 + CAMP2 is ready. + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARM_PODF + Divider for ARM clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0xA8000 + 0xFFFFFFFF + + + SEMC_CLK_SEL + SEMC clock source select + 6 + 1 + read-write + + + SEMC_CLK_SEL_0 + Periph_clk output will be used as SEMC clock root + 0 + + + SEMC_CLK_SEL_1 + SEMC alternative clock will be used as SEMC clock root + 0x1 + + + + + SEMC_ALT_CLK_SEL + SEMC alternative clock select + 7 + 1 + read-write + + + SEMC_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for SEMC root clock + 0 + + + SEMC_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for SEMC root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf. + 8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 10 + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + SEMC_PODF + Post divider for SEMC clock + 16 + 3 + read-write + + + SEMC_PODF_0 + divide by 1 + 0 + + + SEMC_PODF_1 + divide by 2 + 0x1 + + + SEMC_PODF_2 + divide by 3 + 0x2 + + + SEMC_PODF_3 + divide by 4 + 0x3 + + + SEMC_PODF_4 + divide by 5 + 0x4 + + + SEMC_PODF_5 + divide by 6 + 0x5 + + + SEMC_PODF_6 + divide by 7 + 0x6 + + + SEMC_PODF_7 + divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock + 25 + 1 + read-write + + + PERIPH_CLK_SEL_0 + derive clock from pre_periph_clk_sel + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk_divided + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 27 + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x2DAA8324 + 0xFFFFFFFF + + + LPSPI_CLK_SEL + Selector for lpspi clock multiplexer + 4 + 2 + read-write + + + LPSPI_CLK_SEL_0 + derive clock from PLL3 PFD1 clk + 0 + + + LPSPI_CLK_SEL_1 + derive clock from PLL3 PFD0 + 0x1 + + + LPSPI_CLK_SEL_2 + derive clock from PLL2 + 0x2 + + + LPSPI_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 12 + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + TRACE_CLK_SEL + Selector for Trace clock multiplexer + 14 + 2 + read-write + + + TRACE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + TRACE_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + TRACE_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + TRACE_CLK_SEL_3 + derive clock from PLL2 PFD1 + 0x3 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 18 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD3 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided PLL6 + 0x3 + + + + + LPSPI_PODF + Divider for LPSPI. Divider should be updated when output clock is gated. + 26 + 3 + read-write + + + LPSPI_PODF_0 + divide by 1 + 0 + + + LPSPI_PODF_1 + divide by 2 + 0x1 + + + LPSPI_PODF_2 + divide by 3 + 0x2 + + + LPSPI_PODF_3 + divide by 4 + 0x3 + + + LPSPI_PODF_4 + divide by 5 + 0x4 + + + LPSPI_PODF_5 + divide by 6 + 0x5 + + + LPSPI_PODF_6 + divide by 7 + 0x6 + + + LPSPI_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900000 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 10 + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 12 + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3 clock multiplexer + 14 + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + FLEXSPI_PODF + Divider for flexspi clock root. + 23 + 3 + read-write + + + FLEXSPI_PODF_0 + divide by 1 + 0 + + + FLEXSPI_PODF_1 + divide by 2 + 0x1 + + + FLEXSPI_PODF_2 + divide by 3 + 0x2 + + + FLEXSPI_PODF_3 + divide by 4 + 0x3 + + + FLEXSPI_PODF_4 + divide by 5 + 0x4 + + + FLEXSPI_PODF_5 + divide by 6 + 0x5 + + + FLEXSPI_PODF_6 + divide by 7 + 0x6 + + + FLEXSPI_PODF_7 + divide by 8 + 0x7 + + + + + FLEXSPI_CLK_SEL + Selector for flexspi clock multiplexer + 29 + 2 + read-write + + + FLEXSPI_CLK_SEL_0 + derive clock from semc_clk_root_pre + 0 + + + FLEXSPI_CLK_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + FLEXSPI_CLK_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + FLEXSPI_CLK_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x13192F06 + 0xFFFFFFFF + + + FLEXIO1_CLK_SEL + Selector for flexio1 clock multiplexer + 19 + 2 + read-write + + + FLEXIO1_CLK_SEL_0 + derive clock from PLL4 divided clock + 0 + + + FLEXIO1_CLK_SEL_1 + derive clock from PLL3 PFD2 clock + 0x1 + + + FLEXIO1_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x6490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + TRACE_PODF + Divider for trace clock. Divider should be updated when output clock is gated. + 25 + 2 + read-write + + + TRACE_PODF_0 + divide by 1 + 0 + + + TRACE_PODF_1 + divide by 2 + 0x1 + + + TRACE_PODF_2 + divide by 3 + 0x2 + + + TRACE_PODF_3 + divide by 4 + 0x3 + + + + + + + CS1CDR + CCM Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO1_CLK_PRED + Divider for flexio1 clock. + 9 + 3 + read-write + + + FLEXIO1_CLK_PRED_0 + divide by 1 + 0 + + + FLEXIO1_CLK_PRED_1 + divide by 2 + 0x1 + + + FLEXIO1_CLK_PRED_2 + divide by 3 + 0x2 + + + FLEXIO1_CLK_PRED_3 + divide by 4 + 0x3 + + + FLEXIO1_CLK_PRED_4 + divide by 5 + 0x4 + + + FLEXIO1_CLK_PRED_5 + divide by 6 + 0x5 + + + FLEXIO1_CLK_PRED_6 + divide by 7 + 0x6 + + + FLEXIO1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 16 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3 clock pred. + 22 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO1_CLK_PODF + Divider for flexio1 clock. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CS2CDR + CCM Clock Divider Register + 0x2C + 32 + read-write + 0x736C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 20 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 22 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29150 + 0xFFFFFFFF + + + LPI2C_CLK_SEL + Selector for the LPI2C clock multiplexor + 18 + 1 + read-write + + + LPI2C_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + LPI2C_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + LPI2C_CLK_PODF + Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 19 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-only + 0x30841 + 0xFFFFFFFF + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEMC_PODF_BUSY + Busy indicator for semc_podf. + 0 + 1 + read-only + + + SEMC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + SEMC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 16 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + ARM clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + ARM clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 11 + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_LPM_HS1 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 19 + 1 + read-write + + + BYPASS_LPM_HS0 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 21 + 1 + read-write + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 22 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 26 + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 27 + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + SEMC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of semc_podf + 17 + 1 + read-write + oneToClear + + + SEMC_PODF_LOADED_0 + interrupt is not generated due to frequency change of semc_podf + 0 + + + SEMC_PODF_LOADED_1 + interrupt generated due to frequency change of semc_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 19 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 20 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 22 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 26 + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_SEMC_PODF_LOADED + mask interrupt generation due to frequency change of semc_podf + 17 + 1 + read-write + + + MASK_SEMC_PODF_LOADED_0 + don't mask interrupt due to frequency change of semc_podf - interrupt will be created + 0 + + + MASK_SEMC_PODF_LOADED_1 + mask interrupt due to frequency change of semc_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 19 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 20 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 22 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 26 + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO1_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO1_SEL_0 + pll3_sw_clk (divided by 2) + 0 + + + CLKO1_SEL_1 + PLL2 (divided by 2) + 0x1 + + + CLKO1_SEL_2 + ENET PLL (divided by 2) + 0x2 + + + CLKO1_SEL_11 + ahb_clk_root + 0xB + + + CLKO1_SEL_12 + ipg_clk_root + 0xC + + + CLKO1_SEL_13 + perclk_root + 0xD + + + CLKO1_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 16 + 5 + read-write + + + CLKO2_SEL_6 + lpi2c_clk_root + 0x6 + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_16 + lpspi_clk_root + 0x10 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root + 0x14 + + + CLKO2_SEL_22 + trace_clk_root + 0x16 + + + CLKO2_SEL_27 + flexspi_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 21 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 24 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 14 + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + 0x1 + + + SYS_MEM_DS_CTRL_2 + enable memory (outside ARM platform) DS mode when system is in STOP mode + #1x + + + + + FPL + Fast PLL enable. + 16 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal + 17 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the ARM platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 2 + 2 + read-write + + + CG2 + mqs clock ( mqs_hmclk_clock_enable) + 4 + 2 + read-write + + + CG3 + Reserved + 6 + 2 + read-write + + + CG4 + sim_m_clk_r_clk_enable + 8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 10 + 2 + read-write + + + CG6 + lpuart3 clock (lpuart3_clk_enable) + 12 + 2 + read-write + + + CG7 + Reserved + 14 + 2 + read-write + + + CG8 + Reserved + 16 + 2 + read-write + + + CG9 + Reserved + 18 + 2 + read-write + + + CG10 + Reserved + 20 + 2 + read-write + + + CG11 + trace clock (trace_clk_enable) + 22 + 2 + read-write + + + CG12 + gpt2 bus clocks (gpt2_bus_clk_enable) + 24 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 26 + 2 + read-write + + + CG14 + lpuart2 clock (lpuart2_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 30 + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + lpspi1 clocks (lpspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + lpspi2 clocks (lpspi2_clk_enable) + 2 + 2 + read-write + + + CG2 + Reserved + 4 + 2 + read-write + + + CG3 + Reserved + 6 + 2 + read-write + + + CG4 + Reserved + 8 + 2 + read-write + + + CG5 + Reserved + 10 + 2 + read-write + + + CG6 + pit clocks (pit_clk_enable) + 12 + 2 + read-write + + + CG7 + Reserved + 14 + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 16 + 2 + read-write + + + CG9 + Reserved + 18 + 2 + read-write + + + CG10 + gpt1 bus clock (gpt_clk_enable) + 20 + 2 + read-write + + + CG11 + gpt1 serial clock (gpt_serial_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart4 clock (lpuart4_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 26 + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio5 clock (gpio5_clk_enable) + 30 + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + ocram_exsc clock (ocram_exsc_clk_enable) + 0 + 2 + read-write + + + CG1 + Reserved + 2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 4 + 2 + read-write + + + CG3 + lpi2c1 clock (lpi2c1_clk_enable) + 6 + 2 + read-write + + + CG4 + lpi2c2 clock (lpi2c2_clk_enable) + 8 + 2 + read-write + + + CG5 + Reserved + 10 + 2 + read-write + + + CG6 + OCOTP_CTRL clock (iim_clk_enable) + 12 + 2 + read-write + + + CG7 + Reserved + 14 + 2 + read-write + + + CG8 + Reserved + 16 + 2 + read-write + + + CG9 + Reserved + 18 + 2 + read-write + + + CG10 + Reserved + 20 + 2 + read-write + + + CG11 + xbar1 clock (xbar1_clk_enable) + 22 + 2 + read-write + + + CG12 + xbar2 clock (xbar2_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 26 + 2 + read-write + + + CG14 + Reserved + 28 + 2 + read-write + + + CG15 + Reserved + 30 + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFCF + 0xFFFFFFFF + + + CG0 + Reserved + 0 + 2 + read-write + + + CG1 + Reserved + 2 + 2 + read-write + + + CG2 + Reserved + 4 + 2 + read-write + + + CG3 + Reserved + 6 + 2 + read-write + + + CG4 + aoi1 clock (aoi1_clk_enable) + 8 + 2 + read-write + + + CG5 + Reserved + 10 + 2 + read-write + + + CG6 + Reserved + 12 + 2 + read-write + + + CG7 + ewm clocks (ewm_clk_enable) + 14 + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 16 + 2 + read-write + + + CG9 + flexram clock (flexram_clk_enable) + 18 + 2 + read-write + + + CG10 + Reserved + 20 + 2 + read-write + + + CG11 + Reserved + 22 + 2 + read-write + + + CG12 + Reserved + 24 + 2 + read-write + + + CG13 + Reserved + 26 + 2 + read-write + + + CG14 + The OCRAM clock cannot be turned off when the CM cache is running on this device. + 28 + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 30 + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + sim_m7_clk_r_enable + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 4 + 2 + read-write + + + CG3 + bee clock(bee_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m7 clock (sim_m7_clk_enable) + 8 + 2 + read-write + + + CG5 + Reserved + 10 + 2 + read-write + + + CG6 + sim_m clocks (sim_m_clk_enable) + 12 + 2 + read-write + + + CG7 + sim_ems clocks (sim_ems_clk_enable) + 14 + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 16 + 2 + read-write + + + CG9 + Reserved + 18 + 2 + read-write + + + CG10 + Reserved + 20 + 2 + read-write + + + CG11 + Reserved + 22 + 2 + read-write + + + CG12 + enc1 clocks (enc1_clk_enable) + 24 + 2 + read-write + + + CG13 + Reserved + 26 + 2 + read-write + + + CG14 + Reserved + 28 + 2 + read-write + + + CG15 + Reserved + 30 + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + flexio1 clock (flexio1_clk_enable) + 2 + 2 + read-write + + + CG2 + wdog3 clock (wdog3_clk_enable) + 4 + 2 + read-write + + + CG3 + dma clock (dma_clk_enable) + 6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 10 + 2 + read-write + + + CG6 + aipstz4 clocks (aips_tz4_clk_enable) + 12 + 2 + read-write + + + CG7 + spdif clock (spdif_clk_enable) + 14 + 2 + read-write + + + CG8 + Reserved + 16 + 2 + read-write + + + CG9 + sai1 clock (sai1_clk_enable) + 18 + 2 + read-write + + + CG10 + sai2 clock (sai2_clk_enable) + 20 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart1 clock (lpuart1_clk_enable) + 24 + 2 + read-write + + + CG13 + Reserved + 26 + 2 + read-write + + + CG14 + snvs_hp clock (snvs_hp_clk_enable) + 28 + 2 + read-write + + + CG15 + snvs_lp clock (snvs_lp_clk_enable) + 30 + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + Reserved + 2 + 2 + read-write + + + CG2 + Reserved + 4 + 2 + read-write + + + CG3 + dcdc clocks (dcdc_clk_enable) + 6 + 2 + read-write + + + CG4 + Reserved + 8 + 2 + read-write + + + CG5 + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared + 10 + 2 + read-write + + + CG6 + trng clock (trng_clk_enable) + 12 + 2 + read-write + + + CG7 + Reserved + 14 + 2 + read-write + + + CG8 + Reserved + 16 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 18 + 2 + read-write + + + CG10 + sim_per clock (sim_per_clk_enable) + 20 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 22 + 2 + read-write + + + CG12 + Reserved + 24 + 2 + read-write + + + CG13 + timer1 clocks (timer1_clk_enable) + 26 + 2 + read-write + + + CG14 + Reserved + 28 + 2 + read-write + + + CG15 + Reserved + 30 + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_PIT + Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk' + 6 + 1 + read-write + + + MOD_EN_OV_PIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_PIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_TRNG + Overide clock enable signal from TRNG + 9 + 1 + read-write + + + MOD_EN_OV_TRNG_0 + don't override module enable signal + 0 + + + MOD_EN_OV_TRNG_1 + override module enable signal + 0x1 + + + + + + + + + ROMC + ROMC + ROMC + ROMC_ + 0x40180000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 29 + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch + 0 + 1 + read-write + + + THUMBX_0 + Arm patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 17 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + LPUART1 + LPUART + LPUART + LPUART + 0x40184000 + + 0 + 0x30 + registers + + + LPUART1 + 20 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x4010003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + FEATURE_1 + Standard feature set. + 0x1 + + + FEATURE_3 + Standard feature set with MODEM/IrDA support. + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + GLOBAL + LPUART Global Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset. + 0 + + + RST_1 + Module is reset. + 0x1 + + + + + + + PINCFG + LPUART Pin Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRGSEL + Trigger Select + 0 + 2 + read-write + + + TRGSEL_0 + Input trigger is disabled. + 0 + + + TRGSEL_1 + Input trigger is used instead of RXD pin input. + 0x1 + + + TRGSEL_2 + Input trigger is used instead of CTS_B pin input. + 0x2 + + + TRGSEL_3 + Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + 0x3 + + + + + + + BAUD + LPUART Baud Rate Register + 0x10 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + SBNS_0 + One stop bit. + 0 + + + SBNS_1 + Two stop bits. + 0x1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + RXEDGIE_0 + Hardware interrupts from STAT[RXEDGIF] are disabled. + 0 + + + RXEDGIE_1 + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + 0x1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + LBKDIE_0 + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + 0 + + + LBKDIE_1 + Hardware interrupt requested when STAT[LBKDIF] flag is 1. + 0x1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + RESYNCDIS_0 + Resynchronization during received data word is supported + 0 + + + RESYNCDIS_1 + Resynchronization during received data word is disabled + 0x1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + BOTHEDGE_0 + Receiver samples input data using the rising edge of the baud rate clock. + 0 + + + BOTHEDGE_1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + 0x1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + MATCFG_0 + Address Match Wakeup + 0 + + + MATCFG_1 + Idle Match Wakeup + 0x1 + + + MATCFG_2 + Match On and Match Off + 0x2 + + + MATCFG_3 + Enables RWU on Data Match and Match On/Off for transmitter CTS input + 0x3 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + RDMAE_0 + DMA request disabled. + 0 + + + RDMAE_1 + DMA request enabled. + 0x1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + TDMAE_0 + DMA request disabled. + 0 + + + TDMAE_1 + DMA request enabled. + 0x1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + OSR_0 + Writing 0 to this field will result in an oversampling ratio of 16 + 0 + + + OSR_3 + Oversampling ratio of 4, requires BOTHEDGE to be set. + 0x3 + + + OSR_4 + Oversampling ratio of 5, requires BOTHEDGE to be set. + 0x4 + + + OSR_5 + Oversampling ratio of 6, requires BOTHEDGE to be set. + 0x5 + + + OSR_6 + Oversampling ratio of 7, requires BOTHEDGE to be set. + 0x6 + + + OSR_7 + Oversampling ratio of 8. + 0x7 + + + OSR_8 + Oversampling ratio of 9. + 0x8 + + + OSR_9 + Oversampling ratio of 10. + 0x9 + + + OSR_10 + Oversampling ratio of 11. + 0xA + + + OSR_11 + Oversampling ratio of 12. + 0xB + + + OSR_12 + Oversampling ratio of 13. + 0xC + + + OSR_13 + Oversampling ratio of 14. + 0xD + + + OSR_14 + Oversampling ratio of 15. + 0xE + + + OSR_15 + Oversampling ratio of 16. + 0xF + + + OSR_16 + Oversampling ratio of 17. + 0x10 + + + OSR_17 + Oversampling ratio of 18. + 0x11 + + + OSR_18 + Oversampling ratio of 19. + 0x12 + + + OSR_19 + Oversampling ratio of 20. + 0x13 + + + OSR_20 + Oversampling ratio of 21. + 0x14 + + + OSR_21 + Oversampling ratio of 22. + 0x15 + + + OSR_22 + Oversampling ratio of 23. + 0x16 + + + OSR_23 + Oversampling ratio of 24. + 0x17 + + + OSR_24 + Oversampling ratio of 25. + 0x18 + + + OSR_25 + Oversampling ratio of 26. + 0x19 + + + OSR_26 + Oversampling ratio of 27. + 0x1A + + + OSR_27 + Oversampling ratio of 28. + 0x1B + + + OSR_28 + Oversampling ratio of 29. + 0x1C + + + OSR_29 + Oversampling ratio of 30. + 0x1D + + + OSR_30 + Oversampling ratio of 31. + 0x1E + + + OSR_31 + Oversampling ratio of 32. + 0x1F + + + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + M10_0 + Receiver and transmitter use 7-bit to 9-bit data characters. + 0 + + + M10_1 + Receiver and transmitter use 10-bit data characters. + 0x1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + MAEN2_0 + Normal operation. + 0 + + + MAEN2_1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + 0x1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + MAEN1_0 + Normal operation. + 0 + + + MAEN1_1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + 0x1 + + + + + + + STAT + LPUART Status Register + 0x14 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + oneToClear + + + MA2F_0 + Received data is not equal to MA2 + 0 + + + MA2F_1 + Received data is equal to MA2 + 0x1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + oneToClear + + + MA1F_0 + Received data is not equal to MA1 + 0 + + + MA1F_1 + Received data is equal to MA1 + 0x1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + oneToClear + + + PF_0 + No parity error. + 0 + + + PF_1 + Parity error. + 0x1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + oneToClear + + + FE_0 + No framing error detected. This does not guarantee the framing is correct. + 0 + + + FE_1 + Framing error. + 0x1 + + + + + NF + Noise Flag + 18 + 1 + read-write + oneToClear + + + NF_0 + No noise detected. + 0 + + + NF_1 + Noise detected in the received character in the DATA register. + 0x1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + oneToClear + + + OR_0 + No overrun. + 0 + + + OR_1 + Receive overrun (new LPUART data lost). + 0x1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + oneToClear + + + IDLE_0 + No idle line detected. + 0 + + + IDLE_1 + Idle line was detected. + 0x1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + RDRF_0 + Receive data buffer empty. + 0 + + + RDRF_1 + Receive data buffer full. + 0x1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + TC_0 + Transmitter active (sending data, a preamble, or a break). + 0 + + + TC_1 + Transmitter idle (transmission activity complete). + 0x1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + TDRE_0 + Transmit data buffer full. + 0 + + + TDRE_1 + Transmit data buffer empty. + 0x1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + RAF_0 + LPUART receiver idle waiting for a start bit. + 0 + + + RAF_1 + LPUART receiver active (RXD input not idle). + 0x1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + LBKDE_0 + LIN break detect is disabled, normal break character can be detected. + 0 + + + LBKDE_1 + LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + 0x1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + BRK13_0 + Break character is transmitted with length of 9 to 13 bit times. + 0 + + + BRK13_1 + Break character is transmitted with length of 12 to 15 bit times. + 0x1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + RWUID_0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + 0 + + + RWUID_1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + 0x1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + RXINV_0 + Receive data not inverted. + 0 + + + RXINV_1 + Receive data inverted. + 0x1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + MSBF_0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + 0 + + + MSBF_1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + 0x1 + + + + + RXEDGIF + RXD Pin Active Edge Interrupt Flag + 30 + 1 + read-write + oneToClear + + + RXEDGIF_0 + No active edge on the receive pin has occurred. + 0 + + + RXEDGIF_1 + An active edge on the receive pin has occurred. + 0x1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + oneToClear + + + LBKDIF_0 + No LIN break character has been detected. + 0 + + + LBKDIF_1 + LIN break character has been detected. + 0x1 + + + + + + + CTRL + LPUART Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + PT_0 + Even parity. + 0 + + + PT_1 + Odd parity. + 0x1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + PE_0 + No hardware parity generation or checking. + 0 + + + PE_1 + Parity enabled. + 0x1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + ILT_0 + Idle character bit count starts after start bit. + 0 + + + ILT_1 + Idle character bit count starts after stop bit. + 0x1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + WAKE_0 + Configures RWU for idle-line wakeup. + 0 + + + WAKE_1 + Configures RWU with address-mark wakeup. + 0x1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + M_0 + Receiver and transmitter use 8-bit data characters. + 0 + + + M_1 + Receiver and transmitter use 9-bit data characters. + 0x1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + RSRC_0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + 0 + + + RSRC_1 + Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + 0x1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + DOZEEN_0 + LPUART is enabled in Doze mode. + 0 + + + DOZEEN_1 + LPUART is disabled in Doze mode. + 0x1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + LOOPS_0 + Normal operation - RXD and TXD use separate pins. + 0 + + + LOOPS_1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + 0x1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + IDLECFG_0 + 1 idle character + 0 + + + IDLECFG_1 + 2 idle characters + 0x1 + + + IDLECFG_2 + 4 idle characters + 0x2 + + + IDLECFG_3 + 8 idle characters + 0x3 + + + IDLECFG_4 + 16 idle characters + 0x4 + + + IDLECFG_5 + 32 idle characters + 0x5 + + + IDLECFG_6 + 64 idle characters + 0x6 + + + IDLECFG_7 + 128 idle characters + 0x7 + + + + + M7 + 7-Bit Mode Select + 11 + 1 + read-write + + + M7_0 + Receiver and transmitter use 8-bit to 10-bit data characters. + 0 + + + M7_1 + Receiver and transmitter use 7-bit data characters. + 0x1 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + MA2IE_0 + MA2F interrupt disabled + 0 + + + MA2IE_1 + MA2F interrupt enabled + 0x1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + MA1IE_0 + MA1F interrupt disabled + 0 + + + MA1IE_1 + MA1F interrupt enabled + 0x1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + SBK_0 + Normal transmitter operation. + 0 + + + SBK_1 + Queue break character(s) to be sent. + 0x1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + RWU_0 + Normal receiver operation. + 0 + + + RWU_1 + LPUART receiver in standby waiting for wakeup condition. + 0x1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + RE_0 + Receiver disabled. + 0 + + + RE_1 + Receiver enabled. + 0x1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + TE_0 + Transmitter disabled. + 0 + + + TE_1 + Transmitter enabled. + 0x1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + ILIE_0 + Hardware interrupts from IDLE disabled; use polling. + 0 + + + ILIE_1 + Hardware interrupt requested when IDLE flag is 1. + 0x1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + RIE_0 + Hardware interrupts from RDRF disabled; use polling. + 0 + + + RIE_1 + Hardware interrupt requested when RDRF flag is 1. + 0x1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + TCIE_0 + Hardware interrupts from TC disabled; use polling. + 0 + + + TCIE_1 + Hardware interrupt requested when TC flag is 1. + 0x1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + TIE_0 + Hardware interrupts from TDRE disabled; use polling. + 0 + + + TIE_1 + Hardware interrupt requested when TDRE flag is 1. + 0x1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + PEIE_0 + PF interrupts disabled; use polling). + 0 + + + PEIE_1 + Hardware interrupt requested when PF is set. + 0x1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + FEIE_0 + FE interrupts disabled; use polling. + 0 + + + FEIE_1 + Hardware interrupt requested when FE is set. + 0x1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + NEIE_0 + NF interrupts disabled; use polling. + 0 + + + NEIE_1 + Hardware interrupt requested when NF is set. + 0x1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + ORIE_0 + OR interrupts disabled; use polling. + 0 + + + ORIE_1 + Hardware interrupt requested when OR is set. + 0x1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + TXINV_0 + Transmit data not inverted. + 0 + + + TXINV_1 + Transmit data inverted. + 0x1 + + + + + TXDIR + TXD Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + TXDIR_0 + TXD pin is an input in single-wire mode. + 0 + + + TXDIR_1 + TXD pin is an output in single-wire mode. + 0x1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0x1C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + R0T0 + 0 + 1 + read-write + + + R1T1 + R1T1 + 1 + 1 + read-write + + + R2T2 + R2T2 + 2 + 1 + read-write + + + R3T3 + R3T3 + 3 + 1 + read-write + + + R4T4 + R4T4 + 4 + 1 + read-write + + + R5T5 + R5T5 + 5 + 1 + read-write + + + R6T6 + R6T6 + 6 + 1 + read-write + + + R7T7 + R7T7 + 7 + 1 + read-write + + + R8T8 + R8T8 + 8 + 1 + read-write + + + R9T9 + R9T9 + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + IDLINE_0 + Receiver was not idle before receiving this character. + 0 + + + IDLINE_1 + Receiver was idle before receiving this character. + 0x1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + RXEMPT_0 + Receive buffer contains valid data. + 0 + + + RXEMPT_1 + Receive buffer is empty, data returned on read is not valid. + 0x1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + FRETSC_0 + The dataword was received without a frame error on read, or transmit a normal character on write. + 0 + + + FRETSC_1 + The dataword was received with a frame error, or transmit an idle or break character on transmit. + 0x1 + + + + + PARITYE + PARITYE + 14 + 1 + read-only + + + PARITYE_0 + The dataword was received without a parity error. + 0 + + + PARITYE_1 + The dataword was received with a parity error. + 0x1 + + + + + NOISY + NOISY + 15 + 1 + read-only + + + NOISY_0 + The dataword was received without noise. + 0 + + + NOISY_1 + The data was received with noise. + 0x1 + + + + + + + MATCH + LPUART Match Address Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + TXCTSE_0 + CTS has no effect on the transmitter. + 0 + + + TXCTSE_1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + 0x1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + TXRTSE_0 + The transmitter has no effect on RTS. + 0 + + + TXRTSE_1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + 0x1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + TXRTSPOL_0 + Transmitter RTS is active low. + 0 + + + TXRTSPOL_1 + Transmitter RTS is active high. + 0x1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + RXRTSE_0 + The receiver has no effect on RTS. + 0 + + + RXRTSE_1 + RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + 0x1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + TXCTSC_0 + CTS input is sampled at the start of each character. + 0 + + + TXCTSC_1 + CTS input is sampled when the transmitter is idle. + 0x1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + TXCTSSRC_0 + CTS input is the CTS_B pin. + 0 + + + TXCTSSRC_1 + CTS input is the inverted Receiver Match result. + 0x1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 2 + read-write + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + TNP_0 + 1/OSR. + 0 + + + TNP_1 + 2/OSR. + 0x1 + + + TNP_2 + 3/OSR. + 0x2 + + + TNP_3 + 4/OSR. + 0x3 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + IREN_0 + IR disabled. + 0 + + + IREN_1 + IR enabled. + 0x1 + + + + + + + FIFO + LPUART FIFO Register + 0x28 + 32 + read-write + 0xC00011 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO Buffer Depth + 0 + 3 + read-only + + + RXFIFOSIZE_0 + Receive FIFO/Buffer depth = 1 dataword. + 0 + + + RXFIFOSIZE_1 + Receive FIFO/Buffer depth = 4 datawords. + 0x1 + + + RXFIFOSIZE_2 + Receive FIFO/Buffer depth = 8 datawords. + 0x2 + + + RXFIFOSIZE_3 + Receive FIFO/Buffer depth = 16 datawords. + 0x3 + + + RXFIFOSIZE_4 + Receive FIFO/Buffer depth = 32 datawords. + 0x4 + + + RXFIFOSIZE_5 + Receive FIFO/Buffer depth = 64 datawords. + 0x5 + + + RXFIFOSIZE_6 + Receive FIFO/Buffer depth = 128 datawords. + 0x6 + + + RXFIFOSIZE_7 + Receive FIFO/Buffer depth = 256 datawords. + 0x7 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + RXFE_0 + Receive FIFO is not enabled. Buffer is depth 1. + 0 + + + RXFE_1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + 0x1 + + + + + TXFIFOSIZE + Transmit FIFO Buffer Depth + 4 + 3 + read-only + + + TXFIFOSIZE_0 + Transmit FIFO/Buffer depth = 1 dataword. + 0 + + + TXFIFOSIZE_1 + Transmit FIFO/Buffer depth = 4 datawords. + 0x1 + + + TXFIFOSIZE_2 + Transmit FIFO/Buffer depth = 8 datawords. + 0x2 + + + TXFIFOSIZE_3 + Transmit FIFO/Buffer depth = 16 datawords. + 0x3 + + + TXFIFOSIZE_4 + Transmit FIFO/Buffer depth = 32 datawords. + 0x4 + + + TXFIFOSIZE_5 + Transmit FIFO/Buffer depth = 64 datawords. + 0x5 + + + TXFIFOSIZE_6 + Transmit FIFO/Buffer depth = 128 datawords. + 0x6 + + + TXFIFOSIZE_7 + Transmit FIFO/Buffer depth = 256 datawords + 0x7 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + TXFE_0 + Transmit FIFO is not enabled. Buffer is depth 1. + 0 + + + TXFE_1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + 0x1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + RXUFE_0 + RXUF flag does not generate an interrupt to the host. + 0 + + + RXUFE_1 + RXUF flag generates an interrupt to the host. + 0x1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + TXOFE_0 + TXOF flag does not generate an interrupt to the host. + 0 + + + TXOFE_1 + TXOF flag generates an interrupt to the host. + 0x1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + RXIDEN_0 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + 0 + + + RXIDEN_1 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + 0x1 + + + RXIDEN_2 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + 0x2 + + + RXIDEN_3 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + 0x3 + + + RXIDEN_4 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + 0x4 + + + RXIDEN_5 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + 0x5 + + + RXIDEN_6 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + 0x6 + + + RXIDEN_7 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + 0x7 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + read-write + + + RXFLUSH_0 + No flush operation occurs. + 0 + + + RXFLUSH_1 + All data in the receive FIFO/buffer is cleared out. + 0x1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + read-write + + + TXFLUSH_0 + No flush operation occurs. + 0 + + + TXFLUSH_1 + All data in the transmit FIFO/Buffer is cleared out. + 0x1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + oneToClear + + + RXUF_0 + No receive buffer underflow has occurred since the last time the flag was cleared. + 0 + + + RXUF_1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + oneToClear + + + TXOF_0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + 0 + + + TXOF_1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + RXEMPT_0 + Receive buffer is not empty. + 0 + + + RXEMPT_1 + Receive buffer is empty. + 0x1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + TXEMPT_0 + Transmit buffer is not empty. + 0 + + + TXEMPT_1 + Transmit buffer is empty. + 0x1 + + + + + + + WATER + LPUART Watermark Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 2 + read-write + + + TXCOUNT + Transmit Counter + 8 + 3 + read-only + + + RXWATER + Receive Watermark + 16 + 2 + read-write + + + RXCOUNT + Receive Counter + 24 + 3 + read-only + + + + + + + LPUART2 + LPUART + LPUART + 0x40188000 + + 0 + 0x30 + registers + + + LPUART2 + 21 + + + + LPUART3 + LPUART + LPUART + 0x4018C000 + + 0 + 0x30 + registers + + + LPUART3 + 22 + + + + LPUART4 + LPUART + LPUART + 0x40190000 + + 0 + 0x30 + registers + + + LPUART4 + 23 + + + + FLEXIO1 + FLEXIO + FLEXIO + 0x401AC000 + + 0 + 0x7A0 + registers + + + FLEXIO1 + 90 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard features implemented. + 0 + + + FEATURE_1 + Supports state, logic and parallel modes. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x2200808 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + FLEXEN_0 + FlexIO module is disabled. + 0 + + + FLEXEN_1 + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + SWRST_0 + Software reset is disabled + 0 + + + SWRST_1 + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + FASTACC_0 + Configures for normal register accesses to FlexIO + 0 + + + FASTACC_1 + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + DBGE_0 + FlexIO is disabled in debug modes. + 0 + + + DBGE_1 + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + DOZEN_0 + FlexIO enabled in Doze modes. + 0 + + + DOZEN_1 + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 32 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSF + Shifter Status Flag + 0 + 8 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEF + Shifter Error Flags + 0 + 8 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSF + Timer Status Flags + 0 + 8 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 8 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 8 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 8 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 8 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + 8 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + SMOD_0 + Disabled. + 0 + + + SMOD_1 + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + SMOD_2 + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + SMOD_4 + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + SMOD_5 + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + SMOD_6 + State mode. SHIFTBUF contents are used for storing programmable state attributes. + 0x6 + + + SMOD_7 + Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 5 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Shifter pin output disabled + 0 + + + PINCFG_1 + Shifter pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Shifter pin bidirectional output data + 0x2 + + + PINCFG_3 + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + TIMPOL_0 + Shift on posedge of Shift clock + 0 + + + TIMPOL_1 + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 3 + read-write + + + + + 8 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + SSTART_0 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + SSTART_1 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + SSTART_2 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + SSTART_3 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + SSTOP_0 + Stop bit disabled for transmitter/receiver/match store + 0 + + + SSTOP_2 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + 0x2 + + + SSTOP_3 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + INSRC_0 + Pin + 0 + + + INSRC_1 + Shifter N+1 Output + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 5 + read-write + + + + + 8 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 2 + read-write + + + TIMOD_0 + Timer Disabled. + 0 + + + TIMOD_1 + Dual 8-bit counters baud mode. + 0x1 + + + TIMOD_2 + Dual 8-bit counters PWM high mode. + 0x2 + + + TIMOD_3 + Single 16-bit counter mode. + 0x3 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 5 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Timer pin output disabled + 0 + + + PINCFG_1 + Timer pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Timer pin bidirectional output data + 0x2 + + + PINCFG_3 + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + TRGSRC_0 + External trigger selected + 0 + + + TRGSRC_1 + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + TRGPOL_0 + Trigger active high + 0 + + + TRGPOL_1 + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 6 + read-write + + + + + 8 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + TSTART_0 + Start bit disabled + 0 + + + TSTART_1 + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + TSTOP_0 + Stop bit disabled + 0 + + + TSTOP_1 + Stop bit is enabled on timer compare + 0x1 + + + TSTOP_2 + Stop bit is enabled on timer disable + 0x2 + + + TSTOP_3 + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + TIMENA_0 + Timer always enabled + 0 + + + TIMENA_1 + Timer enabled on Timer N-1 enable + 0x1 + + + TIMENA_2 + Timer enabled on Trigger high + 0x2 + + + TIMENA_3 + Timer enabled on Trigger high and Pin high + 0x3 + + + TIMENA_4 + Timer enabled on Pin rising edge + 0x4 + + + TIMENA_5 + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + TIMENA_6 + Timer enabled on Trigger rising edge + 0x6 + + + TIMENA_7 + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + TIMDIS_0 + Timer never disabled + 0 + + + TIMDIS_1 + Timer disabled on Timer N-1 disable + 0x1 + + + TIMDIS_2 + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + TIMDIS_3 + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + TIMDIS_4 + Timer disabled on Pin rising or falling edge + 0x4 + + + TIMDIS_5 + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + TIMDIS_6 + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + TIMRST_0 + Timer never reset + 0 + + + TIMRST_2 + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + TIMRST_3 + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + TIMRST_4 + Timer reset on Timer Pin rising edge + 0x4 + + + TIMRST_6 + Timer reset on Trigger rising edge + 0x6 + + + TIMRST_7 + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 2 + read-write + + + TIMDEC_0 + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + TIMDEC_1 + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + TIMDEC_2 + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + TIMDEC_3 + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + TIMOUT_0 + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + TIMOUT_1 + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + TIMOUT_2 + Timer output is logic one when enabled and on timer reset + 0x2 + + + TIMOUT_3 + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 8 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 8 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 8 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + + + GPIO1 + GPIO + GPIO + GPIO + 0x401B8000 + + 0 + 0x90 + registers + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + DR + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GDIR + 0 + 32 + read-write + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + PSR + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + ICR0 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + ICR1 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + ICR2 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + ICR3 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + ICR4 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + ICR5 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + ICR6 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + ICR7 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + ICR8 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + ICR9 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + ICR10 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + ICR11 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + ICR12 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + ICR13 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + ICR14 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + ICR15 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + ICR16 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + ICR17 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + ICR18 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + ICR19 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + ICR20 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + ICR21 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + ICR22 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + ICR23 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + ICR24 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + ICR25 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + ICR26 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + ICR27 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + ICR28 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + ICR29 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + ICR30 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + ICR31 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + IMR + 0 + 32 + read-write + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + ISR + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + GPIO_EDGE_SEL + 0 + 32 + read-write + + + + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + + + + + GPIO5 + GPIO + GPIO + 0x400C0000 + + 0 + 0x90 + registers + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + + GPIO2 + GPIO + GPIO + 0x401BC000 + + 0 + 0x90 + registers + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + + GPIO3 + GPIO + GPIO + 0x401C0000 + + 0 + 0x90 + registers + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + + TMR1 + Quad Timer + TMR + TMR1_ + 0x401DC000 + + 0 + 0x7A + registers + + + TMR1 + 133 + + + + 4 + 0x20 + 0,1,2,3 + COMP1%s + Timer Channel Compare Register 1 + 0 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_1 + Comparison Value 1 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + COMP2%s + Timer Channel Compare Register 2 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_2 + Comparison Value 2 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CAPT%s + Timer Channel Capture Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CAPTURE + Capture Value + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + LOAD%s + Timer Channel Load Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + LOAD + Timer Load Register + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + HOLD%s + Timer Channel Hold Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + HOLD + This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CNTR%s + Timer Channel Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + COUNTER + This read/write register is the counter for the corresponding channel in a timer module. + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CTRL%s + Timer Channel Control Register + 0xC + 16 + read-write + 0 + 0xFFFF + + + OUTMODE + Output Mode + 0 + 3 + read-write + + + OUTMODE_0 + Asserted while counter is active + 0 + + + OUTMODE_1 + Clear OFLAG output on successful compare + 0x1 + + + OUTMODE_2 + Set OFLAG output on successful compare + 0x2 + + + OUTMODE_3 + Toggle OFLAG output on successful compare + 0x3 + + + OUTMODE_4 + Toggle OFLAG output using alternating compare registers + 0x4 + + + OUTMODE_5 + Set on compare, cleared on secondary source input edge + 0x5 + + + OUTMODE_6 + Set on compare, cleared on counter rollover + 0x6 + + + OUTMODE_7 + Enable gated clock output while counter is active + 0x7 + + + + + COINIT + Co-Channel Initialization + 3 + 1 + read-write + + + COINIT_0 + Co-channel counter/timers cannot force a re-initialization of this counter/timer + 0 + + + COINIT_1 + Co-channel counter/timers may force a re-initialization of this counter/timer + 0x1 + + + + + DIR + Count Direction + 4 + 1 + read-write + + + DIR_0 + Count up. + 0 + + + DIR_1 + Count down. + 0x1 + + + + + LENGTH + Count Length + 5 + 1 + read-write + + + LENGTH_0 + Count until roll over at $FFFF and continue from $0000. + 0 + + + LENGTH_1 + Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + 0x1 + + + + + ONCE + Count Once + 6 + 1 + read-write + + + ONCE_0 + Count repeatedly. + 0 + + + ONCE_1 + Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + 0x1 + + + + + SCS + Secondary Count Source + 7 + 2 + read-write + + + SCS_0 + Counter 0 input pin + 0 + + + SCS_1 + Counter 1 input pin + 0x1 + + + SCS_2 + Counter 2 input pin + 0x2 + + + SCS_3 + Counter 3 input pin + 0x3 + + + + + PCS + Primary Count Source + 9 + 4 + read-write + + + PCS_0 + Counter 0 input pin + 0 + + + PCS_1 + Counter 1 input pin + 0x1 + + + PCS_2 + Counter 2 input pin + 0x2 + + + PCS_3 + Counter 3 input pin + 0x3 + + + PCS_4 + Counter 0 output + 0x4 + + + PCS_5 + Counter 1 output + 0x5 + + + PCS_6 + Counter 2 output + 0x6 + + + PCS_7 + Counter 3 output + 0x7 + + + PCS_8 + IP bus clock divide by 1 prescaler + 0x8 + + + PCS_9 + IP bus clock divide by 2 prescaler + 0x9 + + + PCS_10 + IP bus clock divide by 4 prescaler + 0xA + + + PCS_11 + IP bus clock divide by 8 prescaler + 0xB + + + PCS_12 + IP bus clock divide by 16 prescaler + 0xC + + + PCS_13 + IP bus clock divide by 32 prescaler + 0xD + + + PCS_14 + IP bus clock divide by 64 prescaler + 0xE + + + PCS_15 + IP bus clock divide by 128 prescaler + 0xF + + + + + CM + Count Mode + 13 + 3 + read-write + + + CM_0 + No operation + 0 + + + CM_1 + Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + 0x1 + + + CM_2 + Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + 0x2 + + + CM_3 + Count rising edges of primary source while secondary input high active + 0x3 + + + CM_4 + Quadrature count mode, uses primary and secondary sources + 0x4 + + + CM_5 + Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + 0x5 + + + CM_6 + Edge of secondary source triggers primary count until compare + 0x6 + + + CM_7 + Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + 0x7 + + + + + + + 4 + 0x20 + 0,1,2,3 + SCTRL%s + Timer Channel Status and Control Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + OEN + Output Enable + 0 + 1 + read-write + + + OEN_0 + The external pin is configured as an input. + 0 + + + OEN_1 + The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + 0x1 + + + + + OPS + Output Polarity Select + 1 + 1 + read-write + + + OPS_0 + True polarity. + 0 + + + OPS_1 + Inverted polarity. + 0x1 + + + + + FORCE + Force OFLAG Output + 2 + 1 + read-write + + + VAL + Forced OFLAG Value + 3 + 1 + read-write + + + EEOF + Enable External OFLAG Force + 4 + 1 + read-write + + + MSTR + Master Mode + 5 + 1 + read-write + + + CAPTURE_MODE + Input Capture Mode + 6 + 2 + read-write + + + CAPTURE_MODE_0 + Capture function is disabled + 0 + + + CAPTURE_MODE_1 + Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + 0x1 + + + CAPTURE_MODE_2 + Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + 0x2 + + + CAPTURE_MODE_3 + Load capture register on both edges of input + 0x3 + + + + + INPUT + External Input Signal + 8 + 1 + read-only + + + IPS + Input Polarity Select + 9 + 1 + read-write + + + IEFIE + Input Edge Flag Interrupt Enable + 10 + 1 + read-write + + + IEF + Input Edge Flag + 11 + 1 + read-write + + + TOFIE + Timer Overflow Flag Interrupt Enable + 12 + 1 + read-write + + + TOF + Timer Overflow Flag + 13 + 1 + read-write + + + TCFIE + Timer Compare Flag Interrupt Enable + 14 + 1 + read-write + + + TCF + Timer Compare Flag + 15 + 1 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD1%s + Timer Channel Comparator Load Register 1 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_1 + This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD2%s + Timer Channel Comparator Load Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_2 + This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CSCTRL%s + Timer Channel Comparator Status and Control Register + 0x14 + 16 + read-write + 0 + 0xFFFF + + + CL1 + Compare Load Control 1 + 0 + 2 + read-write + + + CL1_0 + Never preload + 0 + + + CL1_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL1_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + CL2 + Compare Load Control 2 + 2 + 2 + read-write + + + CL2_0 + Never preload + 0 + + + CL2_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL2_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + TCF1 + Timer Compare 1 Interrupt Flag + 4 + 1 + read-write + + + TCF2 + Timer Compare 2 Interrupt Flag + 5 + 1 + read-write + + + TCF1EN + Timer Compare 1 Interrupt Enable + 6 + 1 + read-write + + + TCF2EN + Timer Compare 2 Interrupt Enable + 7 + 1 + read-write + + + UP + Counting Direction Indicator + 9 + 1 + read-only + + + UP_0 + The last count was in the DOWN direction. + 0 + + + UP_1 + The last count was in the UP direction. + 0x1 + + + + + TCI + Triggered Count Initialization Control + 10 + 1 + read-write + + + TCI_0 + Stop counter upon receiving a second trigger event while still counting from the first trigger event. + 0 + + + TCI_1 + Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + 0x1 + + + + + ROC + Reload on Capture + 11 + 1 + read-write + + + ROC_0 + Do not reload the counter on a capture event. + 0 + + + ROC_1 + Reload the counter on a capture event. + 0x1 + + + + + ALT_LOAD + Alternative Load Enable + 12 + 1 + read-write + + + ALT_LOAD_0 + Counter can be re-initialized only with the LOAD register. + 0 + + + ALT_LOAD_1 + Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + 0x1 + + + + + FAULT + Fault Enable + 13 + 1 + read-write + + + FAULT_0 + Fault function disabled. + 0 + + + FAULT_1 + Fault function enabled. + 0x1 + + + + + DBG_EN + Debug Actions Enable + 14 + 2 + read-write + + + DBG_EN_0 + Continue with normal operation during debug mode. (default) + 0 + + + DBG_EN_1 + Halt TMR counter during debug mode. + 0x1 + + + DBG_EN_2 + Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + 0x2 + + + DBG_EN_3 + Both halt counter and force output to 0 during debug mode. + 0x3 + + + + + + + 4 + 0x20 + 0,1,2,3 + FILT%s + Timer Channel Input Filter Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + DMA%s + Timer Channel DMA Enable Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + IEFDE + Input Edge Flag DMA Enable + 0 + 1 + read-write + + + CMPLD1DE + Comparator Preload Register 1 DMA Enable + 1 + 1 + read-write + + + CMPLD2DE + Comparator Preload Register 2 DMA Enable + 2 + 1 + read-write + + + + + ENBL + Timer Channel Enable Register + 0x1E + 16 + read-write + 0xF + 0xFFFF + + + ENBL + Timer Channel Enable + 0 + 4 + read-write + + + ENBL_0 + Timer channel is disabled. + 0 + + + ENBL_1 + Timer channel is enabled. (default) + 0x1 + + + + + + + + + GPT1 + GPT + GPT + GPT1_ + GPT + 0x401EC000 + + 0 + 0x28 + registers + + + GPT1 + 100 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 10 + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 15 + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 16 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 18 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 20 + 3 + read-write + + + OM2 + See OM3 + 23 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 26 + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + OM3_4 + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + See F03 + 29 + 1 + read-write + + + FO2 + See F03 + 30 + 1 + read-write + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 31 + 1 + read-write + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 12 + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x401F0000 + + 0 + 0x28 + registers + + + GPT2 + 101 + + + + OCOTP + no description available + OCOTP + 0x401F4000 + + 0 + 0x6F4 + registers + + + + HW_OCOTP_CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + + + BUSY + OTP controller status bit + 8 + 1 + read-only + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + + + + + HW_OCOTP_CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToSet + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToSet + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + oneToSet + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + oneToSet + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + oneToSet + + + + + HW_OCOTP_CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToClear + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToClear + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + oneToClear + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + oneToClear + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + oneToClear + + + + + HW_OCOTP_CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + OTP write and read access address register + 0 + 6 + read-write + oneToToggle + + + BUSY + OTP controller status bit + 8 + 1 + read-only + oneToToggle + + + ERROR + Set by the controller when an access to a locked region(OTP or shadow register) is requested + 9 + 1 + read-write + oneToToggle + + + RELOAD_SHADOWS + Set to force re-loading the shadow registers (HW/SW capability and LOCK) + 10 + 1 + read-write + oneToToggle + + + WR_UNLOCK + Write 0x3E77 to enable OTP write accesses + 16 + 16 + read-write + oneToToggle + + + + + HW_OCOTP_TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x60D9755 + 0xFFFFFFFF + + + STROBE_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX + This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd + 12 + 4 + read-write + + + STROBE_READ + This count value specifies the strobe period in one time read OTP + 16 + 6 + read-write + + + WAIT + This count value specifies time interval between auto read and write access in one time program + 22 + 6 + read-write + + + + + HW_OCOTP_DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Used to initiate a write to OTP + 0 + 32 + read-write + + + + + HW_OCOTP_READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + Used to initiate a read to OTP + 0 + 1 + read-write + + + + + HW_OCOTP_READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + The data read from OTP + 0 + 32 + read-write + + + + + HW_OCOTP_SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRK_REVOKE_LOCK + Shadow register write and OTP write lock for SRK_REVOKE region + 1 + 1 + read-write + + + FIELD_RETURN_LOCK + Shadow register write and OTP write lock for FIELD_RETURN region + 2 + 1 + read-write + + + + + HW_OCOTP_SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + + + + + HW_OCOTP_SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToSet + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + oneToSet + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + oneToSet + + + + + HW_OCOTP_SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToClear + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + oneToClear + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + oneToClear + + + + + HW_OCOTP_SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB JTAG Debug Enable + 0 + 1 + read-write + oneToToggle + + + SPARE + Unallocated read/write bits for implementation specific software use. + 1 + 30 + read-write + oneToToggle + + + LOCK + When set, all of the bits in this register are locked and can not be changed through SW programming + 31 + 1 + read-write + oneToToggle + + + + + HW_OCOTP_VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + HW_OCOTP_TIMING2 + OTP Controller Timing Register 2 + 0x100 + 32 + read-write + 0x1C30092 + 0xFFFFFFFF + + + RELAX_PROG + This count value specifies the strobe period in one time write OTP + 0 + 12 + read-write + + + RELAX_READ + This count value specifies the strobe period in one time read OTP + 16 + 6 + read-write + + + RELAX1 + This count value specifies time interval between auto read and write access in one time program + 22 + 7 + read-write + + + + + HW_OCOTP_LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + Status of shadow register and OTP write lock for tester region + 0 + 2 + read-only + + + BOOT_CFG + Status of shadow register and OTP write lock for boot_cfg region + 2 + 2 + read-only + + + MEM_TRIM + Status of shadow register and OTP write lock for mem_trim region + 4 + 2 + read-only + + + SJC_RESP + Status of shadow register read and write, OTP read and write lock for sjc_resp region + 6 + 1 + read-only + + + MAC_ADDR + Status of shadow register and OTP write lock for mac_addr region + 8 + 2 + read-only + + + GP1 + Status of shadow register and OTP write lock for gp1 region + 10 + 2 + read-only + + + GP2 + Status of shadow register and OTP write lock for gp2 region + 12 + 2 + read-only + + + OTPMK_MSB + Status of shadow register read and write, OTP read and write lock for otpmk region (MSB) + 15 + 1 + read-only + + + SW_GP1 + Status of shadow register and OTP write lock for sw_gp1 region + 16 + 1 + read-only + + + OTPMK_LSB + Status of shadow register read and write, OTP read and write lock for otpmk region (LSB) + 17 + 1 + read-only + + + ANALOG + Status of shadow register and OTP write lock for analog region + 18 + 2 + read-only + + + OTPMK_CRC + Status of shadow register and OTP write lock for otpmk_crc region + 20 + 1 + read-only + + + SW_GP2_LOCK + Status of shadow register and OTP write lock for sw_gp2 region + 21 + 1 + read-only + + + MISC_CONF + Status of shadow register and OTP write lock for misc_conf region + 22 + 1 + read-only + + + SW_GP2_RLOCK + Status of shadow register and OTP read lock for sw_gp2 region + 23 + 1 + read-only + + + GP3 + Status of shadow register and OTP write lock for gp3 region + 26 + 2 + read-only + + + FIELD_RETURN + Reserved + 28 + 4 + read-write + + + + + HW_OCOTP_CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + HW_OCOTP_CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + This register contains 32 bits of the Unique ID and SJC_CHALLENGE field + 0 + 32 + read-write + + + + + HW_OCOTP_CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 4 (ADDR = 0x04) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 5 (ADDR = 0x05) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 6 (ADDR = 0x06) + 0 + 32 + read-write + + + + + HW_OCOTP_CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 0, word 7 (ADDR = 0x07) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 0 (ADDR = 0x08) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 1 (ADDR = 0x09) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 2 (ADDR = 0x0A) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 3 (ADDR = 0x0B) + 0 + 32 + read-write + + + + + HW_OCOTP_MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 4 (ADDR = 0x0C) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA0 + Value of OTP Bank1 Word5 (Analog Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 5 (ADDR = 0x0D) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA1 + Value of OTP Bank1 Word6 (Analog Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 6 (ADDR = 0x0E) + 0 + 32 + read-write + + + + + HW_OCOTP_ANA2 + Value of OTP Bank1 Word7 (Analog Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP bank 1, word 7 (ADDR = 0x0F) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22)) + 0 + 32 + read-write + + + + + HW_OCOTP_SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23)) + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)) + 0 + 32 + read-write + + + + + HW_OCOTP_SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)) + 0 + 32 + read-write + + + + + HW_OCOTP_MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). + 0 + 32 + read-write + + + + + HW_OCOTP_MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). + 0 + 32 + read-write + + + + + HW_OCOTP_GP3 + Value of OTP Bank4 Word4 (MAC Address) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). + 0 + 32 + read-write + + + + + HW_OCOTP_GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). + 0 + 32 + read-write + + + + + HW_OCOTP_GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP1 + Value of OTP Bank5 Word0 (SW GP1) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP20 + Value of OTP Bank5 Word1 (SW GP2) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP21 + Value of OTP Bank5 Word2 (SW GP2) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP22 + Value of OTP Bank5 Word3 (SW GP2) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). + 0 + 32 + read-write + + + + + HW_OCOTP_SW_GP23 + Value of OTP Bank5 Word4 (SW GP2) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF0 + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). + 0 + 32 + read-write + + + + + HW_OCOTP_MISC_CONF1 + Value of OTP Bank5 Word6 (Misc Conf) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). + 0 + 32 + read-write + + + + + HW_OCOTP_SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). + 0 + 32 + read-write + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x401F8000 + + 0 + 0x4C4 + registers + + + + SW_MUX_CTL_PAD_GPIO_EMC_04 + SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register + 0x24 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT04 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_OUT of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO16 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_JTAG_ACT of instance: sjc + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_05 + SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register + 0x28 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT05 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SPDIF_IN of instance: spdif + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO17 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SJC_DE_B of instance: sjc + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_06 + SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register + 0x2C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT06 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO18 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_07 + SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register + 0x30 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT07 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO19 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_08 + SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register + 0x34 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT08 of instance: xbar1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO20 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_09 + SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register + 0x38 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT09 of instance: xbar1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO21 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_16 + SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register + 0x54 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: MQS_RIGHT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_MCLK of instance: sai2 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_MODE00 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_17 + SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register + 0x58 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_MODE01 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_18 + SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO22 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_19 + SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_XBAR_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO23 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_20 + SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO24 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_21 + SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO25 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_22 + SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO26 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_23 + SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO27 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_24 + SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO28 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO24 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_24 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_25 + SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO29 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO25 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_25 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_26 + SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO30 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO26 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_26 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_27 + SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO31 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO27 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: src + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_27 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_32 + SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER0 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: REF_24M_OUT of instance: anatop + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_32 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_33 + SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER1 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_33 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_34 + SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER2 of instance: qtimer1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_34 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_35 + SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER3 of instance: qtimer1 + 0x1 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_35 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_00 + SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: jtag_mux + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_01 + SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: jtag_mux + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_02 + SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: jtag_mux + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_03 + SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_TDI of instance: jtag_mux + 0 + + + ALT2 + Select mux mode: ALT2 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: usb + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: CCM_PMIC_RDY of instance: ccm + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_04 + SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_TDO of instance: jtag_mux + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: usb + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: EWM_EWM_OUT_B of instance: ewm + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_05 + SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: jtag_mux + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USB_OTG1_ID of instance: anatop + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_06 + SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register + 0xD4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PIT_TRIGGER00 of instance: pit + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + 0x2 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_07 + SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register + 0xD8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: PIT_TRIGGER01 of instance: pit + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1 + 0x2 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: REF_24M_OUT of instance: anatop + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_08 + SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register + 0xDC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL00 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ARM_CM7_TXEV of instance: cm7_mxrt + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_09 + SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register + 0xE0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW00 of instance: kpp + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSU_CSU_INT_DEB of instance: csu + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ARM_CM7_RXEV of instance: cm7_mxrt + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_10 + SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register + 0xE4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI1_SCK of instance: lpspi1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL01 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_11 + SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register + 0xE8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW01 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_12 + SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI1_SDO of instance: lpspi1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_13 + SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI1_SDI of instance: lpspi1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW02 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_14 + SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_COL03 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: WDOG1_WDOG_ANY of instance: wdog1 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_15 + SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: KPP_ROW03 of instance: kpp + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_10 + SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_11 + SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_12 + SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT00 of instance: acmp + 0x1 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO03 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_13 + SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C1_HREQ of instance: lpi2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT01 of instance: acmp + 0x1 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO02 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_14 + SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: lpi2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT02 of instance: acmp + 0x1 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO01 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_15 + SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: lpi2c1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT03 of instance: acmp + 0x1 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_DI0_EXT_CLK of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_00 + SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA03 of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_XBAR_INOUT10 of instance: xbar1 + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_01 + SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_SCLK of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXSPI_A_SS1_B of instance: flexspi + 0x3 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_02 + SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA00 of instance: flexspi + 0x1 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_03 + SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA02 of instance: flexspi + 0x1 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_04 + SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_B_DATA01 of instance: flexspi + 0x1 + + + ALT4 + Select mux mode: ALT4 mux port: EWM_EWM_OUT_B of instance: ewm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_05 + SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DQS of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPI_B_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_RDY of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_06 + SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA03 of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_07 + SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_08 + SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA00 of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SDO of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO28 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_09 + SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO29 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_REF_EN_B of instance: ccm + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_10 + SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO30 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_11 + SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi + 0x1 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO31 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_11 + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_04 + SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register + 0x198 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_05 + SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register + 0x19C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_06 + SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register + 0x1A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_07 + SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register + 0x1A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_08 + SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register + 0x1A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_09 + SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register + 0x1AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_16 + SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register + 0x1C8 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_17 + SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register + 0x1CC + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_18 + SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register + 0x1D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_19 + SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register + 0x1D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_20 + SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register + 0x1D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_21 + SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register + 0x1DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_22 + SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register + 0x1E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_23 + SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register + 0x1E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_24 + SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register + 0x1E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_25 + SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register + 0x1EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_26 + SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register + 0x1F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_27 + SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register + 0x1F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_32 + SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register + 0x208 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_33 + SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register + 0x20C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_34 + SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register + 0x210 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_35 + SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register + 0x214 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_00 + SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register + 0x230 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_01 + SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register + 0x234 + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_02 + SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register + 0x238 + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_03 + SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register + 0x23C + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_04 + SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register + 0x240 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_05 + SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register + 0x244 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_06 + SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register + 0x248 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_07 + SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register + 0x24C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_08 + SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register + 0x250 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_09 + SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register + 0x254 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_10 + SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register + 0x258 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_11 + SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register + 0x25C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_12 + SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register + 0x260 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_13 + SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register + 0x264 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_14 + SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register + 0x268 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_15 + SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register + 0x26C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_10 + SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register + 0x298 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_11 + SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register + 0x29C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_12 + SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register + 0x2A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_13 + SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register + 0x2A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_14 + SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register + 0x2A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_15 + SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register + 0x2AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_00 + SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register + 0x2CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_01 + SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register + 0x2D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_02 + SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register + 0x2D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_03 + SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register + 0x2D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_04 + SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register + 0x2DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_05 + SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register + 0x2E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_06 + SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register + 0x2E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_07 + SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_08 + SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_09 + SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_10 + SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_11 + SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + ANATOP_USB_OTG_ID_SELECT_INPUT + ANATOP_USB_OTG_ID_SELECT_INPUT DAISY Register + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_05_ALT6 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6 + 0 + + + GPIO_AD_B1_11_ALT0 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0 + 0x1 + + + + + + + CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT + CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT DAISY Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_05_ALT6 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT6 + 0x1 + + + GPIO_AD_B0_03_ALT7 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT7 + 0x2 + + + + + + + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 DAISY Register + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT1 + Selecting Pad: GPIO_EMC_26 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 DAISY Register + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT1 + Selecting Pad: GPIO_EMC_24 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 DAISY Register + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_10_ALT1 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT1 + 0 + + + GPIO_EMC_22_ALT1 + Selecting Pad: GPIO_EMC_22 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_3 + FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_3 DAISY Register + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_12_ALT6 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT6 + 0 + + + GPIO_EMC_20_ALT1 + Selecting Pad: GPIO_EMC_20 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 DAISY Register + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT1 + Selecting Pad: GPIO_EMC_27 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 DAISY Register + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT1 + Selecting Pad: GPIO_EMC_25 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 DAISY Register + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_11_ALT1 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT1 + 0 + + + GPIO_EMC_23_ALT1 + Selecting Pad: GPIO_EMC_23 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_3 + FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_3 DAISY Register + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_13_ALT6 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT6 + 0 + + + GPIO_EMC_21_ALT1 + Selecting Pad: GPIO_EMC_21 for Mode: ALT1 + 0x1 + + + + + + + FLEXSPI_IPP_IND_IO_FA_BIT0_SELECT_INPUT + FLEXSPI_IPP_IND_IO_FA_BIT0_SELECT_INPUT DAISY Register + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT1 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT1 + 0 + + + + + + + FLEXSPI_IPP_IND_IO_FA_BIT1_SELECT_INPUT + FLEXSPI_IPP_IND_IO_FA_BIT1_SELECT_INPUT DAISY Register + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT1 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT1 + 0 + + + + + + + FLEXSPI_IPP_IND_IO_FA_BIT2_SELECT_INPUT + FLEXSPI_IPP_IND_IO_FA_BIT2_SELECT_INPUT DAISY Register + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT1 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT1 + 0 + + + + + + + FLEXSPI_IPP_IND_IO_FA_BIT3_SELECT_INPUT + FLEXSPI_IPP_IND_IO_FA_BIT3_SELECT_INPUT DAISY Register + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_06_ALT1 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT1 + 0 + + + + + + + FLEXSPI_IPP_IND_SCK_FA_SELECT_INPUT + FLEXSPI_IPP_IND_SCK_FA_SELECT_INPUT DAISY Register + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT1 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT1 + 0 + + + + + + + LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT + LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_14_ALT0 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT0 + 0x1 + + + + + + + LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT + LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_15_ALT0 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT0 + 0x1 + + + + + + + LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT + LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT2 + Selecting Pad: GPIO_EMC_19 for Mode: ALT2 + 0x1 + + + + + + + LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT + LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_18_ALT2 + Selecting Pad: GPIO_EMC_18 for Mode: ALT2 + 0x1 + + + + + + + LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 + LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_11_ALT1 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT1 + 0x1 + + + + + + + LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT + LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_10_ALT1 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT1 + 0x1 + + + + + + + LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT + LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_13_ALT1 + Selecting Pad: GPIO_AD_B0_13 for Mode: ALT1 + 0x1 + + + + + + + LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT + LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_12_ALT1 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + 0x1 + + + + + + + LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 + LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_06_ALT4 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT4 + 0x2 + + + + + + + LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT + LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_07_ALT4 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT4 + 0x2 + + + + + + + LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT + LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_09_ALT4 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT4 + 0x2 + + + + + + + LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT + LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_08_ALT4 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT4 + 0x2 + + + + + + + LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT + LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT DAISY Register + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT2 + Selecting Pad: GPIO_EMC_20 for Mode: ALT2 + 0x1 + + + + + + + LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT + LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT2 + Selecting Pad: GPIO_EMC_23 for Mode: ALT2 + 0x1 + + + + + + + LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT + LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_22_ALT2 + Selecting Pad: GPIO_EMC_22 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT + LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT2 + Selecting Pad: GPIO_EMC_07 for Mode: ALT2 + 0 + + + GPIO_AD_B0_15_ALT2 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT + LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT2 + Selecting Pad: GPIO_EMC_06 for Mode: ALT2 + 0 + + + GPIO_AD_B0_14_ALT2 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT2 + 0x1 + + + + + + + LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT + LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT DAISY Register + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT + LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_11_ALT2 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT2 + 0x1 + + + GPIO_EMC_33_ALT2 + Selecting Pad: GPIO_EMC_33 for Mode: ALT2 + 0x2 + + + + + + + LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT + LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_10_ALT2 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT2 + 0x1 + + + GPIO_EMC_32_ALT2 + Selecting Pad: GPIO_EMC_32 for Mode: ALT2 + 0x2 + + + + + + + NMI_GLUE_IPP_IND_NMI_SELECT_INPUT + NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_05_ALT7 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT7 + 0 + + + WAKEUP_ALT7 + Selecting Pad: WAKEUP for Mode: ALT7 + 0x1 + + + + + + + QTIMER1_TMR0_INPUT_SELECT_INPUT + QTIMER1_TMR0_INPUT_SELECT_INPUT DAISY Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_32_ALT1 + Selecting Pad: GPIO_EMC_32 for Mode: ALT1 + 0x1 + + + + + + + QTIMER1_TMR1_INPUT_SELECT_INPUT + QTIMER1_TMR1_INPUT_SELECT_INPUT DAISY Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_33_ALT1 + Selecting Pad: GPIO_EMC_33 for Mode: ALT1 + 0x1 + + + + + + + QTIMER1_TMR2_INPUT_SELECT_INPUT + QTIMER1_TMR2_INPUT_SELECT_INPUT DAISY Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_34_ALT1 + Selecting Pad: GPIO_EMC_34 for Mode: ALT1 + 0x1 + + + + + + + QTIMER1_TMR3_INPUT_SELECT_INPUT + QTIMER1_TMR3_INPUT_SELECT_INPUT DAISY Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_35_ALT1 + Selecting Pad: GPIO_EMC_35 for Mode: ALT1 + 0x1 + + + + + + + SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 + SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_03_ALT3 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT3 + 0x1 + + + GPIO_EMC_20_ALT3 + Selecting Pad: GPIO_EMC_20 for Mode: ALT3 + 0x3 + + + + + + + SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT + SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_19_ALT3 + Selecting Pad: GPIO_EMC_19 for Mode: ALT3 + 0x2 + + + + + + + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_21_ALT3 + Selecting Pad: GPIO_EMC_21 for Mode: ALT3 + 0x2 + + + + + + + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 DAISY Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_22_ALT3 + Selecting Pad: GPIO_EMC_22 for Mode: ALT3 + 0x1 + + + + + + + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 DAISY Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT3 + Selecting Pad: GPIO_EMC_23 for Mode: ALT3 + 0x1 + + + + + + + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 + SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 DAISY Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT3 + Selecting Pad: GPIO_EMC_24 for Mode: ALT3 + 0x1 + + + + + + + SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT + SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_18_ALT3 + Selecting Pad: GPIO_EMC_18 for Mode: ALT3 + 0x2 + + + + + + + SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT + SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_26_ALT3 + Selecting Pad: GPIO_EMC_26 for Mode: ALT3 + 0x2 + + + + + + + SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT + SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_27_ALT3 + Selecting Pad: GPIO_EMC_27 for Mode: ALT3 + 0x2 + + + + + + + SAI2_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 + SAI2_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_16_ALT3 + Selecting Pad: GPIO_EMC_16 for Mode: ALT3 + 0x1 + + + + + + + SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT + SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT3 + Selecting Pad: GPIO_EMC_09 for Mode: ALT3 + 0x1 + + + + + + + SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 + SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT3 + Selecting Pad: GPIO_EMC_08 for Mode: ALT3 + 0x1 + + + + + + + SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT + SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT3 + Selecting Pad: GPIO_EMC_07 for Mode: ALT3 + 0x1 + + + + + + + SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT + SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT3 + Selecting Pad: GPIO_EMC_04 for Mode: ALT3 + 0x1 + + + + + + + SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT + SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT3 + Selecting Pad: GPIO_EMC_05 for Mode: ALT3 + 0x1 + + + + + + + SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 + SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_05_ALT3 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT3 + 0 + + + GPIO_EMC_17_ALT3 + Selecting Pad: GPIO_EMC_17 for Mode: ALT3 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT3 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT3 + 0 + + + + + + + SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 + SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT3 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT3 + 0 + + + + + + + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT3 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT3 + 0 + + + + + + + SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT + SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_06_ALT3 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT3 + 0 + + + GPIO_EMC_33_ALT3 + Selecting Pad: GPIO_EMC_33 for Mode: ALT3 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT + SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT3 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT3 + 0 + + + GPIO_EMC_34_ALT3 + Selecting Pad: GPIO_EMC_34 for Mode: ALT3 + 0x1 + + + + + + + SPDIF_SPDIF_IN1_SELECT_INPUT + SPDIF_SPDIF_IN1_SELECT_INPUT DAISY Register + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT2 + Selecting Pad: GPIO_EMC_05 for Mode: ALT2 + 0 + + + + + + + USB_IPP_IND_OTG_OC_SELECT_INPUT + USB_IPP_IND_OTG_OC_SELECT_INPUT DAISY Register + 0x48C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_03_ALT6 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT6 + 0 + + + GPIO_AD_B1_12_ALT0 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT0 + 0x1 + + + + + + + XBAR1_XBAR_IN_SELECT_INPUT_14 + XBAR1_XBAR_IN_SELECT_INPUT_14 DAISY Register + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + XBAR1_XBAR_IN_SELECT_INPUT_15 + XBAR1_XBAR_IN_SELECT_INPUT_15 DAISY Register + 0x4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + XBAR1_XBAR_IN_SELECT_INPUT_16 + XBAR1_XBAR_IN_SELECT_INPUT_16 DAISY Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_18_ALT1 + Selecting Pad: GPIO_EMC_18 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_XBAR_IN_SELECT_INPUT_17 + XBAR1_XBAR_IN_SELECT_INPUT_17 DAISY Register + 0x4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT1 + Selecting Pad: GPIO_EMC_19 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_XBAR_IN_SELECT_INPUT_10 + XBAR1_XBAR_IN_SELECT_INPUT_10 DAISY Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT3 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_XBAR_IN_SELECT_INPUT_12 + XBAR1_XBAR_IN_SELECT_INPUT_12 DAISY Register + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + XBAR1_XBAR_IN_SELECT_INPUT_13 + XBAR1_XBAR_IN_SELECT_INPUT_13 DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + XBAR1_XBAR_IN_SELECT_INPUT_18 + XBAR1_XBAR_IN_SELECT_INPUT_18 DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + XBAR1_XBAR_IN_SELECT_INPUT_19 + XBAR1_XBAR_IN_SELECT_INPUT_19 DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x401FC000 + + 0 + 0x8 + registers + + + KPP + 39 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 2 + 1 + read-write + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 3 + 1 + read-write + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 8 + 8 + read-write + + + + + + + FLEXSPI + FlexSPI + FlexSPI + 0x402A8000 + + 0 + 0x400 + registers + + + FLEXSPI + 108 + + + + MCR0 + Module Control Register 0 + 0 + 32 + read-write + 0xFFFF80C2 + 0xFFFFFFFF + + + SWRESET + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + RXCLKSRC + Sample Clock source selection for Flash Reading + 4 + 2 + read-write + + + RXCLKSRC_0 + Dummy Read strobe generated by FlexSPI Controller and loopback internally. + 0 + + + RXCLKSRC_1 + Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + 0x1 + + + RXCLKSRC_3 + Flash provided Read strobe and input from DQS pad + 0x3 + + + + + ARDFEN + Enable AHB bus Read Access to IP RX FIFO. + 6 + 1 + read-write + + + ARDFEN_0 + IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + 0 + + + ARDFEN_1 + IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + 0x1 + + + + + ATDFEN + Enable AHB bus Write Access to IP TX FIFO. + 7 + 1 + read-write + + + ATDFEN_0 + IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + 0 + + + ATDFEN_1 + IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + 0x1 + + + + + HSEN + Half Speed Serial Flash access Enable. + 11 + 1 + read-write + + + HSEN_0 + Disable divide by 2 of serial flash clock for half speed commands. + 0 + + + HSEN_1 + Enable divide by 2 of serial flash clock for half speed commands. + 0x1 + + + + + DOZEEN + Doze mode enable bit + 12 + 1 + read-write + + + DOZEEN_0 + Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + 0 + + + DOZEEN_1 + Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + 0x1 + + + + + COMBINATIONEN + This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + 13 + 1 + read-write + + + COMBINATIONEN_0 + Disable. + 0 + + + COMBINATIONEN_1 + Enable. + 0x1 + + + + + SCKFREERUNEN + This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + 14 + 1 + read-write + + + SCKFREERUNEN_0 + Disable. + 0 + + + SCKFREERUNEN_1 + Enable. + 0x1 + + + + + IPGRANTWAIT + Time out wait cycle for IP command grant. + 16 + 8 + read-write + + + AHBGRANTWAIT + Timeout wait cycle for AHB command grant. + 24 + 8 + read-write + + + + + MCR1 + Module Control Register 1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + AHBBUSWAIT + AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response + 0 + 16 + read-write + + + SEQWAIT + Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles + 16 + 16 + read-write + + + + + MCR2 + Module Control Register 2 + 0x8 + 32 + read-write + 0x200081F7 + 0xFFFFFFFF + + + CLRAHBBUFOPT + This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + 11 + 1 + read-write + + + CLRAHBBUFOPT_0 + AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + 0 + + + CLRAHBBUFOPT_1 + AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + 0x1 + + + + + CLRLEARNPHASE + The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. + 14 + 1 + read-write + + + SAMEDEVICEEN + All external devices are same devices (both in types and size) for A1/A2/B1/B2. + 15 + 1 + read-write + + + SAMEDEVICEEN_0 + In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + 0 + + + SAMEDEVICEEN_1 + FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + 0x1 + + + + + SCKBDIFFOPT + SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + 19 + 1 + read-write + + + SCKBDIFFOPT_0 + SCKB pad is used as port B SCK clock output. Port B flash access is available. + 0 + + + SCKBDIFFOPT_1 + SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + 0x1 + + + + + RESUMEWAIT + Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + 24 + 8 + read-write + + + + + AHBCR + AHB Bus Control Register + 0xC + 32 + read-write + 0x18 + 0xFFFFFFFF + + + APAREN + Parallel mode enabled for AHB triggered Command (both read and write) . + 0 + 1 + read-write + + + APAREN_0 + Flash will be accessed in Individual mode. + 0 + + + APAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + CACHABLEEN + Enable AHB bus cachable read access support. + 3 + 1 + read-write + + + CACHABLEEN_0 + Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + 0 + + + CACHABLEEN_1 + Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + 0x1 + + + + + BUFFERABLEEN + Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + 4 + 1 + read-write + + + BUFFERABLEEN_0 + Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + 0 + + + BUFFERABLEEN_1 + Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + 0x1 + + + + + PREFETCHEN + AHB Read Prefetch Enable. + 5 + 1 + read-write + + + READADDROPT + AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + 6 + 1 + read-write + + + READADDROPT_0 + There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + 0 + + + READADDROPT_1 + There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + 0x1 + + + + + + + INTEN + Interrupt Enable Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP triggered Command Sequences Execution finished interrupt enable. + 0 + 1 + read-write + + + IPCMDGEEN + IP triggered Command Sequences Grant Timeout interrupt enable. + 1 + 1 + read-write + + + AHBCMDGEEN + AHB triggered Command Sequences Grant Timeout interrupt enable. + 2 + 1 + read-write + + + IPCMDERREN + IP triggered Command Sequences Error Detected interrupt enable. + 3 + 1 + read-write + + + AHBCMDERREN + AHB triggered Command Sequences Error Detected interrupt enable. + 4 + 1 + read-write + + + IPRXWAEN + IP RX FIFO WaterMark available interrupt enable. + 5 + 1 + read-write + + + IPTXWEEN + IP TX FIFO WaterMark empty interrupt enable. + 6 + 1 + read-write + + + SCKSTOPBYRDEN + SCK is stopped during command sequence because Async RX FIFO full interrupt enable. + 8 + 1 + read-write + + + SCKSTOPBYWREN + SCK is stopped during command sequence because Async TX FIFO empty interrupt enable. + 9 + 1 + read-write + + + AHBBUSTIMEOUTEN + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + + + SEQTIMEOUTEN + Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. + 11 + 1 + read-write + + + + + INTR + Interrupt Register + 0x14 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + IPCMDDONE + IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. + 0 + 1 + read-write + oneToClear + + + IPCMDGE + IP triggered Command Sequences Grant Timeout interrupt. + 1 + 1 + read-write + oneToClear + + + AHBCMDGE + AHB triggered Command Sequences Grant Timeout interrupt. + 2 + 1 + read-write + oneToClear + + + IPCMDERR + IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. + 3 + 1 + read-write + oneToClear + + + AHBCMDERR + AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. + 4 + 1 + read-write + oneToClear + + + IPRXWA + IP RX FIFO watermark available interrupt. + 5 + 1 + read-write + oneToClear + + + IPTXWE + IP TX FIFO watermark empty interrupt. + 6 + 1 + read-write + oneToClear + + + SCKSTOPBYRD + SCK is stopped during command sequence because Async RX FIFO full interrupt. + 8 + 1 + read-write + oneToClear + + + SCKSTOPBYWR + SCK is stopped during command sequence because Async TX FIFO empty interrupt. + 9 + 1 + read-write + oneToClear + + + AHBBUSTIMEOUT + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + oneToClear + + + SEQTIMEOUT + Sequence execution timeout interrupt. + 11 + 1 + read-write + oneToClear + + + + + LUTKEY + LUT Key Register + 0x18 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The Key to lock or unlock LUT. + 0 + 32 + read-write + + + + + LUTCR + LUT Control Register + 0x1C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Lock LUT + 0 + 1 + read-write + + + UNLOCK + Unlock LUT + 1 + 1 + read-write + + + + + AHBRXBUF0CR0 + AHB RX Buffer 0 Control Register 0 + 0x20 + 32 + read-write + 0x80000020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 + Flash A1 Control Register 0 + 0x60 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHA2CR0 + Flash A2 Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash B1 Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash B2 Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR1%s + Flash A1 Control Register 1 + 0x70 + 32 + read-write + 0x63 + 0xFFFFFFFF + + + TCSS + Serial Flash CS setup time. + 0 + 5 + read-write + + + TCSH + Serial Flash CS Hold time. + 5 + 5 + read-write + + + WA + Word Addressable. + 10 + 1 + read-write + + + CAS + Column Address Size. + 11 + 4 + read-write + + + CSINTERVALUNIT + CS interval unit + 15 + 1 + read-write + + + CSINTERVALUNIT_0 + The CS interval unit is 1 serial clock cycle + 0 + + + CSINTERVALUNIT_1 + The CS interval unit is 256 serial clock cycle + 0x1 + + + + + CSINTERVAL + This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. + 16 + 16 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR2%s + Flash A1 Control Register 2 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARDSEQID + Sequence Index for AHB Read triggered Command in LUT. + 0 + 4 + read-write + + + ARDSEQNUM + Sequence Number for AHB Read triggered Command in LUT. + 5 + 3 + read-write + + + AWRSEQID + Sequence Index for AHB Write triggered Command. + 8 + 4 + read-write + + + AWRSEQNUM + Sequence Number for AHB Write triggered Command. + 13 + 3 + read-write + + + AWRWAIT + For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface + 16 + 12 + read-write + + + AWRWAITUNIT + AWRWAIT unit + 28 + 3 + read-write + + + AWRWAITUNIT_0 + The AWRWAIT unit is 2 ahb clock cycle + 0 + + + AWRWAITUNIT_1 + The AWRWAIT unit is 8 ahb clock cycle + 0x1 + + + AWRWAITUNIT_2 + The AWRWAIT unit is 32 ahb clock cycle + 0x2 + + + AWRWAITUNIT_3 + The AWRWAIT unit is 128 ahb clock cycle + 0x3 + + + AWRWAITUNIT_4 + The AWRWAIT unit is 512 ahb clock cycle + 0x4 + + + AWRWAITUNIT_5 + The AWRWAIT unit is 2048 ahb clock cycle + 0x5 + + + AWRWAITUNIT_6 + The AWRWAIT unit is 8192 ahb clock cycle + 0x6 + + + AWRWAITUNIT_7 + The AWRWAIT unit is 32768 ahb clock cycle + 0x7 + + + + + CLRINSTRPTR + Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. + 31 + 1 + read-write + + + + + FLSHCR4 + Flash Control Register 4 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMOPT1 + Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + 0 + 1 + read-write + + + WMOPT1_0 + DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0 + + + WMOPT1_1 + DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0x1 + + + + + WMENA + Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + 2 + 1 + read-write + + + WMENA_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENA_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + WMENB + Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + 3 + 1 + read-write + + + WMENB_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENB_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + + + IPCR0 + IP Control Register 0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFAR + Serial Flash Address for IP command. + 0 + 32 + read-write + + + + + IPCR1 + IP Control Register 1 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + Flash Read/Program Data Size (in Bytes) for IP command. + 0 + 16 + read-write + + + ISEQID + Sequence Index in LUT for IP command. + 16 + 4 + read-write + + + ISEQNUM + Sequence Number for IP command: ISEQNUM+1. + 24 + 3 + read-write + + + IPAREN + Parallel mode Enabled for IP command. + 31 + 1 + read-write + + + IPAREN_0 + Flash will be accessed in Individual mode. + 0 + + + IPAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + + + IPCMD + IP Command Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRG + Setting this bit will trigger an IP Command. + 0 + 1 + read-write + + + + + IPRXFCR + IP RX FIFO Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPRXF + Clear all valid data entries in IP RX FIFO. + 0 + 1 + read-write + + + RXDMAEN + IP RX FIFO reading by DMA enabled. + 1 + 1 + read-write + + + RXDMAEN_0 + IP RX FIFO would be read by processor. + 0 + + + RXDMAEN_1 + IP RX FIFO would be read by DMA. + 0x1 + + + + + RXWMRK + Watermark level is (RXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + IPTXFCR + IP TX FIFO Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPTXF + Clear all valid data entries in IP TX FIFO. + 0 + 1 + read-write + + + TXDMAEN + IP TX FIFO filling by DMA enabled. + 1 + 1 + read-write + + + TXDMAEN_0 + IP TX FIFO would be filled by processor. + 0 + + + TXDMAEN_1 + IP TX FIFO would be filled by DMA. + 0x1 + + + + + TXWMRK + Watermark level is (TXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + 2 + 0x4 + A,B + DLLCR%s + DLL Control Register 0 + 0xC0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DLLEN + DLL calibration enable. + 0 + 1 + read-write + + + DLLRESET + Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). + 1 + 1 + read-write + + + SLVDLYTARGET + The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock). + 3 + 4 + read-write + + + OVRDEN + Slave clock delay line delay cell number selection override enable. + 8 + 1 + read-write + + + OVRDVAL + Slave clock delay line delay cell number selection override value. + 9 + 6 + read-write + + + + + STS0 + Status Register 0 + 0xE0 + 32 + read-only + 0x3 + 0xFFFFFFFF + + + SEQIDLE + This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. + 0 + 1 + read-only + + + ARBIDLE + This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + 1 + 1 + read-only + + + ARBCMDSRC + This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + 2 + 2 + read-only + + + ARBCMDSRC_0 + Triggered by AHB read command (triggered by AHB read). + 0 + + + ARBCMDSRC_1 + Triggered by AHB write command (triggered by AHB Write). + 0x1 + + + ARBCMDSRC_2 + Triggered by IP command (triggered by setting register bit IPCMD.TRG). + 0x2 + + + ARBCMDSRC_3 + Triggered by suspended command (resumed). + 0x3 + + + + + + + STS1 + Status Register 1 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHBCMDERRID + Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 0 + 4 + read-only + + + AHBCMDERRCODE + Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 8 + 4 + read-only + + + AHBCMDERRCODE_0 + No error. + 0 + + + AHBCMDERRCODE_2 + AHB Write command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + AHBCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + AHBCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + AHBCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + AHBCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + + + IPCMDERRID + Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 16 + 4 + read-only + + + IPCMDERRCODE + Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 24 + 4 + read-only + + + IPCMDERRCODE_0 + No error. + 0 + + + IPCMDERRCODE_2 + IP command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + IPCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + IPCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + IPCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + IPCMDERRCODE_6 + Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + 0x6 + + + IPCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + IPCMDERRCODE_15 + Flash boundary crossed. + 0xF + + + + + + + STS2 + Status Register 2 + 0xE8 + 32 + read-only + 0x1000100 + 0xFFFFFFFF + + + ASLVLOCK + Flash A sample clock slave delay line locked. + 0 + 1 + read-only + + + AREFLOCK + Flash A sample clock reference delay line locked. + 1 + 1 + read-only + + + ASLVSEL + Flash A sample clock slave delay line delay cell number selection . + 2 + 6 + read-only + + + AREFSEL + Flash A sample clock reference delay line delay cell number selection. + 8 + 6 + read-only + + + BSLVLOCK + Flash B sample clock slave delay line locked. + 16 + 1 + read-only + + + BREFLOCK + Flash B sample clock reference delay line locked. + 17 + 1 + read-only + + + BSLVSEL + Flash B sample clock slave delay line delay cell number selection. + 18 + 6 + read-only + + + BREFSEL + Flash B sample clock reference delay line delay cell number selection. + 24 + 6 + read-only + + + + + AHBSPNDSTS + AHB Suspend Status Register + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + ACTIVE + Indicates if an AHB read prefetch command sequence has been suspended. + 0 + 1 + read-only + + + BUFID + AHB RX BUF ID for suspended command sequence. + 1 + 3 + read-only + + + DATLFT + Left Data size for suspended command sequence (in byte). + 16 + 16 + read-only + + + + + IPRXFSTS + IP RX FIFO Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP RX FIFO. + 0 + 8 + read-only + + + RDCNTR + Total Read Data Counter: RDCNTR * 64 Bits. + 16 + 16 + read-only + + + + + IPTXFSTS + IP TX FIFO Status Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP TX FIFO. + 0 + 8 + read-only + + + WRCNTR + Total Write Data Counter: WRCNTR * 64 Bits. + 16 + 16 + read-only + + + + + 32 + 0x4 + RFDR[%s] + IP RX FIFO Data Register 0 + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-only + + + + + 32 + 0x4 + TFDR[%s] + IP TX FIFO Data Register 0 + 0x180 + 32 + write-only + 0 + 0xFFFFFFFF + + + TXDATA + TX Data + 0 + 32 + write-only + + + + + 64 + 0x4 + LUT[%s] + LUT 0 + 0x200 + 32 + read-write + 0 + 0 + + + OPERAND0 + OPERAND0 + 0 + 8 + read-write + + + NUM_PADS0 + NUM_PADS0 + 8 + 2 + read-write + + + OPCODE0 + OPCODE + 10 + 6 + read-write + + + OPERAND1 + OPERAND1 + 16 + 8 + read-write + + + NUM_PADS1 + NUM_PADS1 + 24 + 2 + read-write + + + OPCODE1 + OPCODE1 + 26 + 6 + read-write + + + + + + + USB + USB + USB + USB_ + 0x402E0000 + + 0 + 0x1E0 + registers + + + USB_OTG1 + 113 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 16 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 16 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 12 + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 16 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 20 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 24 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 1 + 1 + read-write + + + FS_1 + See description at bit 15 + 2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 11 + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 13 + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 14 + 1 + read-write + + + FS_2 + Frame List Size - (Read/Write or Read Only) + 15 + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 16 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 3 + 1 + read-write + + + SEI + System Error- R/WC + 4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 6 + 1 + read-write + + + SRI + SOF Received - R/WC + 7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 10 + 1 + read-write + + + HCH + HCHaIted - Read Only + 12 + 1 + read-write + + + RCL + Reclamation - Read Only + 13 + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 14 + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 15 + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 16 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 24 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 25 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 10 + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 16 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 18 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 19 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 24 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 25 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 24 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 25 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 16 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 16 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 16 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 9 + 1 + read-only + + + LS + Line Status-Read Only + 10 + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 12 + 1 + read-write + + + PO + Port Owner-Read/Write + 13 + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 14 + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 16 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 20 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 21 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 22 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 23 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 24 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 25 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 26 + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 28 + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 29 + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 30 + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 11 + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 12 + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 13 + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 14 + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 16 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 17 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 18 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 19 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 20 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 21 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 22 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 26 + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 27 + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 28 + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 29 + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 30 + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 16 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 16 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 16 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 18 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 23 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + + + USBNC + USB + USB + USBNC + USBNC_ + 0x402E0000 + + 0 + 0x81C + registers + + + + USB_OTG1_CTRL + USB OTG1 Control Register + 0x800 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTG1 Overcurrent Detection + 7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event + 8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity. + 9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt + 10 + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTG1 Software Wake-up Enable + 14 + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTG1 Software Wake-up + 15 + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTG1 Wake-up on ID change enable + 16 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTG1 wake-up on VBUS change enable + 17 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WKUP_DPDM_EN + Wake-up on DPDM change enable + 29 + 1 + read-write + + + WKUP_DPDM_EN_0 + DPDM changes wake-up to be disabled only when VBUS is 0. + 0 + + + WKUP_DPDM_EN_1 + (Default) DPDM changes wake-up to be enabled, it is for device only. + 0x1 + + + + + WIR + OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port + 31 + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTG1_PHY_CTRL_0 + OTG1 UTMI PHY Control 0 Register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTG1 UTMI PHY clock is valid + 31 + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x402FC000 + + 0 + 0x434 + registers + + + DCP + 50 + + + DCP_VMI + 51 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 29 + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 31 + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + AES128 + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 16 + 16 + read-only + + + SHA1 + SHA1 + 0x1 + + + CRC32 + CRC32 + 0x2 + + + SHA256 + SHA256 + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected hashing function should be enabled for this operation. + 4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 8 + 1 + read-only + + + DECRYPT + DECRYPT + 0 + + + ENCRYPT + ENCRYPT + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 10 + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 11 + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 12 + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 13 + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 14 + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 15 + 1 + read-only + + + INPUT + INPUT + 0 + + + OUTPUT + OUTPUT + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 16 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 17 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 18 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 19 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 20 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 21 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 22 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 23 + 1 + read-only + + + TAG + Packet Tag + 24 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + AES128 + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 4 + 4 + read-only + + + ECB + ECB + 0 + + + CBC + CBC + 0x1 + + + + + KEY_SELECT + Key selection field + 8 + 8 + read-only + + + KEY0 + KEY0 + 0 + + + KEY1 + KEY1 + 0x1 + + + KEY2 + KEY2 + 0x2 + + + KEY3 + KEY3 + 0x3 + + + UNIQUE_KEY + UNIQUE_KEY + 0xFE + + + OTP_KEY + OTP_KEY + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 16 + 4 + read-only + + + SHA1 + SHA1 + 0 + + + CRC32 + CRC32 + 0x1 + + + SHA256 + SHA256 + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 24 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + CONTROL + 0x1 + + + OTPKEY0 + OTPKEY0 + 0x10 + + + OTPKEY1 + OTPKEY1 + 0x11 + + + OTPKEY2 + OTPKEY2 + 0x12 + + + OTPKEY3 + OTPKEY3 + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 1 + 1 + read-write + + + BASE + Page table base address + 2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 24 + 8 + read-only + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x40380000 + + 0 + 0x54 + registers + + + SPDIF + 60 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 12 + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 13 + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. + 7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + TxClk_Source_0 + XTALOSC input (XTALOSC clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_2 + tx_clk1 (from SAI1) + 0x2 + + + TxClk_Source_3 + tx_clk2 SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_4 + tx_clk3 (from SAI2) + 0x4 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + TxClk_Source_6 + tx_clk4 (from SAI3) + 0x6 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 11 + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + SAI1 + I2S + I2S + I2S + 0x40384000 + + 0 + 0xE4 + registers + + + SAI1 + 56 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50504 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO reads (from transmit shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO writes (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + TDR[%s] + SAI Transmit Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + read-write + + + + + 4 + 0x4 + TFR[%s] + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + WCP + Write Channel Pointer + 31 + 1 + read-only + + + WCP_0 + No effect. + 0 + + + WCP_1 + FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + 0x1 + + + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO writes (from receive shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO reads (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + RDR[%s] + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + 4 + 0x4 + RFR[%s] + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + RCP + Receive Channel Pointer + 15 + 1 + read-only + + + RCP_0 + No effect. + 0 + + + RCP_1 + FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + 0x1 + + + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + SAI2 + I2S + I2S + 0x40388000 + + 0 + 0xE4 + registers + + + SAI2 + 57 + + + + SAI3 + I2S + I2S + 0x4038C000 + + 0 + 0xE4 + registers + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + + LPSPI1 + LPSPI + LPSPI + LPSPI + 0x40394000 + + 0 + 0x78 + registers + + + LPSPI1 + 32 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1020004 + 0xFFFFFFFF + + + FEATURE + Module Identification Number + 0 + 16 + read-only + + + FEATURE_4 + Standard feature set supporting a 32-bit shift register. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x40404 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + PCSNUM + PCS Number + 16 + 8 + read-only + + + + + CR + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Module Enable + 0 + 1 + read-write + + + MEN_0 + Module is disabled + 0 + + + MEN_1 + Module is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Master logic is not reset + 0 + + + RST_1 + Master logic is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Module is enabled in Doze mode + 0 + + + DOZEN_1 + Module is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Module is disabled in debug mode + 0 + + + DBGEN_1 + Module is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + SR + Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + WCF + Word Complete Flag + 8 + 1 + read-write + oneToClear + + + WCF_0 + Transfer of a received word has not yet completed + 0 + + + WCF_1 + Transfer of a received word has completed + 0x1 + + + + + FCF + Frame Complete Flag + 9 + 1 + read-write + oneToClear + + + FCF_0 + Frame transfer has not completed + 0 + + + FCF_1 + Frame transfer has completed + 0x1 + + + + + TCF + Transfer Complete Flag + 10 + 1 + read-write + oneToClear + + + TCF_0 + All transfers have not completed + 0 + + + TCF_1 + All transfers have completed + 0x1 + + + + + TEF + Transmit Error Flag + 11 + 1 + read-write + oneToClear + + + TEF_0 + Transmit FIFO underrun has not occurred + 0 + + + TEF_1 + Transmit FIFO underrun has occurred + 0x1 + + + + + REF + Receive Error Flag + 12 + 1 + read-write + oneToClear + + + REF_0 + Receive FIFO has not overflowed + 0 + + + REF_1 + Receive FIFO has overflowed + 0x1 + + + + + DMF + Data Match Flag + 13 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Module Busy Flag + 24 + 1 + read-only + + + MBF_0 + LPSPI is idle + 0 + + + MBF_1 + LPSPI is busy + 0x1 + + + + + + + IER + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + WCIE + Word Complete Interrupt Enable + 8 + 1 + read-write + + + WCIE_0 + Disabled + 0 + + + WCIE_1 + Enabled + 0x1 + + + + + FCIE + Frame Complete Interrupt Enable + 9 + 1 + read-write + + + FCIE_0 + Disabled + 0 + + + FCIE_1 + Enabled + 0x1 + + + + + TCIE + Transfer Complete Interrupt Enable + 10 + 1 + read-write + + + TCIE_0 + Disabled + 0 + + + TCIE_1 + Enabled + 0x1 + + + + + TEIE + Transmit Error Interrupt Enable + 11 + 1 + read-write + + + TEIE_0 + Disabled + 0 + + + TEIE_1 + Enabled + 0x1 + + + + + REIE + Receive Error Interrupt Enable + 12 + 1 + read-write + + + REIE_0 + Disabled + 0 + + + REIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 13 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + DER + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + CFGR0 + Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request is disabled + 0 + + + HREN_1 + Host request is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is the LPSPI_HREQ pin + 0 + + + HRSEL_1 + Host request input is the input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO as in normal operations + 0 + + + RDMO_1 + Received data is discarded unless the Data Match Flag (DMF) is set + 0x1 + + + + + + + CFGR1 + Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER + Master Mode + 0 + 1 + read-write + + + MASTER_0 + Slave mode + 0 + + + MASTER_1 + Master mode + 0x1 + + + + + SAMPLE + Sample Point + 1 + 1 + read-write + + + SAMPLE_0 + Input data is sampled on SCK edge + 0 + + + SAMPLE_1 + Input data is sampled on delayed SCK edge + 0x1 + + + + + AUTOPCS + Automatic PCS + 2 + 1 + read-write + + + AUTOPCS_0 + Automatic PCS generation is disabled + 0 + + + AUTOPCS_1 + Automatic PCS generation is enabled + 0x1 + + + + + NOSTALL + No Stall + 3 + 1 + read-write + + + NOSTALL_0 + Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + 0 + + + NOSTALL_1 + Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + 0x1 + + + + + PCSPOL + Peripheral Chip Select Polarity + 8 + 4 + read-write + + + PCSPOL_0 + The Peripheral Chip Select pin PCSx is active low + 0 + + + PCSPOL_1 + The Peripheral Chip Select pin PCSx is active high + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + 0x2 + + + MATCFG_3 + 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + 0x3 + + + MATCFG_4 + 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + 0x4 + + + MATCFG_5 + 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + 0x5 + + + MATCFG_6 + 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + 0x6 + + + MATCFG_7 + 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 2 + read-write + + + PINCFG_0 + SIN is used for input data and SOUT is used for output data + 0 + + + PINCFG_1 + SIN is used for both input and output data + 0x1 + + + PINCFG_2 + SOUT is used for both input and output data + 0x2 + + + PINCFG_3 + SOUT is used for input data and SIN is used for output data + 0x3 + + + + + OUTCFG + Output Config + 26 + 1 + read-write + + + OUTCFG_0 + Output data retains last value when chip select is negated + 0 + + + OUTCFG_1 + Output data is tristated when chip select is negated + 0x1 + + + + + PCSCFG + Peripheral Chip Select Configuration + 27 + 1 + read-write + + + PCSCFG_0 + PCS[3:2] are enabled + 0 + + + PCSCFG_1 + PCS[3:2] are disabled + 0x1 + + + + + + + DMR0 + Data Match Register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 32 + read-write + + + + + DMR1 + Data Match Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH1 + Match 1 Value + 0 + 32 + read-write + + + + + CCR + Clock Configuration Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKDIV + SCK Divider + 0 + 8 + read-write + + + DBT + Delay Between Transfers + 8 + 8 + read-write + + + PCSSCK + PCS-to-SCK Delay + 16 + 8 + read-write + + + SCKPCS + SCK-to-PCS Delay + 24 + 8 + read-write + + + + + FCR + FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 4 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 4 + read-write + + + + + FSR + FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 5 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 5 + read-only + + + + + TCR + Transmit Command Register + 0x60 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + FRAMESZ + Frame Size + 0 + 12 + read-write + + + WIDTH + Transfer Width + 16 + 2 + read-write + + + WIDTH_0 + 1 bit transfer + 0 + + + WIDTH_1 + 2 bit transfer + 0x1 + + + WIDTH_2 + 4 bit transfer + 0x2 + + + + + TXMSK + Transmit Data Mask + 18 + 1 + read-write + + + TXMSK_0 + Normal transfer + 0 + + + TXMSK_1 + Mask transmit data + 0x1 + + + + + RXMSK + Receive Data Mask + 19 + 1 + read-write + + + RXMSK_0 + Normal transfer + 0 + + + RXMSK_1 + Receive data is masked + 0x1 + + + + + CONTC + Continuing Command + 20 + 1 + read-write + + + CONTC_0 + Command word for start of new transfer + 0 + + + CONTC_1 + Command word for continuing transfer + 0x1 + + + + + CONT + Continuous Transfer + 21 + 1 + read-write + + + CONT_0 + Continuous transfer is disabled + 0 + + + CONT_1 + Continuous transfer is enabled + 0x1 + + + + + BYSW + Byte Swap + 22 + 1 + read-write + + + BYSW_0 + Byte swap is disabled + 0 + + + BYSW_1 + Byte swap is enabled + 0x1 + + + + + LSBF + LSB First + 23 + 1 + read-write + + + LSBF_0 + Data is transferred MSB first + 0 + + + LSBF_1 + Data is transferred LSB first + 0x1 + + + + + PCS + Peripheral Chip Select + 24 + 2 + read-write + + + PCS_0 + Transfer using LPSPI_PCS[0] + 0 + + + PCS_1 + Transfer using LPSPI_PCS[1] + 0x1 + + + PCS_2 + Transfer using LPSPI_PCS[2] + 0x2 + + + PCS_3 + Transfer using LPSPI_PCS[3] + 0x3 + + + + + PRESCALE + Prescaler Value + 27 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + CPHA + Clock Phase + 30 + 1 + read-write + + + CPHA_0 + Data is captured on the leading edge of SCK and changed on the following edge of SCK + 0 + + + CPHA_1 + Data is changed on the leading edge of SCK and captured on the following edge of SCK + 0x1 + + + + + CPOL + Clock Polarity + 31 + 1 + read-write + + + CPOL_0 + The inactive state value of SCK is low + 0 + + + CPOL_1 + The inactive state value of SCK is high + 0x1 + + + + + + + TDR + Transmit Data Register + 0x64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 32 + write-only + + + + + RSR + Receive Status Register + 0x70 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SOF + Start Of Frame + 0 + 1 + read-only + + + SOF_0 + Subsequent data word received after LPSPI_PCS assertion + 0 + + + SOF_1 + First data word received after LPSPI_PCS assertion + 0x1 + + + + + RXEMPTY + RX FIFO Empty + 1 + 1 + read-only + + + RXEMPTY_0 + RX FIFO is not empty + 0 + + + RXEMPTY_1 + RX FIFO is empty + 0x1 + + + + + + + RDR + Receive Data Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + + + LPSPI2 + LPSPI + LPSPI + 0x40398000 + + 0 + 0x78 + registers + + + LPSPI2 + 33 + + + + ADC_ETC + ADC_ETC + ADC_ETC + 0x403B0000 + + 0 + 0x150 + registers + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + + CTRL + ADC_ETC Global Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + TRIG_ENABLE + TRIG enable register + 0 + 8 + read-write + + + EXT0_TRIG_ENABLE + TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger. + 8 + 1 + read-write + + + EXT0_TRIG_PRIORITY + External TSC0 trigger priority, 7 is Highest, 0 is lowest . + 9 + 3 + read-write + + + EXT1_TRIG_ENABLE + TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger. + 12 + 1 + read-write + + + EXT1_TRIG_PRIORITY + External TSC1 trigger priority, 7 is Highest, 0 is lowest . + 13 + 3 + read-write + + + PRE_DIVIDER + Pre-divider for trig delay and interval . + 16 + 8 + read-write + + + DMA_MODE_SEL + 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared + 29 + 1 + read-write + + + TSC_BYPASS + 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. + 30 + 1 + read-write + + + SOFTRST + Software reset, high active. When write 1 ,all logical will be reset. + 31 + 1 + read-write + + + + + DONE0_1_IRQ + ETC DONE0 and DONE1 IRQ State Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE0 + TRIG0 done0 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE0 + TRIG1 done0 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE0 + TRIG2 done0 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE0 + TRIG3 done0 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE0 + TRIG4 done0 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE0 + TRIG5 done0 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE0 + TRIG6 done0 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE0 + TRIG7 done0 interrupt detection + 7 + 1 + read-write + + + TRIG0_DONE1 + TRIG0 done1 interrupt detection + 16 + 1 + read-write + + + TRIG1_DONE1 + TRIG1 done1 interrupt detection + 17 + 1 + read-write + + + TRIG2_DONE1 + TRIG2 done1 interrupt detection + 18 + 1 + read-write + + + TRIG3_DONE1 + TRIG3 done1 interrupt detection + 19 + 1 + read-write + + + TRIG4_DONE1 + TRIG4 done1 interrupt detection + 20 + 1 + read-write + + + TRIG5_DONE1 + TRIG5 done1 interrupt detection + 21 + 1 + read-write + + + TRIG6_DONE1 + TRIG6 done1 interrupt detection + 22 + 1 + read-write + + + TRIG7_DONE1 + TRIG7 done1 interrupt detection + 23 + 1 + read-write + + + + + DONE2_ERR_IRQ + ETC DONE_2 and DONE_ERR IRQ State Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE2 + TRIG0 done2 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE2 + TRIG1 done2 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE2 + TRIG2 done2 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE2 + TRIG3 done2 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE2 + TRIG4 done2 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE2 + TRIG5 done2 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE2 + TRIG6 done2 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE2 + TRIG7 done2 interrupt detection + 7 + 1 + read-write + + + TRIG0_ERR + TRIG0 error interrupt detection + 16 + 1 + read-write + + + TRIG1_ERR + TRIG1 error interrupt detection + 17 + 1 + read-write + + + TRIG2_ERR + TRIG2 error interrupt detection + 18 + 1 + read-write + + + TRIG3_ERR + TRIG3 error interrupt detection + 19 + 1 + read-write + + + TRIG4_ERR + TRIG4 error interrupt detection + 20 + 1 + read-write + + + TRIG5_ERR + TRIG5 error interrupt detection + 21 + 1 + read-write + + + TRIG6_ERR + TRIG6 error interrupt detection + 22 + 1 + read-write + + + TRIG7_ERR + TRIG7 error interrupt detection + 23 + 1 + read-write + + + + + DMA_CTRL + ETC DMA control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_ENABLE + When TRIG0 done enable DMA request + 0 + 1 + read-write + + + TRIG1_ENABLE + When TRIG1 done enable DMA request + 1 + 1 + read-write + + + TRIG2_ENABLE + When TRIG2 done enable DMA request + 2 + 1 + read-write + + + TRIG3_ENABLE + When TRIG3 done enable DMA request + 3 + 1 + read-write + + + TRIG4_ENABLE + When TRIG4 done enable DMA request + 4 + 1 + read-write + + + TRIG5_ENABLE + When TRIG5 done enable DMA request + 5 + 1 + read-write + + + TRIG6_ENABLE + When TRIG6 done enable DMA request + 6 + 1 + read-write + + + TRIG7_ENABLE + When TRIG7 done enable DMA request + 7 + 1 + read-write + + + TRIG0_REQ + When TRIG0 done DMA request detection + 16 + 1 + read-write + + + TRIG1_REQ + When TRIG1 done DMA request detection + 17 + 1 + read-write + + + TRIG2_REQ + When TRIG2 done DMA request detection + 18 + 1 + read-write + + + TRIG3_REQ + When TRIG3 done DMA request detection + 19 + 1 + read-write + + + TRIG4_REQ + When TRIG4 done DMA request detection + 20 + 1 + read-write + + + TRIG5_REQ + When TRIG5 done DMA request detection + 21 + 1 + read-write + + + TRIG6_REQ + When TRIG6 done DMA request detection + 22 + 1 + read-write + + + TRIG7_REQ + When TRIG7 done DMA request detection + 23 + 1 + read-write + + + + + TRIG0_CTRL + ETC_TRIG0 Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG0_COUNTER + ETC_TRIG0 Counter Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG0_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG0_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG0_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG0_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG0_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG0_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG1_CTRL + ETC_TRIG1 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG1_COUNTER + ETC_TRIG1 Counter Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG1_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG1_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG1_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG1_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG1_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG1_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG2_CTRL + ETC_TRIG2 Control Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG2_COUNTER + ETC_TRIG2 Counter Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG2_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG2_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG2_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG2_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG2_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG2_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG3_CTRL + ETC_TRIG3 Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG3_COUNTER + ETC_TRIG3 Counter Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG3_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG3_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG3_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG3_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG3_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xA8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG3_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + + + AOI + AND/OR/INVERT module + AOI + AOI_ + 0x403B4000 + + 0 + 0x10 + registers + + + + 4 + 0x4 + 0,1,2,3 + BFCRT01%s + Boolean Function Term 0 and 1 Configuration Register for EVENTn + 0 + 16 + read-write + 0 + 0xFFFF + + + PT1_DC + Product term 1, D input configuration + 0 + 2 + read-write + + + PT1_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT1_DC_1 + Pass the D input in this product term + 0x1 + + + PT1_DC_2 + Complement the D input in this product term + 0x2 + + + PT1_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT1_CC + Product term 1, C input configuration + 2 + 2 + read-write + + + PT1_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT1_CC_1 + Pass the C input in this product term + 0x1 + + + PT1_CC_2 + Complement the C input in this product term + 0x2 + + + PT1_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT1_BC + Product term 1, B input configuration + 4 + 2 + read-write + + + PT1_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT1_BC_1 + Pass the B input in this product term + 0x1 + + + PT1_BC_2 + Complement the B input in this product term + 0x2 + + + PT1_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT1_AC + Product term 1, A input configuration + 6 + 2 + read-write + + + PT1_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT1_AC_1 + Pass the A input in this product term + 0x1 + + + PT1_AC_2 + Complement the A input in this product term + 0x2 + + + PT1_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT0_DC + Product term 0, D input configuration + 8 + 2 + read-write + + + PT0_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT0_DC_1 + Pass the D input in this product term + 0x1 + + + PT0_DC_2 + Complement the D input in this product term + 0x2 + + + PT0_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT0_CC + Product term 0, C input configuration + 10 + 2 + read-write + + + PT0_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT0_CC_1 + Pass the C input in this product term + 0x1 + + + PT0_CC_2 + Complement the C input in this product term + 0x2 + + + PT0_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT0_BC + Product term 0, B input configuration + 12 + 2 + read-write + + + PT0_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT0_BC_1 + Pass the B input in this product term + 0x1 + + + PT0_BC_2 + Complement the B input in this product term + 0x2 + + + PT0_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT0_AC + Product term 0, A input configuration + 14 + 2 + read-write + + + PT0_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT0_AC_1 + Pass the A input in this product term + 0x1 + + + PT0_AC_2 + Complement the A input in this product term + 0x2 + + + PT0_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + 4 + 0x4 + 0,1,2,3 + BFCRT23%s + Boolean Function Term 2 and 3 Configuration Register for EVENTn + 0x2 + 16 + read-write + 0 + 0xFFFF + + + PT3_DC + Product term 3, D input configuration + 0 + 2 + read-write + + + PT3_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT3_DC_1 + Pass the D input in this product term + 0x1 + + + PT3_DC_2 + Complement the D input in this product term + 0x2 + + + PT3_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT3_CC + Product term 3, C input configuration + 2 + 2 + read-write + + + PT3_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT3_CC_1 + Pass the C input in this product term + 0x1 + + + PT3_CC_2 + Complement the C input in this product term + 0x2 + + + PT3_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT3_BC + Product term 3, B input configuration + 4 + 2 + read-write + + + PT3_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT3_BC_1 + Pass the B input in this product term + 0x1 + + + PT3_BC_2 + Complement the B input in this product term + 0x2 + + + PT3_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT3_AC + Product term 3, A input configuration + 6 + 2 + read-write + + + PT3_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT3_AC_1 + Pass the A input in this product term + 0x1 + + + PT3_AC_2 + Complement the A input in this product term + 0x2 + + + PT3_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT2_DC + Product term 2, D input configuration + 8 + 2 + read-write + + + PT2_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT2_DC_1 + Pass the D input in this product term + 0x1 + + + PT2_DC_2 + Complement the D input in this product term + 0x2 + + + PT2_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT2_CC + Product term 2, C input configuration + 10 + 2 + read-write + + + PT2_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT2_CC_1 + Pass the C input in this product term + 0x1 + + + PT2_CC_2 + Complement the C input in this product term + 0x2 + + + PT2_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT2_BC + Product term 2, B input configuration + 12 + 2 + read-write + + + PT2_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT2_BC_1 + Pass the B input in this product term + 0x1 + + + PT2_BC_2 + Complement the B input in this product term + 0x2 + + + PT2_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT2_AC + Product term 2, A input configuration + 14 + 2 + read-write + + + PT2_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT2_AC_1 + Pass the A input in this product term + 0x1 + + + PT2_AC_2 + Complement the A input in this product term + 0x2 + + + PT2_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + + + XBARA + Crossbar Switch + XBARA + XBARA_ + 0x403BC000 + + 0 + 0x88 + registers + + + + SEL0 + Crossbar A Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL1 + Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL1 + Crossbar A Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL3 + Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL2 + Crossbar A Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL5 + Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL3 + Crossbar A Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL7 + Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL4 + Crossbar A Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL9 + Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL5 + Crossbar A Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL11 + Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL6 + Crossbar A Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL13 + Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL7 + Crossbar A Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL15 + Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL8 + Crossbar A Select Register 8 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + SEL16 + Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL17 + Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL9 + Crossbar A Select Register 9 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + SEL18 + Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL19 + Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL10 + Crossbar A Select Register 10 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + SEL20 + Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL21 + Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL11 + Crossbar A Select Register 11 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + SEL22 + Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL23 + Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL12 + Crossbar A Select Register 12 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + SEL24 + Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL25 + Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL13 + Crossbar A Select Register 13 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + SEL26 + Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL27 + Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL14 + Crossbar A Select Register 14 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + SEL28 + Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL29 + Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL15 + Crossbar A Select Register 15 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + SEL30 + Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL31 + Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL16 + Crossbar A Select Register 16 + 0x20 + 16 + read-write + 0 + 0xFFFF + + + SEL32 + Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL33 + Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL17 + Crossbar A Select Register 17 + 0x22 + 16 + read-write + 0 + 0xFFFF + + + SEL34 + Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL35 + Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL18 + Crossbar A Select Register 18 + 0x24 + 16 + read-write + 0 + 0xFFFF + + + SEL36 + Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL37 + Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL19 + Crossbar A Select Register 19 + 0x26 + 16 + read-write + 0 + 0xFFFF + + + SEL38 + Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL39 + Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL20 + Crossbar A Select Register 20 + 0x28 + 16 + read-write + 0 + 0xFFFF + + + SEL40 + Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL41 + Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL21 + Crossbar A Select Register 21 + 0x2A + 16 + read-write + 0 + 0xFFFF + + + SEL42 + Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL43 + Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL22 + Crossbar A Select Register 22 + 0x2C + 16 + read-write + 0 + 0xFFFF + + + SEL44 + Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL45 + Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL23 + Crossbar A Select Register 23 + 0x2E + 16 + read-write + 0 + 0xFFFF + + + SEL46 + Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL47 + Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL24 + Crossbar A Select Register 24 + 0x30 + 16 + read-write + 0 + 0xFFFF + + + SEL48 + Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL49 + Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL25 + Crossbar A Select Register 25 + 0x32 + 16 + read-write + 0 + 0xFFFF + + + SEL50 + Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL51 + Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL26 + Crossbar A Select Register 26 + 0x34 + 16 + read-write + 0 + 0xFFFF + + + SEL52 + Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL53 + Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL27 + Crossbar A Select Register 27 + 0x36 + 16 + read-write + 0 + 0xFFFF + + + SEL54 + Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL55 + Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL28 + Crossbar A Select Register 28 + 0x38 + 16 + read-write + 0 + 0xFFFF + + + SEL56 + Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL57 + Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL29 + Crossbar A Select Register 29 + 0x3A + 16 + read-write + 0 + 0xFFFF + + + SEL58 + Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL59 + Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL30 + Crossbar A Select Register 30 + 0x3C + 16 + read-write + 0 + 0xFFFF + + + SEL60 + Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL61 + Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL31 + Crossbar A Select Register 31 + 0x3E + 16 + read-write + 0 + 0xFFFF + + + SEL62 + Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL63 + Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL32 + Crossbar A Select Register 32 + 0x40 + 16 + read-write + 0 + 0xFFFF + + + SEL64 + Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL65 + Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL33 + Crossbar A Select Register 33 + 0x42 + 16 + read-write + 0 + 0xFFFF + + + SEL66 + Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL67 + Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL34 + Crossbar A Select Register 34 + 0x44 + 16 + read-write + 0 + 0xFFFF + + + SEL68 + Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL69 + Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL35 + Crossbar A Select Register 35 + 0x46 + 16 + read-write + 0 + 0xFFFF + + + SEL70 + Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL71 + Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL36 + Crossbar A Select Register 36 + 0x48 + 16 + read-write + 0 + 0xFFFF + + + SEL72 + Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL73 + Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL37 + Crossbar A Select Register 37 + 0x4A + 16 + read-write + 0 + 0xFFFF + + + SEL74 + Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL75 + Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL38 + Crossbar A Select Register 38 + 0x4C + 16 + read-write + 0 + 0xFFFF + + + SEL76 + Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL77 + Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL39 + Crossbar A Select Register 39 + 0x4E + 16 + read-write + 0 + 0xFFFF + + + SEL78 + Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL79 + Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL40 + Crossbar A Select Register 40 + 0x50 + 16 + read-write + 0 + 0xFFFF + + + SEL80 + Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL81 + Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL41 + Crossbar A Select Register 41 + 0x52 + 16 + read-write + 0 + 0xFFFF + + + SEL82 + Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL83 + Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL42 + Crossbar A Select Register 42 + 0x54 + 16 + read-write + 0 + 0xFFFF + + + SEL84 + Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL85 + Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL43 + Crossbar A Select Register 43 + 0x56 + 16 + read-write + 0 + 0xFFFF + + + SEL86 + Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL87 + Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL44 + Crossbar A Select Register 44 + 0x58 + 16 + read-write + 0 + 0xFFFF + + + SEL88 + Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL89 + Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL45 + Crossbar A Select Register 45 + 0x5A + 16 + read-write + 0 + 0xFFFF + + + SEL90 + Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL91 + Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL46 + Crossbar A Select Register 46 + 0x5C + 16 + read-write + 0 + 0xFFFF + + + SEL92 + Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL93 + Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL47 + Crossbar A Select Register 47 + 0x5E + 16 + read-write + 0 + 0xFFFF + + + SEL94 + Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL95 + Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL48 + Crossbar A Select Register 48 + 0x60 + 16 + read-write + 0 + 0xFFFF + + + SEL96 + Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL97 + Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL49 + Crossbar A Select Register 49 + 0x62 + 16 + read-write + 0 + 0xFFFF + + + SEL98 + Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL99 + Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL50 + Crossbar A Select Register 50 + 0x64 + 16 + read-write + 0 + 0xFFFF + + + SEL100 + Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL101 + Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL51 + Crossbar A Select Register 51 + 0x66 + 16 + read-write + 0 + 0xFFFF + + + SEL102 + Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL103 + Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL52 + Crossbar A Select Register 52 + 0x68 + 16 + read-write + 0 + 0xFFFF + + + SEL104 + Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL105 + Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL53 + Crossbar A Select Register 53 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + SEL106 + Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL107 + Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL54 + Crossbar A Select Register 54 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + SEL108 + Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL109 + Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL55 + Crossbar A Select Register 55 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + SEL110 + Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL111 + Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL56 + Crossbar A Select Register 56 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + SEL112 + Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL113 + Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL57 + Crossbar A Select Register 57 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + SEL114 + Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL115 + Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL58 + Crossbar A Select Register 58 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + SEL116 + Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL117 + Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL59 + Crossbar A Select Register 59 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + SEL118 + Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL119 + Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL60 + Crossbar A Select Register 60 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + SEL120 + Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL121 + Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL61 + Crossbar A Select Register 61 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + SEL122 + Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL123 + Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL62 + Crossbar A Select Register 62 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + SEL124 + Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL125 + Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL63 + Crossbar A Select Register 63 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + SEL126 + Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL127 + Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL64 + Crossbar A Select Register 64 + 0x80 + 16 + read-write + 0 + 0xFFFF + + + SEL128 + Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL129 + Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL65 + Crossbar A Select Register 65 + 0x82 + 16 + read-write + 0 + 0xFFFF + + + SEL130 + Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL131 + Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + CTRL0 + Crossbar A Control Register 0 + 0x84 + 16 + read-write + 0 + 0xFFFF + + + DEN0 + DMA Enable for XBAR_OUT0 + 0 + 1 + read-write + + + DEN0_0 + DMA disabled + 0 + + + DEN0_1 + DMA enabled + 0x1 + + + + + IEN0 + Interrupt Enable for XBAR_OUT0 + 1 + 1 + read-write + + + IEN0_0 + Interrupt disabled + 0 + + + IEN0_1 + Interrupt enabled + 0x1 + + + + + EDGE0 + Active edge for edge detection on XBAR_OUT0 + 2 + 2 + read-write + + + EDGE0_0 + STS0 never asserts + 0 + + + EDGE0_1 + STS0 asserts on rising edges of XBAR_OUT0 + 0x1 + + + EDGE0_2 + STS0 asserts on falling edges of XBAR_OUT0 + 0x2 + + + EDGE0_3 + STS0 asserts on rising and falling edges of XBAR_OUT0 + 0x3 + + + + + STS0 + Edge detection status for XBAR_OUT0 + 4 + 1 + read-write + oneToClear + + + STS0_0 + Active edge not yet detected on XBAR_OUT0 + 0 + + + STS0_1 + Active edge detected on XBAR_OUT0 + 0x1 + + + + + DEN1 + DMA Enable for XBAR_OUT1 + 8 + 1 + read-write + + + DEN1_0 + DMA disabled + 0 + + + DEN1_1 + DMA enabled + 0x1 + + + + + IEN1 + Interrupt Enable for XBAR_OUT1 + 9 + 1 + read-write + + + IEN1_0 + Interrupt disabled + 0 + + + IEN1_1 + Interrupt enabled + 0x1 + + + + + EDGE1 + Active edge for edge detection on XBAR_OUT1 + 10 + 2 + read-write + + + EDGE1_0 + STS1 never asserts + 0 + + + EDGE1_1 + STS1 asserts on rising edges of XBAR_OUT1 + 0x1 + + + EDGE1_2 + STS1 asserts on falling edges of XBAR_OUT1 + 0x2 + + + EDGE1_3 + STS1 asserts on rising and falling edges of XBAR_OUT1 + 0x3 + + + + + STS1 + Edge detection status for XBAR_OUT1 + 12 + 1 + read-write + oneToClear + + + STS1_0 + Active edge not yet detected on XBAR_OUT1 + 0 + + + STS1_1 + Active edge detected on XBAR_OUT1 + 0x1 + + + + + + + CTRL1 + Crossbar A Control Register 1 + 0x86 + 16 + read-write + 0 + 0xFFFF + + + DEN2 + DMA Enable for XBAR_OUT2 + 0 + 1 + read-write + + + DEN2_0 + DMA disabled + 0 + + + DEN2_1 + DMA enabled + 0x1 + + + + + IEN2 + Interrupt Enable for XBAR_OUT2 + 1 + 1 + read-write + + + IEN2_0 + Interrupt disabled + 0 + + + IEN2_1 + Interrupt enabled + 0x1 + + + + + EDGE2 + Active edge for edge detection on XBAR_OUT2 + 2 + 2 + read-write + + + EDGE2_0 + STS2 never asserts + 0 + + + EDGE2_1 + STS2 asserts on rising edges of XBAR_OUT2 + 0x1 + + + EDGE2_2 + STS2 asserts on falling edges of XBAR_OUT2 + 0x2 + + + EDGE2_3 + STS2 asserts on rising and falling edges of XBAR_OUT2 + 0x3 + + + + + STS2 + Edge detection status for XBAR_OUT2 + 4 + 1 + read-write + oneToClear + + + STS2_0 + Active edge not yet detected on XBAR_OUT2 + 0 + + + STS2_1 + Active edge detected on XBAR_OUT2 + 0x1 + + + + + DEN3 + DMA Enable for XBAR_OUT3 + 8 + 1 + read-write + + + DEN3_0 + DMA disabled + 0 + + + DEN3_1 + DMA enabled + 0x1 + + + + + IEN3 + Interrupt Enable for XBAR_OUT3 + 9 + 1 + read-write + + + IEN3_0 + Interrupt disabled + 0 + + + IEN3_1 + Interrupt enabled + 0x1 + + + + + EDGE3 + Active edge for edge detection on XBAR_OUT3 + 10 + 2 + read-write + + + EDGE3_0 + STS3 never asserts + 0 + + + EDGE3_1 + STS3 asserts on rising edges of XBAR_OUT3 + 0x1 + + + EDGE3_2 + STS3 asserts on falling edges of XBAR_OUT3 + 0x2 + + + EDGE3_3 + STS3 asserts on rising and falling edges of XBAR_OUT3 + 0x3 + + + + + STS3 + Edge detection status for XBAR_OUT3 + 12 + 1 + read-write + oneToClear + + + STS3_0 + Active edge not yet detected on XBAR_OUT3 + 0 + + + STS3_1 + Active edge detected on XBAR_OUT3 + 0x1 + + + + + + + + + XBARB + Crossbar Switch + XBARA + XBARB_ + 0x403C0000 + + 0 + 0x10 + registers + + + + SEL0 + Crossbar B Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL1 + Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL1 + Crossbar B Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL3 + Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL2 + Crossbar B Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL5 + Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL3 + Crossbar B Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL7 + Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL4 + Crossbar B Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL9 + Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL5 + Crossbar B Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL11 + Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL6 + Crossbar B Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL13 + Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL7 + Crossbar B Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL15 + Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + + + ENC1 + Quadrature Decoder + ENC + ENC1_ + 0x403C8000 + + 0 + 0x28 + registers + + + ENC1 + 129 + + + + CTRL + Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enable + 0 + 1 + read-write + + + CMPIE_0 + Compare interrupt is disabled + 0 + + + CMPIE_1 + Compare interrupt is enabled + 0x1 + + + + + CMPIRQ + Compare Interrupt Request + 1 + 1 + read-write + oneToClear + + + CMPIRQ_0 + No match has occurred + 0 + + + CMPIRQ_1 + COMP match has occurred + 0x1 + + + + + WDE + Watchdog Enable + 2 + 1 + read-write + + + WDE_0 + Watchdog timer is disabled + 0 + + + WDE_1 + Watchdog timer is enabled + 0x1 + + + + + DIE + Watchdog Timeout Interrupt Enable + 3 + 1 + read-write + + + DIE_0 + Watchdog timer interrupt is disabled + 0 + + + DIE_1 + Watchdog timer interrupt is enabled + 0x1 + + + + + DIRQ + Watchdog Timeout Interrupt Request + 4 + 1 + read-write + oneToClear + + + DIRQ_0 + No interrupt has occurred + 0 + + + DIRQ_1 + Watchdog timeout interrupt has occurred + 0x1 + + + + + XNE + Use Negative Edge of INDEX Pulse + 5 + 1 + read-write + + + XNE_0 + Use positive transition edge of INDEX pulse + 0 + + + XNE_1 + Use negative transition edge of INDEX pulse + 0x1 + + + + + XIP + INDEX Triggered Initialization of Position Counters UPOS and LPOS + 6 + 1 + read-write + + + XIP_0 + No action + 0 + + + XIP_1 + INDEX pulse initializes the position counter + 0x1 + + + + + XIE + INDEX Pulse Interrupt Enable + 7 + 1 + read-write + + + XIE_0 + INDEX pulse interrupt is disabled + 0 + + + XIE_1 + INDEX pulse interrupt is enabled + 0x1 + + + + + XIRQ + INDEX Pulse Interrupt Request + 8 + 1 + read-write + oneToClear + + + XIRQ_0 + No interrupt has occurred + 0 + + + XIRQ_1 + INDEX pulse interrupt has occurred + 0x1 + + + + + PH1 + Enable Signal Phase Count Mode + 9 + 1 + read-write + + + PH1_0 + Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + 0 + + + PH1_1 + Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + 0x1 + + + + + REV + Enable Reverse Direction Counting + 10 + 1 + read-write + + + REV_0 + Count normally + 0 + + + REV_1 + Count in the reverse direction + 0x1 + + + + + SWIP + Software Triggered Initialization of Position Counters UPOS and LPOS + 11 + 1 + read-write + + + SWIP_0 + No action + 0 + + + SWIP_1 + Initialize position counter + 0x1 + + + + + HNE + Use Negative Edge of HOME Input + 12 + 1 + read-write + + + HNE_0 + Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + 0 + + + HNE_1 + Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + 0x1 + + + + + HIP + Enable HOME to Initialize Position Counters UPOS and LPOS + 13 + 1 + read-write + + + HIP_0 + No action + 0 + + + HIP_1 + HOME signal initializes the position counter + 0x1 + + + + + HIE + HOME Interrupt Enable + 14 + 1 + read-write + + + HIE_0 + Disable HOME interrupts + 0 + + + HIE_1 + Enable HOME interrupts + 0x1 + + + + + HIRQ + HOME Signal Transition Interrupt Request + 15 + 1 + read-write + oneToClear + + + HIRQ_0 + No interrupt + 0 + + + HIRQ_1 + HOME signal transition interrupt request + 0x1 + + + + + + + FILT + Input Filter Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + WTR + Watchdog Timeout Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + WDOG + WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt + 0 + 16 + read-write + + + + + POSD + Position Difference Counter Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + POSD + This read/write register contains the position change in value occurring between each read of the position register + 0 + 16 + read-write + + + + + POSDH + Position Difference Hold Register + 0x8 + 16 + read-only + 0 + 0xFFFF + + + POSDH + This read-only register contains a snapshot of the value of the POSD register + 0 + 16 + read-only + + + + + REV + Revolution Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + REV + This read/write register contains the current value of the revolution counter. + 0 + 16 + read-write + + + + + REVH + Revolution Hold Register + 0xC + 16 + read-only + 0 + 0xFFFF + + + REVH + This read-only register contains a snapshot of the value of the REV register. + 0 + 16 + read-only + + + + + UPOS + Upper Position Counter Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the upper (most significant) half of the position counter + 0 + 16 + read-write + + + + + LPOS + Lower Position Counter Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the lower (least significant) half of the position counter + 0 + 16 + read-write + + + + + UPOSH + Upper Position Hold Register + 0x12 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the UPOS register. + 0 + 16 + read-only + + + + + LPOSH + Lower Position Hold Register + 0x14 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the LPOS register. + 0 + 16 + read-only + + + + + UINIT + Upper Initialization Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS) + 0 + 16 + read-write + + + + + LINIT + Lower Initialization Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS) + 0 + 16 + read-write + + + + + IMR + Input Monitor Register + 0x1A + 16 + read-only + 0 + 0xFFFF + + + HOME + This is the raw HOME input. + 0 + 1 + read-only + + + INDEX + This is the raw INDEX input. + 1 + 1 + read-only + + + PHB + This is the raw PHASEB input. + 2 + 1 + read-only + + + PHA + This is the raw PHASEA input. + 3 + 1 + read-only + + + FHOM + This is the filtered version of HOME input. + 4 + 1 + read-only + + + FIND + This is the filtered version of INDEX input. + 5 + 1 + read-only + + + FPHB + This is the filtered version of PHASEB input. + 6 + 1 + read-only + + + FPHA + This is the filtered version of PHASEA input. + 7 + 1 + read-only + + + + + TST + Test Register + 0x1C + 16 + read-write + 0 + 0xFFFF + + + TEST_COUNT + These bits hold the number of quadrature advances to generate. + 0 + 8 + read-write + + + TEST_PERIOD + These bits hold the period of quadrature phase in IPBus clock cycles. + 8 + 5 + read-write + + + QDN + Quadrature Decoder Negative Signal + 13 + 1 + read-write + + + QDN_0 + Leaves quadrature decoder signal in a positive direction + 0 + + + QDN_1 + Generates a negative quadrature decoder signal + 0x1 + + + + + TCE + Test Counter Enable + 14 + 1 + read-write + + + TCE_0 + Test count is not enabled + 0 + + + TCE_1 + Test count is enabled + 0x1 + + + + + TEN + Test Mode Enable + 15 + 1 + read-write + + + TEN_0 + Test module is not enabled + 0 + + + TEN_1 + Test module is enabled + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x1E + 16 + read-write + 0 + 0xFFFF + + + UPDHLD + Update Hold Registers + 0 + 1 + read-write + + + UPDHLD_0 + Disable updates of hold registers on rising edge of TRIGGER + 0 + + + UPDHLD_1 + Enable updates of hold registers on rising edge of TRIGGER + 0x1 + + + + + UPDPOS + Update Position Registers + 1 + 1 + read-write + + + UPDPOS_0 + No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0 + + + UPDPOS_1 + Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0x1 + + + + + MOD + Enable Modulo Counting + 2 + 1 + read-write + + + MOD_0 + Disable modulo counting + 0 + + + MOD_1 + Enable modulo counting + 0x1 + + + + + DIR + Count Direction Flag + 3 + 1 + read-only + + + DIR_0 + Last count was in the down direction + 0 + + + DIR_1 + Last count was in the up direction + 0x1 + + + + + RUIE + Roll-under Interrupt Enable + 4 + 1 + read-write + + + RUIE_0 + Roll-under interrupt is disabled + 0 + + + RUIE_1 + Roll-under interrupt is enabled + 0x1 + + + + + RUIRQ + Roll-under Interrupt Request + 5 + 1 + read-write + oneToClear + + + RUIRQ_0 + No roll-under has occurred + 0 + + + RUIRQ_1 + Roll-under has occurred + 0x1 + + + + + ROIE + Roll-over Interrupt Enable + 6 + 1 + read-write + + + ROIE_0 + Roll-over interrupt is disabled + 0 + + + ROIE_1 + Roll-over interrupt is enabled + 0x1 + + + + + ROIRQ + Roll-over Interrupt Request + 7 + 1 + read-write + oneToClear + + + ROIRQ_0 + No roll-over has occurred + 0 + + + ROIRQ_1 + Roll-over has occurred + 0x1 + + + + + REVMOD + Revolution Counter Modulus Enable + 8 + 1 + read-write + + + REVMOD_0 + Use INDEX pulse to increment/decrement revolution counter (REV). + 0 + + + REVMOD_1 + Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + 0x1 + + + + + OUTCTL + Output Control + 9 + 1 + read-write + + + OUTCTL_0 + POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + 0 + + + OUTCTL_1 + POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + 0x1 + + + + + SABIE + Simultaneous PHASEA and PHASEB Change Interrupt Enable + 10 + 1 + read-write + + + SABIE_0 + Simultaneous PHASEA and PHASEB change interrupt disabled. + 0 + + + SABIE_1 + Simultaneous PHASEA and PHASEB change interrupt enabled. + 0x1 + + + + + SABIRQ + Simultaneous PHASEA and PHASEB Change Interrupt Request + 11 + 1 + read-write + oneToClear + + + SABIRQ_0 + No simultaneous change of PHASEA and PHASEB has occurred. + 0 + + + SABIRQ_1 + A simultaneous change of PHASEA and PHASEB has occurred. + 0x1 + + + + + + + UMOD + Upper Modulus Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the upper (most significant) half of the modulus register + 0 + 16 + read-write + + + + + LMOD + Lower Modulus Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the lower (least significant) half of the modulus register + 0 + 16 + read-write + + + + + UCOMP + Upper Position Compare Register + 0x24 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the upper (most significant) half of the position compare register + 0 + 16 + read-write + + + + + LCOMP + Lower Position Compare Register + 0x26 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the lower (least significant) half of the position compare register + 0 + 16 + read-write + + + + + + + PWM1 + PWM + PWM + 0x403DC000 + + 0 + 0x196 + registers + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + + SM0CNT + Counter Register + 0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM0INIT + Initial Count Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM0CTRL2 + Control 2 Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM0CTRL + Control Register + 0x6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM0VAL0 + Value Register 0 + 0xA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM0FRACVAL1 + Fractional Value Register 1 + 0xC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM0VAL1 + Value Register 1 + 0xE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM0FRACVAL2 + Fractional Value Register 2 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM0VAL2 + Value Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM0FRACVAL3 + Fractional Value Register 3 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM0VAL3 + Value Register 3 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM0FRACVAL4 + Fractional Value Register 4 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM0VAL4 + Value Register 4 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM0FRACVAL5 + Fractional Value Register 5 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM0VAL5 + Value Register 5 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM0FRCTRL + Fractional Control Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM0OCTRL + Output Control Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM0STS + Status Register + 0x24 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM0INTEN + Interrupt Enable Register + 0x26 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM0DMAEN + DMA Enable Register + 0x28 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM0TCTRL + Output Trigger Control Register + 0x2A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM0DISMAP0 + Fault Disable Mapping Register 0 + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM0DISMAP1 + Fault Disable Mapping Register 1 + 0x2E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM0DTCNT0 + Deadtime Count Register 0 + 0x30 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM0DTCNT1 + Deadtime Count Register 1 + 0x32 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM0CAPTCTRLA + Capture Control A Register + 0x34 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPA + Capture Compare A Register + 0x36 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM0CAPTCTRLB + Capture Control B Register + 0x38 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPB + Capture Compare B Register + 0x3A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM0CAPTCTRLX + Capture Control X Register + 0x3C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPX + Capture Compare X Register + 0x3E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM0CVAL0 + Capture Value 0 Register + 0x40 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM0CVAL0CYC + Capture Value 0 Cycle Register + 0x42 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM0CVAL1 + Capture Value 1 Register + 0x44 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM0CVAL1CYC + Capture Value 1 Cycle Register + 0x46 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM0CVAL2 + Capture Value 2 Register + 0x48 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM0CVAL2CYC + Capture Value 2 Cycle Register + 0x4A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM0CVAL3 + Capture Value 3 Register + 0x4C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM0CVAL3CYC + Capture Value 3 Cycle Register + 0x4E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM0CVAL4 + Capture Value 4 Register + 0x50 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM0CVAL4CYC + Capture Value 4 Cycle Register + 0x52 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM0CVAL5 + Capture Value 5 Register + 0x54 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM0CVAL5CYC + Capture Value 5 Cycle Register + 0x56 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM1CNT + Counter Register + 0x60 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM1INIT + Initial Count Register + 0x62 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM1CTRL2 + Control 2 Register + 0x64 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM1CTRL + Control Register + 0x66 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM1VAL0 + Value Register 0 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM1FRACVAL1 + Fractional Value Register 1 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM1VAL1 + Value Register 1 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM1FRACVAL2 + Fractional Value Register 2 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM1VAL2 + Value Register 2 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM1FRACVAL3 + Fractional Value Register 3 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM1VAL3 + Value Register 3 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM1FRACVAL4 + Fractional Value Register 4 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM1VAL4 + Value Register 4 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM1FRACVAL5 + Fractional Value Register 5 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM1VAL5 + Value Register 5 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM1FRCTRL + Fractional Control Register + 0x80 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM1OCTRL + Output Control Register + 0x82 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM1STS + Status Register + 0x84 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM1INTEN + Interrupt Enable Register + 0x86 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM1DMAEN + DMA Enable Register + 0x88 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM1TCTRL + Output Trigger Control Register + 0x8A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM1DISMAP0 + Fault Disable Mapping Register 0 + 0x8C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM1DISMAP1 + Fault Disable Mapping Register 1 + 0x8E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM1DTCNT0 + Deadtime Count Register 0 + 0x90 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM1DTCNT1 + Deadtime Count Register 1 + 0x92 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM1CAPTCTRLA + Capture Control A Register + 0x94 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPA + Capture Compare A Register + 0x96 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM1CAPTCTRLB + Capture Control B Register + 0x98 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPB + Capture Compare B Register + 0x9A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM1CAPTCTRLX + Capture Control X Register + 0x9C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPX + Capture Compare X Register + 0x9E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM1CVAL0 + Capture Value 0 Register + 0xA0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM1CVAL0CYC + Capture Value 0 Cycle Register + 0xA2 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM1CVAL1 + Capture Value 1 Register + 0xA4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM1CVAL1CYC + Capture Value 1 Cycle Register + 0xA6 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM1CVAL2 + Capture Value 2 Register + 0xA8 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM1CVAL2CYC + Capture Value 2 Cycle Register + 0xAA + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM1CVAL3 + Capture Value 3 Register + 0xAC + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM1CVAL3CYC + Capture Value 3 Cycle Register + 0xAE + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM1CVAL4 + Capture Value 4 Register + 0xB0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM1CVAL4CYC + Capture Value 4 Cycle Register + 0xB2 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM1CVAL5 + Capture Value 5 Register + 0xB4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM1CVAL5CYC + Capture Value 5 Cycle Register + 0xB6 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM2CNT + Counter Register + 0xC0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM2INIT + Initial Count Register + 0xC2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM2CTRL2 + Control 2 Register + 0xC4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM2CTRL + Control Register + 0xC6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM2VAL0 + Value Register 0 + 0xCA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM2FRACVAL1 + Fractional Value Register 1 + 0xCC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM2VAL1 + Value Register 1 + 0xCE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM2FRACVAL2 + Fractional Value Register 2 + 0xD0 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM2VAL2 + Value Register 2 + 0xD2 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM2FRACVAL3 + Fractional Value Register 3 + 0xD4 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM2VAL3 + Value Register 3 + 0xD6 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM2FRACVAL4 + Fractional Value Register 4 + 0xD8 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM2VAL4 + Value Register 4 + 0xDA + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM2FRACVAL5 + Fractional Value Register 5 + 0xDC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM2VAL5 + Value Register 5 + 0xDE + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM2FRCTRL + Fractional Control Register + 0xE0 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM2OCTRL + Output Control Register + 0xE2 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM2STS + Status Register + 0xE4 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM2INTEN + Interrupt Enable Register + 0xE6 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM2DMAEN + DMA Enable Register + 0xE8 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM2TCTRL + Output Trigger Control Register + 0xEA + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM2DISMAP0 + Fault Disable Mapping Register 0 + 0xEC + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM2DISMAP1 + Fault Disable Mapping Register 1 + 0xEE + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM2DTCNT0 + Deadtime Count Register 0 + 0xF0 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM2DTCNT1 + Deadtime Count Register 1 + 0xF2 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM2CAPTCTRLA + Capture Control A Register + 0xF4 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPA + Capture Compare A Register + 0xF6 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM2CAPTCTRLB + Capture Control B Register + 0xF8 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPB + Capture Compare B Register + 0xFA + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM2CAPTCTRLX + Capture Control X Register + 0xFC + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPX + Capture Compare X Register + 0xFE + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM2CVAL0 + Capture Value 0 Register + 0x100 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM2CVAL0CYC + Capture Value 0 Cycle Register + 0x102 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM2CVAL1 + Capture Value 1 Register + 0x104 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM2CVAL1CYC + Capture Value 1 Cycle Register + 0x106 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM2CVAL2 + Capture Value 2 Register + 0x108 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM2CVAL2CYC + Capture Value 2 Cycle Register + 0x10A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM2CVAL3 + Capture Value 3 Register + 0x10C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM2CVAL3CYC + Capture Value 3 Cycle Register + 0x10E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM2CVAL4 + Capture Value 4 Register + 0x110 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM2CVAL4CYC + Capture Value 4 Cycle Register + 0x112 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM2CVAL5 + Capture Value 5 Register + 0x114 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM2CVAL5CYC + Capture Value 5 Cycle Register + 0x116 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM3CNT + Counter Register + 0x120 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM3INIT + Initial Count Register + 0x122 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM3CTRL2 + Control 2 Register + 0x124 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM3CTRL + Control Register + 0x126 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM3VAL0 + Value Register 0 + 0x12A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM3FRACVAL1 + Fractional Value Register 1 + 0x12C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM3VAL1 + Value Register 1 + 0x12E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM3FRACVAL2 + Fractional Value Register 2 + 0x130 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM3VAL2 + Value Register 2 + 0x132 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM3FRACVAL3 + Fractional Value Register 3 + 0x134 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM3VAL3 + Value Register 3 + 0x136 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM3FRACVAL4 + Fractional Value Register 4 + 0x138 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM3VAL4 + Value Register 4 + 0x13A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM3FRACVAL5 + Fractional Value Register 5 + 0x13C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM3VAL5 + Value Register 5 + 0x13E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM3FRCTRL + Fractional Control Register + 0x140 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM3OCTRL + Output Control Register + 0x142 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM3STS + Status Register + 0x144 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM3INTEN + Interrupt Enable Register + 0x146 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM3DMAEN + DMA Enable Register + 0x148 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM3TCTRL + Output Trigger Control Register + 0x14A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM3DISMAP0 + Fault Disable Mapping Register 0 + 0x14C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM3DISMAP1 + Fault Disable Mapping Register 1 + 0x14E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM3DTCNT0 + Deadtime Count Register 0 + 0x150 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM3DTCNT1 + Deadtime Count Register 1 + 0x152 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM3CAPTCTRLA + Capture Control A Register + 0x154 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPA + Capture Compare A Register + 0x156 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM3CAPTCTRLB + Capture Control B Register + 0x158 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPB + Capture Compare B Register + 0x15A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM3CAPTCTRLX + Capture Control X Register + 0x15C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPX + Capture Compare X Register + 0x15E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM3CVAL0 + Capture Value 0 Register + 0x160 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM3CVAL0CYC + Capture Value 0 Cycle Register + 0x162 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM3CVAL1 + Capture Value 1 Register + 0x164 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM3CVAL1CYC + Capture Value 1 Cycle Register + 0x166 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM3CVAL2 + Capture Value 2 Register + 0x168 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM3CVAL2CYC + Capture Value 2 Cycle Register + 0x16A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM3CVAL3 + Capture Value 3 Register + 0x16C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM3CVAL3CYC + Capture Value 3 Cycle Register + 0x16E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM3CVAL4 + Capture Value 4 Register + 0x170 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM3CVAL4CYC + Capture Value 4 Cycle Register + 0x172 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM3CVAL5 + Capture Value 5 Register + 0x174 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM3CVAL5CYC + Capture Value 5 Cycle Register + 0x176 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + OUTEN + Output Enable Register + 0x180 + 16 + read-write + 0 + 0xFFFF + + + PWMX_EN + PWM_X Output Enables + 0 + 4 + read-write + + + PWMX_EN_0 + PWM_X output disabled. + 0 + + + PWMX_EN_1 + PWM_X output enabled. + 0x1 + + + + + PWMB_EN + PWM_B Output Enables + 4 + 4 + read-write + + + PWMB_EN_0 + PWM_B output disabled. + 0 + + + PWMB_EN_1 + PWM_B output enabled. + 0x1 + + + + + PWMA_EN + PWM_A Output Enables + 8 + 4 + read-write + + + PWMA_EN_0 + PWM_A output disabled. + 0 + + + PWMA_EN_1 + PWM_A output enabled. + 0x1 + + + + + + + MASK + Mask Register + 0x182 + 16 + read-write + 0 + 0xFFFF + + + MASKX + PWM_X Masks + 0 + 4 + read-write + + + MASKX_0 + PWM_X output normal. + 0 + + + MASKX_1 + PWM_X output masked. + 0x1 + + + + + MASKB + PWM_B Masks + 4 + 4 + read-write + + + MASKB_0 + PWM_B output normal. + 0 + + + MASKB_1 + PWM_B output masked. + 0x1 + + + + + MASKA + PWM_A Masks + 8 + 4 + read-write + + + MASKA_0 + PWM_A output normal. + 0 + + + MASKA_1 + PWM_A output masked. + 0x1 + + + + + UPDATE_MASK + Update Mask Bits Immediately + 12 + 4 + write-only + + + UPDATE_MASK_0 + Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + 0 + + + UPDATE_MASK_1 + Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + 0x1 + + + + + + + SWCOUT + Software Controlled Output Register + 0x184 + 16 + read-write + 0 + 0xFFFF + + + SM0OUT45 + Submodule 0 Software Controlled Output 45 + 0 + 1 + read-write + + + SM0OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0 + + + SM0OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0x1 + + + + + SM0OUT23 + Submodule 0 Software Controlled Output 23 + 1 + 1 + read-write + + + SM0OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0 + + + SM0OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0x1 + + + + + SM1OUT45 + Submodule 1 Software Controlled Output 45 + 2 + 1 + read-write + + + SM1OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0 + + + SM1OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0x1 + + + + + SM1OUT23 + Submodule 1 Software Controlled Output 23 + 3 + 1 + read-write + + + SM1OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0 + + + SM1OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0x1 + + + + + SM2OUT45 + Submodule 2 Software Controlled Output 45 + 4 + 1 + read-write + + + SM2OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0 + + + SM2OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0x1 + + + + + SM2OUT23 + Submodule 2 Software Controlled Output 23 + 5 + 1 + read-write + + + SM2OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0 + + + SM2OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0x1 + + + + + SM3OUT45 + Submodule 3 Software Controlled Output 45 + 6 + 1 + read-write + + + SM3OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0 + + + SM3OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0x1 + + + + + SM3OUT23 + Submodule 3 Software Controlled Output 23 + 7 + 1 + read-write + + + SM3OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0 + + + SM3OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0x1 + + + + + + + DTSRCSEL + PWM Source Select Register + 0x186 + 16 + read-write + 0 + 0xFFFF + + + SM0SEL45 + Submodule 0 PWM45 Control Select + 0 + 2 + read-write + + + SM0SEL45_0 + Generated SM0PWM45 signal is used by the deadtime logic. + 0 + + + SM0SEL45_1 + Inverted generated SM0PWM45 signal is used by the deadtime logic. + 0x1 + + + SM0SEL45_2 + SWCOUT[SM0OUT45] is used by the deadtime logic. + 0x2 + + + SM0SEL45_3 + PWM0_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM0SEL23 + Submodule 0 PWM23 Control Select + 2 + 2 + read-write + + + SM0SEL23_0 + Generated SM0PWM23 signal is used by the deadtime logic. + 0 + + + SM0SEL23_1 + Inverted generated SM0PWM23 signal is used by the deadtime logic. + 0x1 + + + SM0SEL23_2 + SWCOUT[SM0OUT23] is used by the deadtime logic. + 0x2 + + + SM0SEL23_3 + PWM0_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL45 + Submodule 1 PWM45 Control Select + 4 + 2 + read-write + + + SM1SEL45_0 + Generated SM1PWM45 signal is used by the deadtime logic. + 0 + + + SM1SEL45_1 + Inverted generated SM1PWM45 signal is used by the deadtime logic. + 0x1 + + + SM1SEL45_2 + SWCOUT[SM1OUT45] is used by the deadtime logic. + 0x2 + + + SM1SEL45_3 + PWM1_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL23 + Submodule 1 PWM23 Control Select + 6 + 2 + read-write + + + SM1SEL23_0 + Generated SM1PWM23 signal is used by the deadtime logic. + 0 + + + SM1SEL23_1 + Inverted generated SM1PWM23 signal is used by the deadtime logic. + 0x1 + + + SM1SEL23_2 + SWCOUT[SM1OUT23] is used by the deadtime logic. + 0x2 + + + SM1SEL23_3 + PWM1_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL45 + Submodule 2 PWM45 Control Select + 8 + 2 + read-write + + + SM2SEL45_0 + Generated SM2PWM45 signal is used by the deadtime logic. + 0 + + + SM2SEL45_1 + Inverted generated SM2PWM45 signal is used by the deadtime logic. + 0x1 + + + SM2SEL45_2 + SWCOUT[SM2OUT45] is used by the deadtime logic. + 0x2 + + + SM2SEL45_3 + PWM2_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL23 + Submodule 2 PWM23 Control Select + 10 + 2 + read-write + + + SM2SEL23_0 + Generated SM2PWM23 signal is used by the deadtime logic. + 0 + + + SM2SEL23_1 + Inverted generated SM2PWM23 signal is used by the deadtime logic. + 0x1 + + + SM2SEL23_2 + SWCOUT[SM2OUT23] is used by the deadtime logic. + 0x2 + + + SM2SEL23_3 + PWM2_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL45 + Submodule 3 PWM45 Control Select + 12 + 2 + read-write + + + SM3SEL45_0 + Generated SM3PWM45 signal is used by the deadtime logic. + 0 + + + SM3SEL45_1 + Inverted generated SM3PWM45 signal is used by the deadtime logic. + 0x1 + + + SM3SEL45_2 + SWCOUT[SM3OUT45] is used by the deadtime logic. + 0x2 + + + SM3SEL45_3 + PWM3_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL23 + Submodule 3 PWM23 Control Select + 14 + 2 + read-write + + + SM3SEL23_0 + Generated SM3PWM23 signal is used by the deadtime logic. + 0 + + + SM3SEL23_1 + Inverted generated SM3PWM23 signal is used by the deadtime logic. + 0x1 + + + SM3SEL23_2 + SWCOUT[SM3OUT23] is used by the deadtime logic. + 0x2 + + + SM3SEL23_3 + PWM3_EXTA signal is used by the deadtime logic. + 0x3 + + + + + + + MCTRL + Master Control Register + 0x188 + 16 + read-write + 0 + 0xFFFF + + + LDOK + Load Okay + 0 + 4 + read-write + + + LDOK_0 + Do not load new values. + 0 + + + LDOK_1 + Load prescaler, modulus, and PWM values of the corresponding submodule. + 0x1 + + + + + CLDOK + Clear Load Okay + 4 + 4 + read-write + + + RUN + Run + 8 + 4 + read-write + + + RUN_0 + PWM generator is disabled in the corresponding submodule. + 0 + + + RUN_1 + PWM generator is enabled in the corresponding submodule. + 0x1 + + + + + IPOL + Current Polarity + 12 + 4 + read-write + + + IPOL_0 + PWM23 is used to generate complementary PWM pair in the corresponding submodule. + 0 + + + IPOL_1 + PWM45 is used to generate complementary PWM pair in the corresponding submodule. + 0x1 + + + + + + + MCTRL2 + Master Control 2 Register + 0x18A + 16 + read-write + 0 + 0xFFFF + + + MONPLL + Monitor PLL State + 0 + 2 + read-write + + + MONPLL_0 + Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + 0 + + + MONPLL_1 + Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + 0x1 + + + MONPLL_2 + Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + 0x2 + + + MONPLL_3 + Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + 0x3 + + + + + + + FCTRL0 + Fault Control Register + 0x18C + 16 + read-write + 0 + 0xFFFF + + + FIE + Fault Interrupt Enables + 0 + 4 + read-write + + + FIE_0 + FAULTx CPU interrupt requests disabled. + 0 + + + FIE_1 + FAULTx CPU interrupt requests enabled. + 0x1 + + + + + FSAFE + Fault Safety Mode + 4 + 4 + read-write + + + FSAFE_0 + Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + 0 + + + FSAFE_1 + Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + 0x1 + + + + + FAUTO + Automatic Fault Clearing + 8 + 4 + read-write + + + FAUTO_0 + Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + 0 + + + FAUTO_1 + Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + 0x1 + + + + + FLVL + Fault Level + 12 + 4 + read-write + + + FLVL_0 + A logic 0 on the fault input indicates a fault condition. + 0 + + + FLVL_1 + A logic 1 on the fault input indicates a fault condition. + 0x1 + + + + + + + FSTS0 + Fault Status Register + 0x18E + 16 + read-write + 0 + 0xFFFF + + + FFLAG + Fault Flags + 0 + 4 + read-write + + + FFLAG_0 + No fault on the FAULTx pin. + 0 + + + FFLAG_1 + Fault on the FAULTx pin. + 0x1 + + + + + FFULL + Full Cycle + 4 + 4 + read-write + + + FFULL_0 + PWM outputs are not re-enabled at the start of a full cycle + 0 + + + FFULL_1 + PWM outputs are re-enabled at the start of a full cycle + 0x1 + + + + + FFPIN + Filtered Fault Pins + 8 + 4 + read-only + + + FHALF + Half Cycle Fault Recovery + 12 + 4 + read-write + + + FHALF_0 + PWM outputs are not re-enabled at the start of a half cycle. + 0 + + + FHALF_1 + PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + 0x1 + + + + + + + FFILT0 + Fault Filter Register + 0x190 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Fault Filter Period + 0 + 8 + read-write + + + FILT_CNT + Fault Filter Count + 8 + 3 + read-write + + + GSTR + Fault Glitch Stretch Enable + 15 + 1 + read-write + + + GSTR_0 + Fault input glitch stretching is disabled. + 0 + + + GSTR_1 + Input fault signals will be stretched to at least 2 IPBus clock cycles. + 0x1 + + + + + + + FTST0 + Fault Test Register + 0x192 + 16 + read-write + 0 + 0xFFFF + + + FTEST + Fault Test + 0 + 1 + read-write + + + FTEST_0 + No fault + 0 + + + FTEST_1 + Cause a simulated fault + 0x1 + + + + + + + FCTRL20 + Fault Control 2 Register + 0x194 + 16 + read-write + 0 + 0xFFFF + + + NOCOMB + No Combinational Path From Fault Input To PWM Output + 0 + 4 + read-write + + + NOCOMB_0 + There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + 0 + + + NOCOMB_1 + The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + 0x1 + + + + + + + + + BEE + Bus Encryption Engine + BEE + BEE_ + 0x403EC000 + + 0 + 0x48 + registers + + + BEE + 55 + + + + CTRL + BEE Control Register + 0 + 32 + read-write + 0x7700 + 0xFFFFFFFF + + + BEE_ENABLE + BEE enable bit + 0 + 1 + read-write + + + BEE_ENABLE_0 + Disable BEE + 0 + + + BEE_ENABLE_1 + Enable BEE + 0x1 + + + + + CTRL_CLK_EN + Clock enable input, low inactive + 1 + 1 + read-write + + + CTRL_SFTRST_N + Soft reset input, low active + 2 + 1 + read-write + + + KEY_VALID + AES-128 key is ready + 4 + 1 + read-write + + + KEY_REGION_SEL + AES key region select + 5 + 1 + read-write + + + KEY_REGION_SEL_0 + Load AES key for region0 + 0 + + + KEY_REGION_SEL_1 + Load AES key for region1 + 0x1 + + + + + AC_PROT_EN + Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only + 6 + 1 + read-write + + + LITTLE_ENDIAN + Endian swap control for the 16 bytes input and output data of AES core. + 7 + 1 + read-write + + + LITTLE_ENDIAN_0 + The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + 0 + + + LITTLE_ENDIAN_1 + The input and output data of AES core is not swapped. + 0x1 + + + + + SECURITY_LEVEL_R0 + Security level of the allowed access for memory region0 + 8 + 2 + read-write + + + CTRL_AES_MODE_R0 + AES mode of region0 + 10 + 1 + read-write + + + CTRL_AES_MODE_R0_0 + ECB + 0 + + + CTRL_AES_MODE_R0_1 + CTR + 0x1 + + + + + SECURITY_LEVEL_R1 + Security level of the allowed access for memory region1 + 12 + 2 + read-write + + + CTRL_AES_MODE_R1 + AES mode of region1 + 14 + 1 + read-write + + + CTRL_AES_MODE_R1_0 + ECB + 0 + + + CTRL_AES_MODE_R1_1 + CTR + 0x1 + + + + + BEE_ENABLE_LOCK + Lock bit for bee_enable + 16 + 1 + read-write + + + CTRL_CLK_EN_LOCK + Lock bit for ctrl_clk_en + 17 + 1 + read-write + + + CTRL_SFTRST_N_LOCK + Lock bit for ctrl_sftrst + 18 + 1 + read-write + + + REGION1_ADDR_LOCK + Lock bit for region1 address boundary + 19 + 1 + read-write + + + KEY_VALID_LOCK + Lock bit for key_valid + 20 + 1 + read-write + + + KEY_REGION_SEL_LOCK + Lock bit for key_region_sel + 21 + 1 + read-write + + + AC_PROT_EN_LOCK + Lock bit for ac_prot + 22 + 1 + read-write + + + LITTLE_ENDIAN_LOCK + Lock bit for little_endian + 23 + 1 + read-write + + + SECURITY_LEVEL_R0_LOCK + Lock bits for security_level_r0 + 24 + 2 + read-write + + + CTRL_AES_MODE_R0_LOCK + Lock bit for region0 ctrl_aes_mode + 26 + 1 + read-write + + + REGION0_KEY_LOCK + Lock bit for region0 AES key + 27 + 1 + read-write + + + SECURITY_LEVEL_R1_LOCK + Lock bits for security_level_r1 + 28 + 2 + read-write + + + CTRL_AES_MODE_R1_LOCK + Lock bit for region1 ctrl_aes_mode + 30 + 1 + read-write + + + REGION1_KEY_LOCK + Lock bit for region1 AES key + 31 + 1 + read-write + + + + + ADDR_OFFSET0 + no description available + 0x4 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET0 + Signed offset for BEE region 0 + 0 + 16 + read-write + + + ADDR_OFFSET0_LOCK + Lock bits for addr_offset0 + 16 + 16 + read-write + + + + + ADDR_OFFSET1 + no description available + 0x8 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET1 + Signed offset for BEE region 1 + 0 + 16 + read-write + + + ADDR_OFFSET1_LOCK + Lock bits for addr_offset1 + 16 + 16 + read-write + + + + + AES_KEY0_W0 + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY0 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W1 + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY1 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W2 + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY2 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W3 + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY3 + AES 128 key from software + 0 + 32 + read-write + + + + + STATUS + no description available + 0x1C + 32 + read-write + 0 + 0 + + + IRQ_VEC + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort + 0 + 8 + read-write + oneToClear + + + BEE_IDLE + 1'b1: BEE is idle; 1'b0: BEE is active + 8 + 1 + read-only + + + + + CTR_NONCE0_W0 + no description available + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE00 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W1 + no description available + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE01 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W2 + no description available + 0x28 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE02 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W3 + no description available + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE03 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE1_W0 + no description available + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE10 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W1 + no description available + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE11 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W2 + no description available + 0x38 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE12 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W3 + no description available + 0x3C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE13 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + REGION1_TOP + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_TOP + Address upper limit of region1 + 0 + 32 + read-write + + + + + REGION1_BOT + no description available + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_BOT + Address lower limit of region1 + 0 + 32 + read-write + + + + + + + LPI2C1 + LPI2C + LPI2C + LPI2C + 0x403F0000 + + 0 + 0x174 + registers + + + LPI2C1 + 28 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1000003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_2 + Master only, with standard feature set + 0x2 + + + FEATURE_3 + Master and slave, with standard feature set + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + MTXFIFO + Master Transmit FIFO Size + 0 + 4 + read-only + + + MRXFIFO + Master Receive FIFO Size + 8 + 4 + read-only + + + + + MCR + Master Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Master Enable + 0 + 1 + read-write + + + MEN_0 + Master logic is disabled + 0 + + + MEN_1 + Master logic is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Master logic is not reset + 0 + + + RST_1 + Master logic is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Master is enabled in Doze mode + 0 + + + DOZEN_1 + Master is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Master is disabled in debug mode + 0 + + + DBGEN_1 + Master is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + MSR + Master Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data is not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + EPF + End Packet Flag + 8 + 1 + read-write + oneToClear + + + EPF_0 + Master has not generated a STOP or Repeated START condition + 0 + + + EPF_1 + Master has generated a STOP or Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Master has not generated a STOP condition + 0 + + + SDF_1 + Master has generated a STOP condition + 0x1 + + + + + NDF + NACK Detect Flag + 10 + 1 + read-write + oneToClear + + + NDF_0 + Unexpected NACK was not detected + 0 + + + NDF_1 + Unexpected NACK was detected + 0x1 + + + + + ALF + Arbitration Lost Flag + 11 + 1 + read-write + oneToClear + + + ALF_0 + Master has not lost arbitration + 0 + + + ALF_1 + Master has lost arbitration + 0x1 + + + + + FEF + FIFO Error Flag + 12 + 1 + read-write + oneToClear + + + FEF_0 + No error + 0 + + + FEF_1 + Master sending or receiving data without a START condition + 0x1 + + + + + PLTF + Pin Low Timeout Flag + 13 + 1 + read-write + oneToClear + + + PLTF_0 + Pin low timeout has not occurred or is disabled + 0 + + + PLTF_1 + Pin low timeout has occurred + 0x1 + + + + + DMF + Data Match Flag + 14 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Master Busy Flag + 24 + 1 + read-only + + + MBF_0 + I2C Master is idle + 0 + + + MBF_1 + I2C Master is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + MIER + Master Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + EPIE + End Packet Interrupt Enable + 8 + 1 + read-write + + + EPIE_0 + Disabled + 0 + + + EPIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + NDIE + NACK Detect Interrupt Enable + 10 + 1 + read-write + + + NDIE_0 + Disabled + 0 + + + NDIE_1 + Enabled + 0x1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 11 + 1 + read-write + + + ALIE_0 + Disabled + 0 + + + ALIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 12 + 1 + read-write + + + FEIE_0 + Enabled + 0 + + + FEIE_1 + Disabled + 0x1 + + + + + PLTIE + Pin Low Timeout Interrupt Enable + 13 + 1 + read-write + + + PLTIE_0 + Disabled + 0 + + + PLTIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 14 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + MDER + Master DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + MCFGR0 + Master Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request input is disabled + 0 + + + HREN_1 + Host request input is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is pin HREQ + 0 + + + HRSEL_1 + Host request input is input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO + 0 + + + RDMO_1 + Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + 0x1 + + + + + + + MCFGR1 + Master Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALE + Prescaler + 0 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + AUTOSTOP + Automatic STOP Generation + 8 + 1 + read-write + + + AUTOSTOP_0 + No effect + 0 + + + AUTOSTOP_1 + STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + 0x1 + + + + + IGNACK + IGNACK + 9 + 1 + read-write + + + IGNACK_0 + LPI2C Master will receive ACK and NACK normally + 0 + + + IGNACK_1 + LPI2C Master will treat a received NACK as if it (NACK) was an ACK + 0x1 + + + + + TIMECFG + Timeout Configuration + 10 + 1 + read-write + + + TIMECFG_0 + Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + 0 + + + TIMECFG_1 + Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + Match is enabled (1st data word equals MATCH0 OR MATCH1) + 0x2 + + + MATCFG_3 + Match is enabled (any data word equals MATCH0 OR MATCH1) + 0x3 + + + MATCFG_4 + Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + 0x4 + + + MATCFG_5 + Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + 0x5 + + + MATCFG_6 + Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x6 + + + MATCFG_7 + Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 3 + read-write + + + PINCFG_0 + 2-pin open drain mode + 0 + + + PINCFG_1 + 2-pin output only mode (ultra-fast mode) + 0x1 + + + PINCFG_2 + 2-pin push-pull mode + 0x2 + + + PINCFG_3 + 4-pin push-pull mode + 0x3 + + + PINCFG_4 + 2-pin open drain mode with separate LPI2C slave + 0x4 + + + PINCFG_5 + 2-pin output only mode (ultra-fast mode) with separate LPI2C slave + 0x5 + + + PINCFG_6 + 2-pin push-pull mode with separate LPI2C slave + 0x6 + + + PINCFG_7 + 4-pin push-pull mode (inverted outputs) + 0x7 + + + + + + + MCFGR2 + Master Configuration Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSIDLE + Bus Idle Timeout + 0 + 12 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + MCFGR3 + Master Configuration Register 3 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PINLOW + Pin Low Timeout + 8 + 12 + read-write + + + + + MDMR + Master Data Match Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 8 + read-write + + + MATCH1 + Match 1 Value + 16 + 8 + read-write + + + + + MCCR0 + Master Clock Configuration Register 0 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MCCR1 + Master Clock Configuration Register 1 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MFCR + Master FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 2 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 2 + read-write + + + + + MFSR + Master FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 3 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 3 + read-only + + + + + MTDR + Master Transmit Data Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + CMD + Command Data + 8 + 3 + write-only + + + CMD_0 + Transmit DATA[7:0] + 0 + + + CMD_1 + Receive (DATA[7:0] + 1) bytes + 0x1 + + + CMD_2 + Generate STOP condition + 0x2 + + + CMD_3 + Receive and discard (DATA[7:0] + 1) bytes + 0x3 + + + CMD_4 + Generate (repeated) START and transmit address in DATA[7:0] + 0x4 + + + CMD_5 + Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + 0x5 + + + CMD_6 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + 0x6 + + + CMD_7 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + 0x7 + + + + + + + MRDR + Master Receive Data Register + 0x70 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + Receive FIFO is not empty + 0 + + + RXEMPTY_1 + Receive FIFO is empty + 0x1 + + + + + + + SCR + Slave Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEN + Slave Enable + 0 + 1 + read-write + + + SEN_0 + I2C Slave mode is disabled + 0 + + + SEN_1 + I2C Slave mode is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Slave mode logic is not reset + 0 + + + RST_1 + Slave mode logic is reset + 0x1 + + + + + FILTEN + Filter Enable + 4 + 1 + read-write + + + FILTEN_0 + Disable digital filter and output delay counter for slave mode + 0 + + + FILTEN_1 + Enable digital filter and output delay counter for slave mode + 0x1 + + + + + FILTDZ + Filter Doze Enable + 5 + 1 + read-write + + + FILTDZ_0 + Filter remains enabled in Doze mode + 0 + + + FILTDZ_1 + Filter is disabled in Doze mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit Data Register is now empty + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive Data Register is now empty + 0x1 + + + + + + + SSR + Slave Status Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + AVF + Address Valid Flag + 2 + 1 + read-only + + + AVF_0 + Address Status Register is not valid + 0 + + + AVF_1 + Address Status Register is valid + 0x1 + + + + + TAF + Transmit ACK Flag + 3 + 1 + read-only + + + TAF_0 + Transmit ACK/NACK is not required + 0 + + + TAF_1 + Transmit ACK/NACK is required + 0x1 + + + + + RSF + Repeated Start Flag + 8 + 1 + read-write + oneToClear + + + RSF_0 + Slave has not detected a Repeated START condition + 0 + + + RSF_1 + Slave has detected a Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Slave has not detected a STOP condition + 0 + + + SDF_1 + Slave has detected a STOP condition + 0x1 + + + + + BEF + Bit Error Flag + 10 + 1 + read-write + oneToClear + + + BEF_0 + Slave has not detected a bit error + 0 + + + BEF_1 + Slave has detected a bit error + 0x1 + + + + + FEF + FIFO Error Flag + 11 + 1 + read-write + oneToClear + + + FEF_0 + FIFO underflow or overflow was not detected + 0 + + + FEF_1 + FIFO underflow or overflow was detected + 0x1 + + + + + AM0F + Address Match 0 Flag + 12 + 1 + read-only + + + AM0F_0 + Have not received an ADDR0 matching address + 0 + + + AM0F_1 + Have received an ADDR0 matching address + 0x1 + + + + + AM1F + Address Match 1 Flag + 13 + 1 + read-only + + + AM1F_0 + Have not received an ADDR1 or ADDR0/ADDR1 range matching address + 0 + + + AM1F_1 + Have received an ADDR1 or ADDR0/ADDR1 range matching address + 0x1 + + + + + GCF + General Call Flag + 14 + 1 + read-only + + + GCF_0 + Slave has not detected the General Call Address or the General Call Address is disabled + 0 + + + GCF_1 + Slave has detected the General Call Address + 0x1 + + + + + SARF + SMBus Alert Response Flag + 15 + 1 + read-only + + + SARF_0 + SMBus Alert Response is disabled or not detected + 0 + + + SARF_1 + SMBus Alert Response is enabled and detected + 0x1 + + + + + SBF + Slave Busy Flag + 24 + 1 + read-only + + + SBF_0 + I2C Slave is idle + 0 + + + SBF_1 + I2C Slave is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + SIER + Slave Interrupt Enable Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + AVIE + Address Valid Interrupt Enable + 2 + 1 + read-write + + + AVIE_0 + Disabled + 0 + + + AVIE_1 + Enabled + 0x1 + + + + + TAIE + Transmit ACK Interrupt Enable + 3 + 1 + read-write + + + TAIE_0 + Disabled + 0 + + + TAIE_1 + Enabled + 0x1 + + + + + RSIE + Repeated Start Interrupt Enable + 8 + 1 + read-write + + + RSIE_0 + Disabled + 0 + + + RSIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + BEIE + Bit Error Interrupt Enable + 10 + 1 + read-write + + + BEIE_0 + Disabled + 0 + + + BEIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 11 + 1 + read-write + + + FEIE_0 + Disabled + 0 + + + FEIE_1 + Enabled + 0x1 + + + + + AM0IE + Address Match 0 Interrupt Enable + 12 + 1 + read-write + + + AM0IE_0 + Enabled + 0 + + + AM0IE_1 + Disabled + 0x1 + + + + + AM1F + Address Match 1 Interrupt Enable + 13 + 1 + read-write + + + AM1F_0 + Disabled + 0 + + + AM1F_1 + Enabled + 0x1 + + + + + GCIE + General Call Interrupt Enable + 14 + 1 + read-write + + + GCIE_0 + Disabled + 0 + + + GCIE_1 + Enabled + 0x1 + + + + + SARIE + SMBus Alert Response Interrupt Enable + 15 + 1 + read-write + + + SARIE_0 + Disabled + 0 + + + SARIE_1 + Enabled + 0x1 + + + + + + + SDER + Slave DMA Enable Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + AVDE + Address Valid DMA Enable + 2 + 1 + read-write + + + AVDE_0 + DMA request is disabled + 0 + + + AVDE_1 + DMA request is enabled + 0x1 + + + + + + + SCFGR1 + Slave Configuration Register 1 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADRSTALL + Address SCL Stall + 0 + 1 + read-write + + + ADRSTALL_0 + Clock stretching is disabled + 0 + + + ADRSTALL_1 + Clock stretching is enabled + 0x1 + + + + + RXSTALL + RX SCL Stall + 1 + 1 + read-write + + + RXSTALL_0 + Clock stretching is disabled + 0 + + + RXSTALL_1 + Clock stretching is enabled + 0x1 + + + + + TXDSTALL + TX Data SCL Stall + 2 + 1 + read-write + + + TXDSTALL_0 + Clock stretching is disabled + 0 + + + TXDSTALL_1 + Clock stretching is enabled + 0x1 + + + + + ACKSTALL + ACK SCL Stall + 3 + 1 + read-write + + + ACKSTALL_0 + Clock stretching is disabled + 0 + + + ACKSTALL_1 + Clock stretching is enabled + 0x1 + + + + + GCEN + General Call Enable + 8 + 1 + read-write + + + GCEN_0 + General Call address is disabled + 0 + + + GCEN_1 + General Call address is enabled + 0x1 + + + + + SAEN + SMBus Alert Enable + 9 + 1 + read-write + + + SAEN_0 + Disables match on SMBus Alert + 0 + + + SAEN_1 + Enables match on SMBus Alert + 0x1 + + + + + TXCFG + Transmit Flag Configuration + 10 + 1 + read-write + + + TXCFG_0 + Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + 0 + + + TXCFG_1 + Transmit Data Flag will assert whenever the Transmit Data register is empty + 0x1 + + + + + RXCFG + Receive Data Configuration + 11 + 1 + read-write + + + RXCFG_0 + Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + 0 + + + RXCFG_1 + Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + 0x1 + + + + + IGNACK + Ignore NACK + 12 + 1 + read-write + + + IGNACK_0 + Slave will end transfer when NACK is detected + 0 + + + IGNACK_1 + Slave will not end transfer when NACK detected + 0x1 + + + + + HSMEN + High Speed Mode Enable + 13 + 1 + read-write + + + HSMEN_0 + Disables detection of HS-mode master code + 0 + + + HSMEN_1 + Enables detection of HS-mode master code + 0x1 + + + + + ADDRCFG + Address Configuration + 16 + 3 + read-write + + + ADDRCFG_0 + Address match 0 (7-bit) + 0 + + + ADDRCFG_1 + Address match 0 (10-bit) + 0x1 + + + ADDRCFG_2 + Address match 0 (7-bit) or Address match 1 (7-bit) + 0x2 + + + ADDRCFG_3 + Address match 0 (10-bit) or Address match 1 (10-bit) + 0x3 + + + ADDRCFG_4 + Address match 0 (7-bit) or Address match 1 (10-bit) + 0x4 + + + ADDRCFG_5 + Address match 0 (10-bit) or Address match 1 (7-bit) + 0x5 + + + ADDRCFG_6 + From Address match 0 (7-bit) to Address match 1 (7-bit) + 0x6 + + + ADDRCFG_7 + From Address match 0 (10-bit) to Address match 1 (10-bit) + 0x7 + + + + + + + SCFGR2 + Slave Configuration Register 2 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKHOLD + Clock Hold Time + 0 + 4 + read-write + + + DATAVD + Data Valid Delay + 8 + 6 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + SAMR + Slave Address Match Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + Address 0 Value + 1 + 10 + read-write + + + ADDR1 + Address 1 Value + 17 + 10 + read-write + + + + + SASR + Slave Address Status Register + 0x150 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + RADDR + Received Address + 0 + 11 + read-only + + + ANV + Address Not Valid + 14 + 1 + read-only + + + ANV_0 + Received Address (RADDR) is valid + 0 + + + ANV_1 + Received Address (RADDR) is not valid + 0x1 + + + + + + + STAR + Slave Transmit ACK Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXNACK + Transmit NACK + 0 + 1 + read-write + + + TXNACK_0 + Write a Transmit ACK for each received word + 0 + + + TXNACK_1 + Write a Transmit NACK for each received word + 0x1 + + + + + + + STDR + Slave Transmit Data Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + + + SRDR + Slave Receive Data Register + 0x170 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + The Receive Data Register is not empty + 0 + + + RXEMPTY_1 + The Receive Data Register is empty + 0x1 + + + + + SOF + Start Of Frame + 15 + 1 + read-only + + + SOF_0 + Indicates this is not the first data word since a (repeated) START or STOP condition + 0 + + + SOF_1 + Indicates this is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + + + LPI2C2 + LPI2C + LPI2C + 0x403F4000 + + 0 + 0x174 + registers + + + LPI2C2 + 29 + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xFAC + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + DISFOLD_0 + Normal operation. + 0 + + + + + FPEXCODIS + Disables FPU exception outputs. + 10 + 1 + read-write + + + FPEXCODIS_0 + Normal operation. + 0 + + + FPEXCODIS_1 + FPU exception outputs are disabled. + 0x1 + + + + + DISRAMODE + Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. + 11 + 1 + read-write + + + DISRAMODE_0 + Normal operation. + 0 + + + DISRAMODE_1 + Dynamic disabled. + 0x1 + + + + + DISITMATBFLUSH + Disables ITM and DWT ATB flush. + 12 + 1 + read-write + + + DISITMATBFLUSH_1 + ITM and DWT ATB flush disabled, this bit is always 1. + 0x1 + + + + + DISBTACREAD + Disables BTAC read. + 13 + 1 + read-write + + + DISBTACREAD_0 + Normal operation. + 0 + + + DISBTACREAD_1 + BTAC is not used and only static branch prediction can occur. + 0x1 + + + + + DISBTACALLOC + Disables BTAC allocate. + 14 + 1 + read-write + + + DISBTACALLOC_0 + Normal operation. + 0 + + + DISBTACALLOC_1 + No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. + 0x1 + + + + + DISCRITAXIRUR + Disables critical AXI Read-Under-Read. + 15 + 1 + read-write + + + DISCRITAXIRUR_0 + Normal operation. + 0 + + + DISCRITAXIRUR_1 + An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. + 0x1 + + + + + DISDI + Disables dual-issued. + 16 + 5 + read-write + + + DISDI_0 + Normal operation. + 0 + + + DISDI_1 + Nothing can be dual-issued when this instruction type is in channel 0. + 0x1 + + + + + DISISSCH1 + Disables dual-issued. + 21 + 5 + read-write + + + DISISSCH1_0 + Normal operation. + 0 + + + DISISSCH1_1 + Nothing can be dual-issued when this instruction type is in channel 1. + 0x1 + + + + + DISDYNADD + Disables dynamic allocation of ADD and SUB instructions + 26 + 1 + read-write + + + DISDYNADD_0 + Normal operation. Some ADD and SUB instrctions are resolved in EX1. + 0 + + + DISDYNADD_1 + All ADD and SUB instructions are resolved in EX2. + 0x1 + + + + + DISCRITAXIRUW + Disables critical AXI read-under-write + 27 + 1 + read-write + + + DISCRITAXIRUW_0 + Normal operation. This is backwards compatible with r0. + 0 + + + DISCRITAXIRUW_1 + AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. + 0x1 + + + + + DISFPUISSOPT + Disables critical AXI read-under-write + 28 + 1 + read-write + + + DISFPUISSOPT_0 + Normal operation. + 0 + + + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + ARCHITECTURE + ARCHITECTURE + 16 + 4 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + Indicates whether there are preempted active exceptions + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + read-only + + + ISRPENDING + Interrupt pending flag, excluding NMI and Faults + 22 + 1 + read-only + + + ISRPENDING_0 + No external interrupt pending. + 0 + + + ISRPENDING_1 + External interrupt pending. + 0x1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Writing 1 to this bit causes a local system reset + 0 + 1 + write-only + + + VECTRESET_0 + No change + 0 + + + VECTRESET_1 + Causes a local system reset + 0x1 + + + + + VECTCLRACTIVE + Writing 1 to this bit clears all active state information for fixed and configurable exceptions. + 1 + 1 + write-only + + + VECTCLRACTIVE_0 + No change + 0 + + + VECTCLRACTIVE_1 + Clears all active state information for fixed and configurable exceptions + 0x1 + + + + + SYSRESETREQ + System reset request + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + Data endianness + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + NONBASETHRDENA + Indicates how the processor enters Thread mode + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + DC + Enables L1 data cache. + 16 + 1 + read-write + + + DC_0 + L1 data cache disabled + 0 + + + DC_1 + L1 data cache enabled + 0x1 + + + + + IC + Enables L1 instruction cache. + 17 + 1 + read-write + + + IC_0 + L1 instruction cache disabled + 0 + + + IC_1 + L1 instruction cache enabled + 0x1 + + + + + BP + Always reads-as-one. It indicates branch prediction is enabled. + 18 + 1 + read-only + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + SVCall active bit + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + Debug monitor active bit + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + PendSV exception active bit + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + MemManage fault occurred during floating-point lazy state preservation + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + Instruction bus error + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + Precise data bus error + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + Bus fault occurred during floating-point lazy state preservation + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + No coprocessor UsageFault + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + Indicates a BusFault on a vector table read during exception processing. + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. + 31 + 1 + read-write + + + DEBUGEVT_0 + No Debug event has occurred. + 0 + + + DEBUGEVT_1 + Debug event has occurred. The Debug Fault Status Register has been updated. + 0x1 + + + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + Debug event generated by BKPT instruction execution or a breakpoint match in FPB + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + Debug event generated by the DWT + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + Indicates triggering of a Vector catch + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + Debug event generated because of the assertion of an external debug request + 4 + 1 + read-write + + + EXTERNAL_0 + No external debug request debug event + 0 + + + EXTERNAL_1 + External debug request debug event + 0x1 + + + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + ID_PFR0 + Processor Feature Register 0 + 0xD40 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATE0 + ARM instruction set support + 0 + 4 + read-only + + + STATE0_0 + ARMv7-M unused + 0 + + + STATE0_1 + ARMv7-M unused + 0x1 + + + STATE0_2 + ARMv7-M unused + 0x2 + + + STATE0_3 + Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. + 0x3 + + + + + STATE1 + Thumb instruction set support + 4 + 4 + read-only + + + STATE1_0 + The processor does not support the ARM instruction set. + 0 + + + STATE1_1 + ARMv7-M unused + 0x1 + + + + + STATE2 + ARMv7-M unused + 8 + 4 + read-only + + + STATE3 + ARMv7-M unused + 12 + 4 + read-only + + + + + ID_PFR1 + Processor Feature Register 1 + 0xD44 + 32 + read-only + 0 + 0xFFFFFFFF + + + PROGMODEL + M profile programmers' model + 8 + 4 + read-only + + + PROGMODEL_0 + ARMv7-M unused + 0 + + + PROGMODEL_2 + Two-stack programmers' model supported + 0x2 + + + + + + + ID_DFR0 + Debug Feature Register + 0xD48 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUGMODEL + Support for memory-mapped debug model for M profile processors + 20 + 4 + read-only + + + DEBUGMODEL_0 + Not supported + 0 + + + DEBUGMODEL_1 + Support for M profile Debug architecture, with memory-mapped access. + 0x1 + + + + + + + ID_AFR0 + Auxiliary Feature Register + 0xD4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IMPLEMENTATION_DEFINED0 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 0 + 4 + read-only + + + IMPLEMENTATION_DEFINED1 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 4 + 4 + read-only + + + IMPLEMENTATION_DEFINED2 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 8 + 4 + read-only + + + IMPLEMENTATION_DEFINED3 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 12 + 4 + read-only + + + + + ID_MMFR0 + Memory Model Feature Register 0 + 0xD50 + 32 + read-only + 0 + 0xFFFFFFFF + + + PMSASUPPORT + Indicates support for a PMSA + 4 + 4 + read-only + + + PMSASUPPORT_0 + Not supported + 0 + + + PMSASUPPORT_1 + ARMv7-M unused + 0x1 + + + PMSASUPPORT_2 + ARMv7-M unused + 0x2 + + + PMSASUPPORT_3 + PMSAv7, providing support for a base region and subregions. + 0x3 + + + + + OUTERMOST_SHAREABILITY + Indicates the outermost shareability domain implemented + 8 + 4 + read-only + + + OUTERMOST_SHAREABILITY_0 + Implemented as Non-cacheable + 0 + + + OUTERMOST_SHAREABILITY_1 + ARMv7-M unused + 0x1 + + + OUTERMOST_SHAREABILITY_2 + ARMv7-M unused + 0x2 + + + OUTERMOST_SHAREABILITY_3 + ARMv7-M unused + 0x3 + + + OUTERMOST_SHAREABILITY_4 + ARMv7-M unused + 0x4 + + + OUTERMOST_SHAREABILITY_5 + ARMv7-M unused + 0x5 + + + OUTERMOST_SHAREABILITY_6 + ARMv7-M unused + 0x6 + + + OUTERMOST_SHAREABILITY_7 + ARMv7-M unused + 0x7 + + + OUTERMOST_SHAREABILITY_8 + ARMv7-M unused + 0x8 + + + OUTERMOST_SHAREABILITY_9 + ARMv7-M unused + 0x9 + + + OUTERMOST_SHAREABILITY_10 + ARMv7-M unused + 0xA + + + OUTERMOST_SHAREABILITY_11 + ARMv7-M unused + 0xB + + + OUTERMOST_SHAREABILITY_12 + ARMv7-M unused + 0xC + + + OUTERMOST_SHAREABILITY_13 + ARMv7-M unused + 0xD + + + OUTERMOST_SHAREABILITY_14 + ARMv7-M unused + 0xE + + + OUTERMOST_SHAREABILITY_15 + Shareability ignored. + 0xF + + + + + SHAREABILITY_LEVELS + Indicates the number of shareability levels implemented + 12 + 4 + read-only + + + SHAREABILITY_LEVELS_0 + One level of shareability implemented + 0 + + + SHAREABILITY_LEVELS_1 + ARMv7-M unused + 0x1 + + + + + TCM_SUPPORT + Indicates the support for Tightly Coupled Memory + 16 + 4 + read-only + + + TCM_SUPPORT_0 + No tightly coupled memories implemented. + 0 + + + TCM_SUPPORT_1 + Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. + 0x1 + + + TCM_SUPPORT_2 + ARMv7-M unused + 0x2 + + + + + AUXILIARY_REGISTERS + Indicates the support for Auxiliary registers + 20 + 4 + read-only + + + AUXILIARY_REGISTERS_0 + Not supported + 0 + + + AUXILIARY_REGISTERS_1 + Support for Auxiliary Control Register only. + 0x1 + + + AUXILIARY_REGISTERS_2 + ARMv7-M unused + 0x2 + + + + + + + ID_MMFR1 + Memory Model Feature Register 1 + 0xD54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR1 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_MMFR2 + Memory Model Feature Register 2 + 0xD58 + 32 + read-only + 0 + 0xFFFFFFFF + + + WFI_STALL + Indicates the support for Wait For Interrupt (WFI) stalling + 24 + 4 + read-only + + + WFI_STALL_0 + Not supported + 0 + + + WFI_STALL_1 + Support for WFI stalling + 0x1 + + + + + + + ID_MMFR3 + Memory Model Feature Register 3 + 0xD5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR3 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_ISAR0 + Instruction Set Attributes Register 0 + 0xD60 + 32 + read-only + 0 + 0xFFFFFFFF + + + BITCOUNT_INSTRS + Indicates the supported Bit Counting instructions + 4 + 4 + read-only + + + BITCOUNT_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITCOUNT_INSTRS_1 + Adds support for the CLZ instruction + 0x1 + + + + + BITFIELD_INSTRS + Indicates the supported BitField instructions + 8 + 4 + read-only + + + BITFIELD_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITFIELD_INSTRS_1 + Adds support for the BFC, BFI, SBFX, and UBFX instructions + 0x1 + + + + + CMPBRANCH_INSTRS + Indicates the supported combined Compare and Branch instructions + 12 + 4 + read-only + + + CMPBRANCH_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + CMPBRANCH_INSTRS_1 + Adds support for the CBNZ and CBZ instructions + 0x1 + + + + + COPROC_INSTRS + Indicates the supported Coprocessor instructions + 16 + 4 + read-only + + + COPROC_INSTRS_0 + None supported, except for separately attributed architectures, for example the Floating-point extension + 0 + + + COPROC_INSTRS_1 + Adds support for generic CDP, LDC, MCR, MRC, and STC instructions + 0x1 + + + COPROC_INSTRS_2 + As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions + 0x2 + + + COPROC_INSTRS_3 + As for 2, and adds support for generic MCRR and MRRC instructions + 0x3 + + + COPROC_INSTRS_4 + As for 3, and adds support for generic MCRR2 and MRRC2 instructions + 0x4 + + + + + DEBUG_INSTRS + Indicates the supported Debug instructions + 20 + 4 + read-only + + + DEBUG_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DEBUG_INSTRS_1 + Adds support for the BKPT instruction + 0x1 + + + + + DIVIDE_INSTRS + Indicates the supported Divide instructions + 24 + 4 + read-only + + + DIVIDE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DIVIDE_INSTRS_1 + Adds support for the SDIV and UDIV instructions + 0x1 + + + + + + + ID_ISAR1 + Instruction Set Attributes Register 1 + 0xD64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EXTEND_INSTRS + Indicates the supported Extend instructions + 12 + 4 + read-only + + + EXTEND_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + EXTEND_INSTRS_1 + Adds support for the SXTB, SXTH, UXTB, and UXTH instructions + 0x1 + + + EXTEND_INSTRS_2 + As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions + 0x2 + + + + + IFTHEN_INSTRS + Indicates the supported IfThen instructions + 16 + 4 + read-only + + + IFTHEN_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IFTHEN_INSTRS_1 + Adds support for the IT instructions, and for the IT bits in the PSRs + 0x1 + + + + + IMMEDIATE_INSTRS + Indicates the support for data-processing instructions with long immediate + 20 + 4 + read-only + + + IMMEDIATE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IMMEDIATE_INSTRS_1 + Adds support for the ADDW, MOVW, MOVT, and SUBW instructions + 0x1 + + + + + INTERWORK_INSTRS + Indicates the supported Interworking instructions + 24 + 4 + read-only + + + INTERWORK_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + INTERWORK_INSTRS_1 + Adds support for the BX instruction, and the T bit in the PSR + 0x1 + + + INTERWORK_INSTRS_2 + As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior + 0x2 + + + INTERWORK_INSTRS_3 + ARMv7-M unused + 0x3 + + + + + + + ID_ISAR2 + Instruction Set Attributes Register 2 + 0xD68 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOADSTORE_INSTRS + Indicates the supported additional load and store instructions + 0 + 4 + read-only + + + LOADSTORE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + LOADSTORE_INSTRS_1 + Adds support for the LDRD and STRD instructions + 0x1 + + + + + MEMHINT_INSTRS + Indicates the supported Memory Hint instructions + 4 + 4 + read-only + + + MEMHINT_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + MEMHINT_INSTRS_1 + Adds support for the PLD instruction, ARMv7-M unused. + 0x1 + + + MEMHINT_INSTRS_2 + As for 1, ARMv7-M unused. + 0x2 + + + MEMHINT_INSTRS_3 + As for 1 or 2, and adds support for the PLI instruction. + 0x3 + + + + + MULTIACCESSINT_INSTRS + Indicates the support for multi-access interruptible instructions + 8 + 4 + read-only + + + MULTIACCESSINT_INSTRS_0 + None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. + 0 + + + MULTIACCESSINT_INSTRS_1 + LDM and STM instructions are restartable. + 0x1 + + + MULTIACCESSINT_INSTRS_2 + LDM and STM instructions are continuable. + 0x2 + + + + + MULT_INSTRS + Indicates the supported additional Multiply instructions + 12 + 4 + read-only + + + MULT_INSTRS_0 + None supported. This means only MUL is supported. ARMv7-M unused. + 0 + + + MULT_INSTRS_1 + Adds support for the MLA instruction, ARMv7-M unused. + 0x1 + + + MULT_INSTRS_2 + As for 1, and adds support for the MLS instruction. + 0x2 + + + + + MULTS_INSTRS + Indicates the supported advanced signed Multiply instructions + 16 + 4 + read-only + + + MULTS_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTS_INSTRS_1 + Adds support for the SMULL and SMLAL instructions + 0x1 + + + MULTS_INSTRS_2 + As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. + 0x2 + + + MULTS_INSTRS_3 + As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. + 0x3 + + + + + MULTU_INSTRS + Indicates the supported advanced unsigned Multiply instructions + 20 + 4 + read-only + + + MULTU_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTU_INSTRS_1 + Adds support for the UMULL and UMLAL instructions. + 0x1 + + + MULTU_INSTRS_2 + As for 1, and adds support for the UMAAL instruction. + 0x2 + + + + + REVERSAL_INSTRS + Indicates the supported Reversal instructions + 28 + 4 + read-only + + + REVERSAL_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + REVERSAL_INSTRS_1 + Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. + 0x1 + + + REVERSAL_INSTRS_2 + As for 1, and adds support for the RBIT instruction. + 0x2 + + + + + + + ID_ISAR3 + Instruction Set Attributes Register 3 + 0xD6C + 32 + read-only + 0 + 0xFFFFFFFF + + + SATURATE_INSTRS + Indicates the supported Saturate instructions + 0 + 4 + read-only + + + SATURATE_INSTRS_0 + None supported + 0 + + + SATURATE_INSTRS_1 + Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. + 0x1 + + + + + SIMD_INSTRS + Indicates the supported SIMD instructions + 4 + 4 + read-only + + + SIMD_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SIMD_INSTRS_1 + Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. + 0x1 + + + SIMD_INSTRS_3 + As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. + 0x3 + + + + + SVC_INSTRS + Indicates the supported SVC instructions + 8 + 4 + read-only + + + SVC_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SVC_INSTRS_1 + Adds support for the SVC instruction. + 0x1 + + + + + SYNCHPRIM_INSTRS + Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives + 12 + 4 + read-only + + + TABBRANCH_INSTRS + Indicates the supported Table Branch instructions + 16 + 4 + read-only + + + TABBRANCH_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TABBRANCH_INSTRS_1 + Adds support for the TBB and TBH instructions. + 0x1 + + + + + THUMBCOPY_INSTRS + Indicates the supported non flag-setting MOV instructions + 20 + 4 + read-only + + + THUMBCOPY_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + THUMBCOPY_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + TRUENOP_INSTRS + Indicates the supported non flag-setting MOV instructions + 24 + 4 + read-only + + + TRUENOP_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TRUENOP_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + + + ID_ISAR4 + Instruction Set Attributes Register 4 + 0xD70 + 32 + read-only + 0 + 0xFFFFFFFF + + + UNPRIV_INSTRS + Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. + 0 + 4 + read-only + + + UNPRIV_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + UNPRIV_INSTRS_1 + Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. + 0x1 + + + UNPRIV_INSTRS_2 + As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. + 0x2 + + + + + WITHSHIFTS_INSTRS + Indicates the support for instructions with shifts + 4 + 4 + read-only + + + WITHSHIFTS_INSTRS_0 + Nonzero shifts supported only in MOV and shift instructions. + 0 + + + WITHSHIFTS_INSTRS_1 + Adds support for shifts of loads and stores over the range LSL 0-3. + 0x1 + + + WITHSHIFTS_INSTRS_3 + As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. + 0x3 + + + WITHSHIFTS_INSTRS_4 + ARMv7-M unused. + 0x4 + + + + + WRITEBACK_INSTRS + Indicates the support for Writeback addressing modes + 8 + 4 + read-only + + + WRITEBACK_INSTRS_0 + Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. + 0 + + + WRITEBACK_INSTRS_1 + Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. + 0x1 + + + + + BARRIER_INSTRS + Indicates the supported Barrier instructions + 16 + 4 + read-only + + + BARRIER_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + BARRIER_INSTRS_1 + Adds support for the DMB, DSB, and ISB barrier instructions. + 0x1 + + + + + SYNCHPRIM_INSTRS_FRAC + Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives + 20 + 4 + read-only + + + PSR_M_INSTRS + Indicates the supported M profile instructions to modify the PSRs + 24 + 4 + read-only + + + PSR_M_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + PSR_M_INSTRS_1 + Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. + 0x1 + + + + + + + CLIDR + Cache Level ID register + 0xD78 + 32 + read-only + 0 + 0xFFFFFFFF + + + CL1 + Indicate the type of cache implemented at level 1. + 0 + 3 + read-only + + + CL1_0 + No cache + 0 + + + CL1_1 + Instruction cache only + 0x1 + + + CL1_2 + Data cache only + 0x2 + + + CL1_3 + Separate instruction and data caches + 0x3 + + + CL1_4 + Unified cache + 0x4 + + + + + CL2 + Indicate the type of cache implemented at level 2. + 3 + 3 + read-only + + + CL2_0 + No cache + 0 + + + CL2_1 + Instruction cache only + 0x1 + + + CL2_2 + Data cache only + 0x2 + + + CL2_3 + Separate instruction and data caches + 0x3 + + + CL2_4 + Unified cache + 0x4 + + + + + CL3 + Indicate the type of cache implemented at level 3. + 6 + 3 + read-only + + + CL3_0 + No cache + 0 + + + CL3_1 + Instruction cache only + 0x1 + + + CL3_2 + Data cache only + 0x2 + + + CL3_3 + Separate instruction and data caches + 0x3 + + + CL3_4 + Unified cache + 0x4 + + + + + CL4 + Indicate the type of cache implemented at level 4. + 9 + 3 + read-only + + + CL4_0 + No cache + 0 + + + CL4_1 + Instruction cache only + 0x1 + + + CL4_2 + Data cache only + 0x2 + + + CL4_3 + Separate instruction and data caches + 0x3 + + + CL4_4 + Unified cache + 0x4 + + + + + CL5 + Indicate the type of cache implemented at level 5. + 12 + 3 + read-only + + + CL5_0 + No cache + 0 + + + CL5_1 + Instruction cache only + 0x1 + + + CL5_2 + Data cache only + 0x2 + + + CL5_3 + Separate instruction and data caches + 0x3 + + + CL5_4 + Unified cache + 0x4 + + + + + CL6 + Indicate the type of cache implemented at level 6. + 15 + 3 + read-only + + + CL6_0 + No cache + 0 + + + CL6_1 + Instruction cache only + 0x1 + + + CL6_2 + Data cache only + 0x2 + + + CL6_3 + Separate instruction and data caches + 0x3 + + + CL6_4 + Unified cache + 0x4 + + + + + CL7 + Indicate the type of cache implemented at level 7. + 18 + 3 + read-only + + + CL7_0 + No cache + 0 + + + CL7_1 + Instruction cache only + 0x1 + + + CL7_2 + Data cache only + 0x2 + + + CL7_3 + Separate instruction and data caches + 0x3 + + + CL7_4 + Unified cache + 0x4 + + + + + LOUIS + Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. + 21 + 3 + read-only + + + LOUIS_0 + 0 + 0 + + + LOUIS_1 + 1 + 0x1 + + + LOUIS_2 + 2 + 0x2 + + + LOUIS_3 + 3 + 0x3 + + + LOUIS_4 + 4 + 0x4 + + + LOUIS_5 + 5 + 0x5 + + + LOUIS_6 + 6 + 0x6 + + + LOUIS_7 + 7 + 0x7 + + + + + LOC + Level of Coherency for the cache hierarchy + 24 + 3 + read-only + + + LOC_0 + 0 + 0 + + + LOC_1 + 1 + 0x1 + + + LOC_2 + 2 + 0x2 + + + LOC_3 + 3 + 0x3 + + + LOC_4 + 4 + 0x4 + + + LOC_5 + 5 + 0x5 + + + LOC_6 + 6 + 0x6 + + + LOC_7 + 7 + 0x7 + + + + + LOU + Level of Unification for the cache hierarchy + 27 + 3 + read-only + + + LOU_0 + 0 + 0 + + + LOU_1 + 1 + 0x1 + + + LOU_2 + 2 + 0x2 + + + LOU_3 + 3 + 0x3 + + + LOU_4 + 4 + 0x4 + + + LOU_5 + 5 + 0x5 + + + LOU_6 + 6 + 0x6 + + + LOU_7 + 7 + 0x7 + + + + + + + CTR + Cache Type register + 0xD7C + 32 + read-only + 0x8000C000 + 0xFFFFFFFF + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. + 0 + 4 + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. + 16 + 4 + read-only + + + ERG + Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. + 20 + 4 + read-only + + + CWG + Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. + 24 + 4 + read-only + + + FORMAT + Indicates the implemented CTR format. + 29 + 3 + read-only + + + FORMAT_4 + ARMv7 format. + 0x4 + + + + + + + CCSIDR + Cache Size ID Register + 0xD80 + 32 + read-only + 0 + 0xFFFFFFFF + + + LINESIZE + (Log2(Number of words in cache line)) - 2. + 0 + 3 + read-only + + + LINESIZE_0 + The line length of 4 words. + 0 + + + LINESIZE_1 + The line length of 8 words. + 0x1 + + + LINESIZE_2 + The line length of 16 words. + 0x2 + + + LINESIZE_3 + The line length of 32 words. + 0x3 + + + LINESIZE_4 + The line length of 64 words. + 0x4 + + + LINESIZE_5 + The line length of 128 words. + 0x5 + + + LINESIZE_6 + The line length of 256 words. + 0x6 + + + LINESIZE_7 + The line length of 512 words. + 0x7 + + + + + ASSOCIATIVITY + (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. + 3 + 10 + read-only + + + NUMSETS + (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. + 13 + 15 + read-only + + + WA + Indicates whether the cache level supports write-allocation + 28 + 1 + read-only + + + WA_0 + Feature not supported + 0 + + + WA_1 + Feature supported + 0x1 + + + + + RA + Indicates whether the cache level supports read-allocation + 29 + 1 + read-only + + + RA_0 + Feature not supported + 0 + + + RA_1 + Feature supported + 0x1 + + + + + WB + Indicates whether the cache level supports write-back + 30 + 1 + read-only + + + WB_0 + Feature not supported + 0 + + + WB_1 + Feature supported + 0x1 + + + + + WT + Indicates whether the cache level supports write-through + 31 + 1 + read-only + + + WT_0 + Feature not supported + 0 + + + WT_1 + Feature supported + 0x1 + + + + + + + CSSELR + Cache Size Selection Register + 0xD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IND + Instruction not data bit + 0 + 1 + read-write + + + IND_0 + Data or unified cache. + 0 + + + IND_1 + Instruction cache. + 0x1 + + + + + LEVEL + Cache level of required cache + 1 + 3 + read-write + + + LEVEL_0 + Level 1 cache. + 0 + + + LEVEL_1 + Level 2 cache. + 0x1 + + + LEVEL_2 + Level 3 cache. + 0x2 + + + LEVEL_3 + Level 4 cache. + 0x3 + + + LEVEL_4 + Level 5 cache. + 0x4 + + + LEVEL_5 + Level 6 cache. + 0x5 + + + LEVEL_6 + Level 7 cache. + 0x6 + + + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CP0 + Access privileges for coprocessor 0. + 0 + 2 + read-write + + + CP0_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP0_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP0_3 + Full access. + 0x3 + + + + + CP1 + Access privileges for coprocessor 1. + 2 + 2 + read-write + + + CP1_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP1_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP1_3 + Full access. + 0x3 + + + + + CP2 + Access privileges for coprocessor 2. + 4 + 2 + read-write + + + CP2_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP2_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP2_3 + Full access. + 0x3 + + + + + CP3 + Access privileges for coprocessor 3. + 6 + 2 + read-write + + + CP3_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP3_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP3_3 + Full access. + 0x3 + + + + + CP4 + Access privileges for coprocessor 4. + 8 + 2 + read-write + + + CP4_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP4_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP4_3 + Full access. + 0x3 + + + + + CP5 + Access privileges for coprocessor 5. + 10 + 2 + read-write + + + CP5_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP5_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP5_3 + Full access. + 0x3 + + + + + CP6 + Access privileges for coprocessor 6. + 12 + 2 + read-write + + + CP6_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP6_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP6_3 + Full access. + 0x3 + + + + + CP7 + Access privileges for coprocessor 7. + 14 + 2 + read-write + + + CP7_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP7_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP7_3 + Full access. + 0x3 + + + + + CP10 + Access privileges for coprocessor 10. + 20 + 2 + read-write + + + CP10_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP10_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP10_3 + Full access. + 0x3 + + + + + CP11 + Access privileges for coprocessor 11. + 22 + 2 + read-write + + + CP11_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP11_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP11_3 + Full access. + 0x3 + + + + + + + STIR + Instruction cache invalidate all to Point of Unification (PoU) + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Indicates the interrupt to be triggered + 0 + 9 + write-only + + + + + ICIALLU + Instruction cache invalidate all to Point of Unification (PoU) + 0xF50 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIALLU + I-cache invalidate all to PoU + 0 + 32 + write-only + + + + + ICIMVAU + Instruction cache invalidate by address to PoU + 0xF58 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIMVAU + I-cache invalidate by MVA to PoU + 0 + 32 + write-only + + + + + DCIMVAC + Data cache invalidate by address to Point of Coherency (PoC) + 0xF5C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCIMVAC + D-cache invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCISW + Data cache invalidate by set/way + 0xF60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCISW + D-cache invalidate by set-way + 0 + 32 + write-only + + + + + DCCMVAU + Data cache by address to PoU + 0xF64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAU + D-cache clean by MVA to PoU + 0 + 32 + write-only + + + + + DCCMVAC + Data cache clean by address to PoC + 0xF68 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAC + D-cache clean by MVA to PoC + 0 + 32 + write-only + + + + + DCCSW + Data cache clean by set/way + 0xF6C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCSW + D-cache clean by set-way + 0 + 32 + write-only + + + + + DCCIMVAC + Data cache clean and invalidate by address to PoC + 0xF70 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCIMVAC + D-cache clean and invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCCISW + Data cache clean and invalidate by set/way + 0xF74 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCISW + D-cache clean and invalidate by set-way + 0 + 32 + write-only + + + + + CM7_ITCMCR + Instruction Tightly-Coupled Memory Control Register + 0xF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_DTCMCR + Data Tightly-Coupled Memory Control Register + 0xF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_AHBPCR + AHBP Control Register + 0xF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + AHBP enable. + 0 + 1 + read-write + + + EN_0 + AHBP disabled. When disabled all accesses are made to the AXIM interface. + 0 + + + EN_1 + AHBP enabled. + 0x1 + + + + + SZ + AHBP size. + 1 + 3 + read-only + + + SZ_0 + 0MB. AHBP disabled. + 0 + + + SZ_1 + 64MB. + 0x1 + + + SZ_2 + 128MB. + 0x2 + + + SZ_3 + 256MB. + 0x3 + + + SZ_4 + 512MB. + 0x4 + + + + + + + CM7_CACR + L1 Cache Control Register + 0xF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + SIWT + Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. + 0 + 1 + read-write + + + SIWT_0 + Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. + 0 + + + SIWT_1 + Normal Cacheable shared locations are treated as Write-Through. + 0x1 + + + + + ECCDIS + Enables ECC in the instruction and data cache. + 1 + 1 + read-write + + + ECCDIS_0 + Enables ECC in the instruction and data cache. + 0 + + + ECCDIS_1 + Disables ECC in the instruction and data cache. + 0x1 + + + + + FORCEWT + Enables Force Write-Through in the data cache. + 2 + 1 + read-write + + + FORCEWT_0 + Disables Force Write-Through. + 0 + + + FORCEWT_1 + Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. + 0x1 + + + + + + + CM7_AHBSCR + AHB Slave Control Register + 0xFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTL + AHBS prioritization control. + 0 + 2 + read-write + + + CTL_0 + AHBS access priority demoted. This is the reset value. + 0 + + + CTL_1 + Software access priority demoted. + 0x1 + + + CTL_2 + AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. + 0x2 + + + CTL_3 + AHBSPRI signal has control of access priority. + 0x3 + + + + + TPRI + Threshold execution priority for AHBS traffic demotion. + 2 + 9 + read-write + + + INITCOUNT + Fairness counter initialization value. + 11 + 5 + read-write + + + + + CM7_ABFSR + Auxiliary Bus Fault Status Register + 0xFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM + Asynchronous fault on ITCM interface. + 0 + 1 + read-write + + + DTCM + Asynchronous fault on DTCM interface. + 1 + 1 + read-write + + + AHBP + Asynchronous fault on AHBP interface. + 2 + 1 + read-write + + + AXIM + Asynchronous fault on AXIM interface. + 3 + 1 + read-write + + + EPPB + Asynchronous fault on EPPB interface. + 4 + 1 + read-write + + + AXIMTYPE + Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. + 8 + 2 + read-write + + + AXIMTYPE_0 + OKAY. + 0 + + + AXIMTYPE_1 + EXOKAY. + 0x1 + + + AXIMTYPE_2 + SLVERR. + 0x2 + + + AXIMTYPE_3 + DECERR. + 0x3 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + CTI0_ERROR + 17 + + + CTI1_ERROR + 18 + + + CORE + 19 + + + LPUART1 + 20 + + + LPUART2 + 21 + + + LPUART3 + 22 + + + LPUART4 + 23 + + + LPI2C1 + 28 + + + LPI2C2 + 29 + + + LPSPI1 + 32 + + + LPSPI2 + 33 + + + FLEXRAM + 38 + + + KPP + 39 + + + Reserved56 + 40 + + + GPR_IRQ + 41 + + + Reserved58 + 42 + + + Reserved59 + 43 + + + Reserved60 + 44 + + + WDOG2 + 45 + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + CSU + 49 + + + DCP + 50 + + + DCP_VMI + 51 + + + Reserved68 + 52 + + + TRNG + 53 + + + BEE + 55 + + + SAI1 + 56 + + + SAI2 + 57 + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + SPDIF + 60 + + + PMU + 61 + + + Reserved78 + 62 + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + USB_PHY + 65 + + + Reserved82 + 66 + + + ADC1 + 67 + + + DCDC + 69 + + + Reserved86 + 70 + + + Reserved87 + 71 + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + Reserved102 + 86 + + + Reserved103 + 87 + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + FLEXIO1 + 90 + + + Reserved107 + 91 + + + WDOG1 + 92 + + + RTWDOG + 93 + + + EWM + 94 + + + CCM_1 + 95 + + + CCM_2 + 96 + + + GPC + 97 + + + SRC + 98 + + + Reserved115 + 99 + + + GPT1 + 100 + + + GPT2 + 101 + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + Reserved123 + 107 + + + FLEXSPI + 108 + + + Reserved128 + 112 + + + USB_OTG1 + 113 + + + XBAR1_IRQ_0_1 + 116 + + + XBAR1_IRQ_2_3 + 117 + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + PIT + 122 + + + Reserved143 + 127 + + + Reserved144 + 128 + + + ENC1 + 129 + + + Reserved147 + 131 + + + Reserved148 + 132 + + + TMR1 + 133 + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER4 + Interrupt Set Enable Register n + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER4 + Interrupt Clear Enable Register n + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR4 + Interrupt Set Pending Register n + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR4 + Interrupt Clear Pending Register n + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR4 + Interrupt Active bit Register n + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register 0 + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of the INT_DMA0_DMA16 interrupt 0 + 4 + 4 + read-write + + + + + NVICIP1 + Interrupt Priority Register 1 + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of the INT_DMA1_DMA17 interrupt 1 + 4 + 4 + read-write + + + + + NVICIP2 + Interrupt Priority Register 2 + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of the INT_DMA2_DMA18 interrupt 2 + 4 + 4 + read-write + + + + + NVICIP3 + Interrupt Priority Register 3 + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of the INT_DMA3_DMA19 interrupt 3 + 4 + 4 + read-write + + + + + NVICIP4 + Interrupt Priority Register 4 + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of the INT_DMA4_DMA20 interrupt 4 + 4 + 4 + read-write + + + + + NVICIP5 + Interrupt Priority Register 5 + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of the INT_DMA5_DMA21 interrupt 5 + 4 + 4 + read-write + + + + + NVICIP6 + Interrupt Priority Register 6 + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of the INT_DMA6_DMA22 interrupt 6 + 4 + 4 + read-write + + + + + NVICIP7 + Interrupt Priority Register 7 + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of the INT_DMA7_DMA23 interrupt 7 + 4 + 4 + read-write + + + + + NVICIP8 + Interrupt Priority Register 8 + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of the INT_DMA8_DMA24 interrupt 8 + 4 + 4 + read-write + + + + + NVICIP9 + Interrupt Priority Register 9 + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of the INT_DMA9_DMA25 interrupt 9 + 4 + 4 + read-write + + + + + NVICIP10 + Interrupt Priority Register 10 + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of the INT_DMA10_DMA26 interrupt 10 + 4 + 4 + read-write + + + + + NVICIP11 + Interrupt Priority Register 11 + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of the INT_DMA11_DMA27 interrupt 11 + 4 + 4 + read-write + + + + + NVICIP12 + Interrupt Priority Register 12 + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of the INT_DMA12_DMA28 interrupt 12 + 4 + 4 + read-write + + + + + NVICIP13 + Interrupt Priority Register 13 + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of the INT_DMA13_DMA29 interrupt 13 + 4 + 4 + read-write + + + + + NVICIP14 + Interrupt Priority Register 14 + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of the INT_DMA14_DMA30 interrupt 14 + 4 + 4 + read-write + + + + + NVICIP15 + Interrupt Priority Register 15 + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of the INT_DMA15_DMA31 interrupt 15 + 4 + 4 + read-write + + + + + NVICIP16 + Interrupt Priority Register 16 + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of the INT_DMA_ERROR interrupt 16 + 4 + 4 + read-write + + + + + NVICIP17 + Interrupt Priority Register 17 + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of the INT_CTI0_ERROR interrupt 17 + 4 + 4 + read-write + + + + + NVICIP18 + Interrupt Priority Register 18 + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of the INT_CTI1_ERROR interrupt 18 + 4 + 4 + read-write + + + + + NVICIP19 + Interrupt Priority Register 19 + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of the INT_CORE interrupt 19 + 4 + 4 + read-write + + + + + NVICIP20 + Interrupt Priority Register 20 + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of the INT_LPUART1 interrupt 20 + 4 + 4 + read-write + + + + + NVICIP21 + Interrupt Priority Register 21 + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of the INT_LPUART2 interrupt 21 + 4 + 4 + read-write + + + + + NVICIP22 + Interrupt Priority Register 22 + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of the INT_LPUART3 interrupt 22 + 4 + 4 + read-write + + + + + NVICIP23 + Interrupt Priority Register 23 + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of the INT_LPUART4 interrupt 23 + 4 + 4 + read-write + + + + + NVICIP24 + Interrupt Priority Register 24 + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of interrupt 24 + 4 + 4 + read-write + + + + + NVICIP25 + Interrupt Priority Register 25 + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of interrupt 25 + 4 + 4 + read-write + + + + + NVICIP26 + Interrupt Priority Register 26 + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of interrupt 26 + 4 + 4 + read-write + + + + + NVICIP27 + Interrupt Priority Register 27 + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of interrupt 27 + 4 + 4 + read-write + + + + + NVICIP28 + Interrupt Priority Register 28 + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of the INT_LPI2C1 interrupt 28 + 4 + 4 + read-write + + + + + NVICIP29 + Interrupt Priority Register 29 + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of the INT_LPI2C2 interrupt 29 + 4 + 4 + read-write + + + + + NVICIP30 + Interrupt Priority Register 30 + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of interrupt 30 + 4 + 4 + read-write + + + + + NVICIP31 + Interrupt Priority Register 31 + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of interrupt 31 + 4 + 4 + read-write + + + + + NVICIP32 + Interrupt Priority Register 32 + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of the INT_LPSPI1 interrupt 32 + 4 + 4 + read-write + + + + + NVICIP33 + Interrupt Priority Register 33 + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of the INT_LPSPI2 interrupt 33 + 4 + 4 + read-write + + + + + NVICIP34 + Interrupt Priority Register 34 + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of interrupt 34 + 4 + 4 + read-write + + + + + NVICIP35 + Interrupt Priority Register 35 + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of interrupt 35 + 4 + 4 + read-write + + + + + NVICIP36 + Interrupt Priority Register 36 + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of interrupt 36 + 4 + 4 + read-write + + + + + NVICIP37 + Interrupt Priority Register 37 + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of interrupt 37 + 4 + 4 + read-write + + + + + NVICIP38 + Interrupt Priority Register 38 + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of the INT_FLEXRAM interrupt 38 + 4 + 4 + read-write + + + + + NVICIP39 + Interrupt Priority Register 39 + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of the INT_KPP interrupt 39 + 4 + 4 + read-write + + + + + NVICIP40 + Interrupt Priority Register 40 + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of the INT_Reserved56 interrupt 40 + 4 + 4 + read-write + + + + + NVICIP41 + Interrupt Priority Register 41 + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of the INT_GPR_IRQ interrupt 41 + 4 + 4 + read-write + + + + + NVICIP42 + Interrupt Priority Register 42 + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of the INT_Reserved58 interrupt 42 + 4 + 4 + read-write + + + + + NVICIP43 + Interrupt Priority Register 43 + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of the INT_Reserved59 interrupt 43 + 4 + 4 + read-write + + + + + NVICIP44 + Interrupt Priority Register 44 + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of the INT_Reserved60 interrupt 44 + 4 + 4 + read-write + + + + + NVICIP45 + Interrupt Priority Register 45 + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of the INT_WDOG2 interrupt 45 + 4 + 4 + read-write + + + + + NVICIP46 + Interrupt Priority Register 46 + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of the INT_SNVS_HP_WRAPPER interrupt 46 + 4 + 4 + read-write + + + + + NVICIP47 + Interrupt Priority Register 47 + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47 + 4 + 4 + read-write + + + + + NVICIP48 + Interrupt Priority Register 48 + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of the INT_SNVS_LP_WRAPPER interrupt 48 + 4 + 4 + read-write + + + + + NVICIP49 + Interrupt Priority Register 49 + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of the INT_CSU interrupt 49 + 4 + 4 + read-write + + + + + NVICIP50 + Interrupt Priority Register 50 + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of the INT_DCP interrupt 50 + 4 + 4 + read-write + + + + + NVICIP51 + Interrupt Priority Register 51 + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of the INT_DCP_VMI interrupt 51 + 4 + 4 + read-write + + + + + NVICIP52 + Interrupt Priority Register 52 + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of the INT_Reserved68 interrupt 52 + 4 + 4 + read-write + + + + + NVICIP53 + Interrupt Priority Register 53 + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of the INT_TRNG interrupt 53 + 4 + 4 + read-write + + + + + NVICIP54 + Interrupt Priority Register 54 + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of interrupt 54 + 4 + 4 + read-write + + + + + NVICIP55 + Interrupt Priority Register 55 + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of the INT_BEE interrupt 55 + 4 + 4 + read-write + + + + + NVICIP56 + Interrupt Priority Register 56 + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of the INT_SAI1 interrupt 56 + 4 + 4 + read-write + + + + + NVICIP57 + Interrupt Priority Register 57 + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of the INT_SAI2 interrupt 57 + 4 + 4 + read-write + + + + + NVICIP58 + Interrupt Priority Register 58 + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of the INT_SAI3_RX interrupt 58 + 4 + 4 + read-write + + + + + NVICIP59 + Interrupt Priority Register 59 + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of the INT_SAI3_TX interrupt 59 + 4 + 4 + read-write + + + + + NVICIP60 + Interrupt Priority Register 60 + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of the INT_SPDIF interrupt 60 + 4 + 4 + read-write + + + + + NVICIP61 + Interrupt Priority Register 61 + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of the INT_PMU interrupt 61 + 4 + 4 + read-write + + + + + NVICIP62 + Interrupt Priority Register 62 + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of the INT_Reserved78 interrupt 62 + 4 + 4 + read-write + + + + + NVICIP63 + Interrupt Priority Register 63 + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of the INT_TEMP_LOW_HIGH interrupt 63 + 4 + 4 + read-write + + + + + NVICIP64 + Interrupt Priority Register 64 + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of the INT_TEMP_PANIC interrupt 64 + 4 + 4 + read-write + + + + + NVICIP65 + Interrupt Priority Register 65 + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of the INT_USB_PHY interrupt 65 + 4 + 4 + read-write + + + + + NVICIP66 + Interrupt Priority Register 66 + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of the INT_Reserved82 interrupt 66 + 4 + 4 + read-write + + + + + NVICIP67 + Interrupt Priority Register 67 + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of the INT_ADC1 interrupt 67 + 4 + 4 + read-write + + + + + NVICIP68 + Interrupt Priority Register 68 + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of interrupt 68 + 4 + 4 + read-write + + + + + NVICIP69 + Interrupt Priority Register 69 + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of the INT_DCDC interrupt 69 + 4 + 4 + read-write + + + + + NVICIP70 + Interrupt Priority Register 70 + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of the INT_Reserved86 interrupt 70 + 4 + 4 + read-write + + + + + NVICIP71 + Interrupt Priority Register 71 + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of the INT_Reserved87 interrupt 71 + 4 + 4 + read-write + + + + + NVICIP72 + Interrupt Priority Register 72 + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of the INT_GPIO1_INT0 interrupt 72 + 4 + 4 + read-write + + + + + NVICIP73 + Interrupt Priority Register 73 + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of the INT_GPIO1_INT1 interrupt 73 + 4 + 4 + read-write + + + + + NVICIP74 + Interrupt Priority Register 74 + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of the INT_GPIO1_INT2 interrupt 74 + 4 + 4 + read-write + + + + + NVICIP75 + Interrupt Priority Register 75 + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of the INT_GPIO1_INT3 interrupt 75 + 4 + 4 + read-write + + + + + NVICIP76 + Interrupt Priority Register 76 + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of the INT_GPIO1_INT4 interrupt 76 + 4 + 4 + read-write + + + + + NVICIP77 + Interrupt Priority Register 77 + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of the INT_GPIO1_INT5 interrupt 77 + 4 + 4 + read-write + + + + + NVICIP78 + Interrupt Priority Register 78 + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of the INT_GPIO1_INT6 interrupt 78 + 4 + 4 + read-write + + + + + NVICIP79 + Interrupt Priority Register 79 + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of the INT_GPIO1_INT7 interrupt 79 + 4 + 4 + read-write + + + + + NVICIP80 + Interrupt Priority Register 80 + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of the INT_GPIO1_Combined_0_15 interrupt 80 + 4 + 4 + read-write + + + + + NVICIP81 + Interrupt Priority Register 81 + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of the INT_GPIO1_Combined_16_31 interrupt 81 + 4 + 4 + read-write + + + + + NVICIP82 + Interrupt Priority Register 82 + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of the INT_GPIO2_Combined_0_15 interrupt 82 + 4 + 4 + read-write + + + + + NVICIP83 + Interrupt Priority Register 83 + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of the INT_GPIO2_Combined_16_31 interrupt 83 + 4 + 4 + read-write + + + + + NVICIP84 + Interrupt Priority Register 84 + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of the INT_GPIO3_Combined_0_15 interrupt 84 + 4 + 4 + read-write + + + + + NVICIP85 + Interrupt Priority Register 85 + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of the INT_GPIO3_Combined_16_31 interrupt 85 + 4 + 4 + read-write + + + + + NVICIP86 + Interrupt Priority Register 86 + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of the INT_Reserved102 interrupt 86 + 4 + 4 + read-write + + + + + NVICIP87 + Interrupt Priority Register 87 + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of the INT_Reserved103 interrupt 87 + 4 + 4 + read-write + + + + + NVICIP88 + Interrupt Priority Register 88 + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of the INT_GPIO5_Combined_0_15 interrupt 88 + 4 + 4 + read-write + + + + + NVICIP89 + Interrupt Priority Register 89 + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of the INT_GPIO5_Combined_16_31 interrupt 89 + 4 + 4 + read-write + + + + + NVICIP90 + Interrupt Priority Register 90 + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of the INT_FLEXIO1 interrupt 90 + 4 + 4 + read-write + + + + + NVICIP91 + Interrupt Priority Register 91 + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of the INT_Reserved107 interrupt 91 + 4 + 4 + read-write + + + + + NVICIP92 + Interrupt Priority Register 92 + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of the INT_WDOG1 interrupt 92 + 4 + 4 + read-write + + + + + NVICIP93 + Interrupt Priority Register 93 + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of the INT_RTWDOG interrupt 93 + 4 + 4 + read-write + + + + + NVICIP94 + Interrupt Priority Register 94 + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of the INT_EWM interrupt 94 + 4 + 4 + read-write + + + + + NVICIP95 + Interrupt Priority Register 95 + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of the INT_CCM_1 interrupt 95 + 4 + 4 + read-write + + + + + NVICIP96 + Interrupt Priority Register 96 + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of the INT_CCM_2 interrupt 96 + 4 + 4 + read-write + + + + + NVICIP97 + Interrupt Priority Register 97 + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of the INT_GPC interrupt 97 + 4 + 4 + read-write + + + + + NVICIP98 + Interrupt Priority Register 98 + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of the INT_SRC interrupt 98 + 4 + 4 + read-write + + + + + NVICIP99 + Interrupt Priority Register 99 + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of the INT_Reserved115 interrupt 99 + 4 + 4 + read-write + + + + + NVICIP100 + Interrupt Priority Register 100 + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of the INT_GPT1 interrupt 100 + 4 + 4 + read-write + + + + + NVICIP101 + Interrupt Priority Register 101 + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of the INT_GPT2 interrupt 101 + 4 + 4 + read-write + + + + + NVICIP102 + Interrupt Priority Register 102 + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of the INT_PWM1_0 interrupt 102 + 4 + 4 + read-write + + + + + NVICIP103 + Interrupt Priority Register 103 + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of the INT_PWM1_1 interrupt 103 + 4 + 4 + read-write + + + + + NVICIP104 + Interrupt Priority Register 104 + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of the INT_PWM1_2 interrupt 104 + 4 + 4 + read-write + + + + + NVICIP105 + Interrupt Priority Register 105 + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of the INT_PWM1_3 interrupt 105 + 4 + 4 + read-write + + + + + NVICIP106 + Interrupt Priority Register 106 + 0x36A + 8 + read-write + 0 + 0xFF + + + PRI106 + Priority of the INT_PWM1_FAULT interrupt 106 + 4 + 4 + read-write + + + + + NVICIP107 + Interrupt Priority Register 107 + 0x36B + 8 + read-write + 0 + 0xFF + + + PRI107 + Priority of the INT_Reserved123 interrupt 107 + 4 + 4 + read-write + + + + + NVICIP108 + Interrupt Priority Register 108 + 0x36C + 8 + read-write + 0 + 0xFF + + + PRI108 + Priority of the INT_FLEXSPI interrupt 108 + 4 + 4 + read-write + + + + + NVICIP109 + Interrupt Priority Register 109 + 0x36D + 8 + read-write + 0 + 0xFF + + + PRI109 + Priority of interrupt 109 + 4 + 4 + read-write + + + + + NVICIP110 + Interrupt Priority Register 110 + 0x36E + 8 + read-write + 0 + 0xFF + + + PRI110 + Priority of interrupt 110 + 4 + 4 + read-write + + + + + NVICIP111 + Interrupt Priority Register 111 + 0x36F + 8 + read-write + 0 + 0xFF + + + PRI111 + Priority of interrupt 111 + 4 + 4 + read-write + + + + + NVICIP112 + Interrupt Priority Register 112 + 0x370 + 8 + read-write + 0 + 0xFF + + + PRI112 + Priority of the INT_Reserved128 interrupt 112 + 4 + 4 + read-write + + + + + NVICIP113 + Interrupt Priority Register 113 + 0x371 + 8 + read-write + 0 + 0xFF + + + PRI113 + Priority of the INT_USB_OTG1 interrupt 113 + 4 + 4 + read-write + + + + + NVICIP114 + Interrupt Priority Register 114 + 0x372 + 8 + read-write + 0 + 0xFF + + + PRI114 + Priority of interrupt 114 + 4 + 4 + read-write + + + + + NVICIP115 + Interrupt Priority Register 115 + 0x373 + 8 + read-write + 0 + 0xFF + + + PRI115 + Priority of interrupt 115 + 4 + 4 + read-write + + + + + NVICIP116 + Interrupt Priority Register 116 + 0x374 + 8 + read-write + 0 + 0xFF + + + PRI116 + Priority of the INT_XBAR1_IRQ_0_1 interrupt 116 + 4 + 4 + read-write + + + + + NVICIP117 + Interrupt Priority Register 117 + 0x375 + 8 + read-write + 0 + 0xFF + + + PRI117 + Priority of the INT_XBAR1_IRQ_2_3 interrupt 117 + 4 + 4 + read-write + + + + + NVICIP118 + Interrupt Priority Register 118 + 0x376 + 8 + read-write + 0 + 0xFF + + + PRI118 + Priority of the INT_ADC_ETC_IRQ0 interrupt 118 + 4 + 4 + read-write + + + + + NVICIP119 + Interrupt Priority Register 119 + 0x377 + 8 + read-write + 0 + 0xFF + + + PRI119 + Priority of the INT_ADC_ETC_IRQ1 interrupt 119 + 4 + 4 + read-write + + + + + NVICIP120 + Interrupt Priority Register 120 + 0x378 + 8 + read-write + 0 + 0xFF + + + PRI120 + Priority of the INT_ADC_ETC_IRQ2 interrupt 120 + 4 + 4 + read-write + + + + + NVICIP121 + Interrupt Priority Register 121 + 0x379 + 8 + read-write + 0 + 0xFF + + + PRI121 + Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 121 + 4 + 4 + read-write + + + + + NVICIP122 + Interrupt Priority Register 122 + 0x37A + 8 + read-write + 0 + 0xFF + + + PRI122 + Priority of the INT_PIT interrupt 122 + 4 + 4 + read-write + + + + + NVICIP123 + Interrupt Priority Register 123 + 0x37B + 8 + read-write + 0 + 0xFF + + + PRI123 + Priority of interrupt 123 + 4 + 4 + read-write + + + + + NVICIP124 + Interrupt Priority Register 124 + 0x37C + 8 + read-write + 0 + 0xFF + + + PRI124 + Priority of interrupt 124 + 4 + 4 + read-write + + + + + NVICIP125 + Interrupt Priority Register 125 + 0x37D + 8 + read-write + 0 + 0xFF + + + PRI125 + Priority of interrupt 125 + 4 + 4 + read-write + + + + + NVICIP126 + Interrupt Priority Register 126 + 0x37E + 8 + read-write + 0 + 0xFF + + + PRI126 + Priority of interrupt 126 + 4 + 4 + read-write + + + + + NVICIP127 + Interrupt Priority Register 127 + 0x37F + 8 + read-write + 0 + 0xFF + + + PRI127 + Priority of the INT_Reserved143 interrupt 127 + 4 + 4 + read-write + + + + + NVICIP128 + Interrupt Priority Register 128 + 0x380 + 8 + read-write + 0 + 0xFF + + + PRI128 + Priority of the INT_Reserved144 interrupt 128 + 4 + 4 + read-write + + + + + NVICIP129 + Interrupt Priority Register 129 + 0x381 + 8 + read-write + 0 + 0xFF + + + PRI129 + Priority of the INT_ENC1 interrupt 129 + 4 + 4 + read-write + + + + + NVICIP130 + Interrupt Priority Register 130 + 0x382 + 8 + read-write + 0 + 0xFF + + + PRI130 + Priority of interrupt 130 + 4 + 4 + read-write + + + + + NVICIP131 + Interrupt Priority Register 131 + 0x383 + 8 + read-write + 0 + 0xFF + + + PRI131 + Priority of the INT_Reserved147 interrupt 131 + 4 + 4 + read-write + + + + + NVICIP132 + Interrupt Priority Register 132 + 0x384 + 8 + read-write + 0 + 0xFF + + + PRI132 + Priority of the INT_Reserved148 interrupt 132 + 4 + 4 + read-write + + + + + NVICIP133 + Interrupt Priority Register 133 + 0x385 + 8 + read-write + 0 + 0xFF + + + PRI133 + Priority of the INT_TMR1 interrupt 133 + 4 + 4 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + + + \ No newline at end of file diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015_features.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015_features.h new file mode 100644 index 0000000000000..dee8407c9926d --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015_features.h @@ -0,0 +1,504 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-02-20 +** Build: b190221 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2018-11-05) +** Initial version. +** - rev. 1.0 (2019-01-18) +** Rev.0 Header GA +** - rev. 1.1 (2019-02-20) +** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP. +** +** ################################################################### +*/ + +#ifndef _MIMXRT1015_FEATURES_H_ +#define _MIMXRT1015_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (1) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (4) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (2) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (4) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (1) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (1) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (1) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (1) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* @brief Conversion control count (related to number of registers HCn and Rn). */ +#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) + +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief Channel IRQ entry shared offset. */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ +#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) + +/* FLEXRAM module features */ + +/* @brief Bank size */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) +/* @brief Total Bank numbers */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) + +/* GPC module features */ + +/* @brief Has DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) +/* @brief Has GPC interrupt/event masking. */ +#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) +/* @brief Has L2 cache power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) +/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) +/* @brief Has VADC power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) +/* @brief Has Display power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) +/* @brief Supports IRQ 0-31. */ +#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (133) + +/* OCOTP module features */ + +/* No feature definitions */ + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PWM module features */ + +/* @brief Number of each EflexPWM module channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U) +/* @brief Number of EflexPWM module A channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U) +/* @brief Number of EflexPWM module B channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U) +/* @brief Number of EflexPWM module X channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U) +/* @brief Number of each EflexPWM module compare channels interrupts. */ +#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module reload channels interrupts. */ +#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module capture channels interrupts. */ +#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module reload error channels interrupts. */ +#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module fault channels interrupts. */ +#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U) +/* @brief Number of submodules in each EflexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) + +/* RTWDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) +/* @brief RTWDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == SAI1) ? (4) : \ + (((x) == SAI2) ? (1) : \ + (((x) == SAI3) ? (1) : (-1)))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is LOCKUP_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is no WRBC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) +/* @brief There is no WRE bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (0) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is JTAG_SW_RST bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (1) +/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (0) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) +/* @brief There is no WBI bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) + +/* SCB module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* TRNG module features */ + +/* @brief TRNG has no TRNG_ACC bitfield. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (0) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* XBARA module features */ + +/* @brief Number of interrupt requests. */ +#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) + +#endif /* _MIMXRT1015_FEATURES_H_ */ + diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.c b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.c new file mode 100644 index 0000000000000..604c06b205f45 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.c @@ -0,0 +1,907 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if ((defined(__ICCARM__)) || (defined(__GNUC__))) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +volatile uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +volatile uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL3 PFD3 */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + + /* PLL2 PFD3 */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + + /* PLL6 divided(/1) */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = 500000000U; + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + else + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; +} + +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the PER clock frequency. + * + * return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetFreq(kCLOCK_IpgClk); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + + case kCLOCK_SemcClk: + freq = CLOCK_GetSemcFreq(); + break; + + case kCLOCK_IpgClk: + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll500MClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet500M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY->PWD = 0; + USBPHY->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +/*! + * brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = 0; + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput500M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)) | enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + clock_64b_t freqTmp; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllEnet500M: + /* PLL6 is fixed at 25MHz. */ + freq = 500000000UL; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.h new file mode 100644 index 0000000000000..caedbbbf01fd7 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.h @@ -0,0 +1,1286 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.1.6. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_ENET_OFFSET 0xE0 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_Aoi \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1 \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_IpInvalid, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + { \ + kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \ + } \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_Xbar2 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_SysPllClk = 0xCU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xDU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0xEU, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0xFU, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x10U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPllClk = 0x11U, /*!< Enet PLLCLK ref_enetpll. */ + kCLOCK_EnetPll25MClk = 0x12U, /*!< Enet PLLCLK ref_enetpll25M. */ + kCLOCK_EnetPll500MClk = 0x13U, /*!< Enet PLLCLK ref_enetpll500M. */ + + kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2, Reserved */ + kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + /*!< CCGR1, CG7, Reserved */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + /*!< CCGR2, CG1, Reserved */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + /*!< CCGR2, CG7, Reserved */ + /*!< CCGR2, CG8, Reserved */ + /*!< CCGR2, CG9, Reserved */ + /*!< CCGR2, CG10, Reserved */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + /*!< CCGR2, CG14, Reserved */ + /*!< CCGR2, CG15, Reserved */ + + /* CCM CCGR3 */ + /*!< CCGR3, CG0, Reserved */ + kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + /*!< CCGR3, CG5, Reserved */ + /*!< CCGR3, CG6, Reserved */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + /*!< CCGR3, CG14, Reserved */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + /*!< CCGR4, CG10, Reserved */ + /*!< CCGR4, CG11, Reserved */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + /*!< CCGR4, CG14, Reserved */ + /*!< CCGR4, CG15, Reserved */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + /*!< CCGR5, CG8, Reserved */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + /*!< CCGR6, CG15, Reserved */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_TRACE_CLK_SEL_SHIFT, + CCM_CBCMR_TRACE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, + CCM_CBCMR_LPSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI3_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_SEL_SHIFT, + CCM_CSCDR1_UART_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, + CCM_CDCDR_SPDIF0_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, + CCM_CSCDR2_LPI2C_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET, + CCM_CACRR_ARM_PODF_SHIFT, + CCM_CACRR_ARM_PODF_MASK, + CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_AHB_PODF_SHIFT, + CCM_CBCDR_AHB_PODF_MASK, + CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE( + CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_PODF_SHIFT, + CCM_CSCMR1_FLEXSPI_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_PODF_SHIFT, + CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_TRACE_PODF_SHIFT, + CCM_CSCDR1_TRACE_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_PODF_SHIFT, + CCM_CSCDR1_UART_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI3_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, + CCM_CS2CDR_SAI2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ + +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + + bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */ + + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */ +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 6); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_device_registers.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_device_registers.h new file mode 100644 index 0000000000000..49f3013f6eea0 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_device_registers.h @@ -0,0 +1,35 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1015CAF4A) || defined(CPU_MIMXRT1015DAF5A)) + +#define MIMXRT1015_SERIES + +/* CMSIS-style register definitions */ +#include "MIMXRT1015.h" +/* CPU specific feature definitions */ +#include "MIMXRT1015_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_iomuxc.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_iomuxc.h new file mode 100644 index 0000000000000..15bb775136000 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_iomuxc.h @@ -0,0 +1,565 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_04_XBAR1_XBAR_INOUT04 0x401F8024U, 0x1U, 0, 0, 0x401F8198U +#define IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x401F8024U, 0x2U, 0, 0, 0x401F8198U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x401F8024U, 0x3U, 0x401F8464U, 0x1U, 0x401F8198U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x401F8024U, 0x4U, 0, 0, 0x401F8198U +#define IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8198U +#define IOMUXC_GPIO_EMC_04_SJC_JTAG_ACT 0x401F8024U, 0x7U, 0, 0, 0x401F8198U + +#define IOMUXC_GPIO_EMC_05_XBAR1_XBAR_INOUT05 0x401F8028U, 0x1U, 0, 0, 0x401F819CU +#define IOMUXC_GPIO_EMC_05_SPDIF_IN 0x401F8028U, 0x2U, 0x401F8488U, 0x0U, 0x401F819CU +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x3U, 0x401F8468U, 0x1U, 0x401F819CU +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x401F8028U, 0x4U, 0, 0, 0x401F819CU +#define IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F819CU +#define IOMUXC_GPIO_EMC_05_SJC_DE_B 0x401F8028U, 0x7U, 0, 0, 0x401F819CU + +#define IOMUXC_GPIO_EMC_06_XBAR1_XBAR_INOUT06 0x401F802CU, 0x1U, 0, 0, 0x401F81A0U +#define IOMUXC_GPIO_EMC_06_LPUART3_TX 0x401F802CU, 0x2U, 0x401F83DCU, 0x0U, 0x401F81A0U +#define IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x401F802CU, 0x3U, 0, 0, 0x401F81A0U +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x401F802CU, 0x4U, 0, 0, 0x401F81A0U +#define IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F81A0U + +#define IOMUXC_GPIO_EMC_07_XBAR1_XBAR_INOUT07 0x401F8030U, 0x1U, 0, 0, 0x401F81A4U +#define IOMUXC_GPIO_EMC_07_LPUART3_RX 0x401F8030U, 0x2U, 0x401F83D8U, 0x0U, 0x401F81A4U +#define IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x401F8030U, 0x3U, 0x401F8460U, 0x1U, 0x401F81A4U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x401F8030U, 0x4U, 0, 0, 0x401F81A4U +#define IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F81A4U + +#define IOMUXC_GPIO_EMC_08_XBAR1_XBAR_INOUT08 0x401F8034U, 0x1U, 0, 0, 0x401F81A8U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x3U, 0x401F845CU, 0x1U, 0x401F81A8U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x401F8034U, 0x4U, 0, 0, 0x401F81A8U +#define IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F81A8U + +#define IOMUXC_GPIO_EMC_09_XBAR1_XBAR_INOUT09 0x401F8038U, 0x1U, 0, 0, 0x401F81ACU +#define IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x401F8038U, 0x3U, 0x401F8458U, 0x1U, 0x401F81ACU +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x401F8038U, 0x4U, 0, 0, 0x401F81ACU +#define IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F81ACU + +#define IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x401F8054U, 0x2U, 0, 0, 0x401F81C8U +#define IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x401F8054U, 0x3U, 0x401F8454U, 0x1U, 0x401F81C8U +#define IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F81C8U +#define IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x401F8054U, 0x6U, 0, 0, 0x401F81C8U + +#define IOMUXC_GPIO_EMC_17_MQS_LEFT 0x401F8058U, 0x2U, 0, 0, 0x401F81CCU +#define IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x401F8058U, 0x3U, 0x401F846CU, 0x1U, 0x401F81CCU +#define IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F81CCU +#define IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x401F8058U, 0x6U, 0, 0, 0x401F81CCU + +#define IOMUXC_GPIO_EMC_18_XBAR1_XBAR_INOUT16 0x401F805CU, 0x1U, 0x401F84A8U, 0x1U, 0x401F81D0U +#define IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x401F805CU, 0x2U, 0x401F8388U, 0x1U, 0x401F81D0U +#define IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x401F805CU, 0x3U, 0x401F8448U, 0x2U, 0x401F81D0U +#define IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x401F805CU, 0x4U, 0, 0, 0x401F81D0U +#define IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F81D0U +#define IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x401F805CU, 0x6U, 0, 0, 0x401F81D0U + +#define IOMUXC_GPIO_EMC_19_XBAR1_XBAR_INOUT17 0x401F8060U, 0x1U, 0x401F84ACU, 0x1U, 0x401F81D4U +#define IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x401F8060U, 0x2U, 0x401F8384U, 0x1U, 0x401F81D4U +#define IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x401F8060U, 0x3U, 0x401F8434U, 0x2U, 0x401F81D4U +#define IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x401F8060U, 0x4U, 0, 0, 0x401F81D4U +#define IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F81D4U +#define IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x401F8060U, 0x6U, 0, 0, 0x401F81D4U + +#define IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x401F8064U, 0x1U, 0x401F8334U, 0x1U, 0x401F81D8U +#define IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x401F8064U, 0x2U, 0x401F83CCU, 0x1U, 0x401F81D8U +#define IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x401F8064U, 0x3U, 0x401F8430U, 0x3U, 0x401F81D8U +#define IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x401F8064U, 0x4U, 0, 0, 0x401F81D8U +#define IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F81D8U +#define IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x401F8064U, 0x6U, 0, 0, 0x401F81D8U + +#define IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x401F8068U, 0x1U, 0x401F8344U, 0x1U, 0x401F81DCU +#define IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x401F8068U, 0x2U, 0, 0, 0x401F81DCU +#define IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x401F8068U, 0x3U, 0x401F8438U, 0x2U, 0x401F81DCU +#define IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x401F8068U, 0x4U, 0, 0, 0x401F81DCU +#define IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F81DCU +#define IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x401F8068U, 0x6U, 0, 0, 0x401F81DCU + +#define IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x401F806CU, 0x1U, 0x401F8330U, 0x1U, 0x401F81E0U +#define IOMUXC_GPIO_EMC_22_LPUART2_TX 0x401F806CU, 0x2U, 0x401F83D4U, 0x1U, 0x401F81E0U +#define IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x401F806CU, 0x3U, 0x401F843CU, 0x1U, 0x401F81E0U +#define IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x401F806CU, 0x4U, 0, 0, 0x401F81E0U +#define IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F81E0U +#define IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x401F806CU, 0x6U, 0, 0, 0x401F81E0U + +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x401F8070U, 0x1U, 0x401F8340U, 0x1U, 0x401F81E4U +#define IOMUXC_GPIO_EMC_23_LPUART2_RX 0x401F8070U, 0x2U, 0x401F83D0U, 0x1U, 0x401F81E4U +#define IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x401F8070U, 0x3U, 0x401F8440U, 0x1U, 0x401F81E4U +#define IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x401F8070U, 0x4U, 0, 0, 0x401F81E4U +#define IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F81E4U +#define IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x401F8070U, 0x6U, 0, 0, 0x401F81E4U + +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x401F8074U, 0x1U, 0x401F832CU, 0x1U, 0x401F81E8U +#define IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x401F8074U, 0x3U, 0x401F8444U, 0x1U, 0x401F81E8U +#define IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x401F8074U, 0x4U, 0, 0, 0x401F81E8U +#define IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F81E8U +#define IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x401F8074U, 0x6U, 0, 0, 0x401F81E8U + +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x401F8078U, 0x1U, 0x401F833CU, 0x1U, 0x401F81ECU +#define IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x401F8078U, 0x3U, 0, 0, 0x401F81ECU +#define IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x401F8078U, 0x4U, 0, 0, 0x401F81ECU +#define IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F81ECU +#define IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x401F8078U, 0x6U, 0, 0, 0x401F81ECU + +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x401F807CU, 0x1U, 0x401F8328U, 0x1U, 0x401F81F0U +#define IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x401F807CU, 0x3U, 0x401F844CU, 0x2U, 0x401F81F0U +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x401F807CU, 0x4U, 0, 0, 0x401F81F0U +#define IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F81F0U +#define IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x401F807CU, 0x6U, 0, 0, 0x401F81F0U + +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x401F8080U, 0x1U, 0x401F8338U, 0x1U, 0x401F81F4U +#define IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x401F8080U, 0x3U, 0x401F8450U, 0x2U, 0x401F81F4U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x401F8080U, 0x4U, 0, 0, 0x401F81F4U +#define IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F81F4U +#define IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x401F8080U, 0x6U, 0, 0, 0x401F81F4U + +#define IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x401F8094U, 0x1U, 0x401F8410U, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_32_LPUART4_TX 0x401F8094U, 0x2U, 0x401F83E8U, 0x2U, 0x401F8208U +#define IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x401F8094U, 0x3U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x401F8094U, 0x5U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x401F8094U, 0x7U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x401F8098U, 0x1U, 0x401F8414U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_33_LPUART4_RX 0x401F8098U, 0x2U, 0x401F83E4U, 0x2U, 0x401F820CU +#define IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x401F8098U, 0x3U, 0x401F847CU, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x401F8098U, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x401F809CU, 0x1U, 0x401F8418U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x401F809CU, 0x3U, 0x401F8480U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x401F809CU, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x401F80A0U, 0x1U, 0x401F841CU, 0x1U, 0x401F8214U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x401F80A0U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_AD_B0_00_JTAG_MUX_TMS 0x401F80BCU, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x401F80BCU, 0x7U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_AD_B0_01_JTAG_MUX_TCK 0x401F80C0U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x401F80C0U, 0x7U, 0, 0, 0x401F8234U + +#define IOMUXC_GPIO_AD_B0_02_JTAG_MUX_MOD 0x401F80C4U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x401F80C4U, 0x7U, 0, 0, 0x401F8238U + +#define IOMUXC_GPIO_AD_B0_03_JTAG_MUX_TDI 0x401F80C8U, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_AD_B0_03_WDOG1_WDOG_B 0x401F80C8U, 0x2U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x401F80C8U, 0x3U, 0x401F8430U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x6U, 0x401F848CU, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x401F80C8U, 0x7U, 0x401F8300U, 0x2U, 0x401F823CU + +#define IOMUXC_GPIO_AD_B0_04_JTAG_MUX_TDO 0x401F80CCU, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x401F80CCU, 0x6U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_AD_B0_04_EWM_EWM_OUT_B 0x401F80CCU, 0x7U, 0, 0, 0x401F8240U + +#define IOMUXC_GPIO_AD_B0_05_JTAG_MUX_TRSTB 0x401F80D0U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x401F80D0U, 0x6U, 0x401F82FCU, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x401F80D0U, 0x7U, 0x401F840CU, 0x0U, 0x401F8244U + +#define IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x401F80D4U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x401F80D4U, 0x1U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x401F80D4U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x401F80D4U, 0x6U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x401F80D8U, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x401F80D8U, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x401F80D8U, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x401F80D8U, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x401F80DCU, 0x2U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x401F80DCU, 0x3U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x401F80DCU, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x401F80E0U, 0x2U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x401F80E0U, 0x3U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_AD_B0_09_CSU_CSU_INT_DEB 0x401F80E0U, 0x4U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x401F80E0U, 0x6U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x401F80E4U, 0x1U, 0x401F83A0U, 0x1U, 0x401F8258U +#define IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x401F80E4U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x401F80E8U, 0x1U, 0x401F839CU, 0x1U, 0x401F825CU +#define IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x401F80E8U, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x401F80ECU, 0x1U, 0x401F83A8U, 0x1U, 0x401F8260U +#define IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x401F80ECU, 0x2U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x401F80ECU, 0x3U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x401F80ECU, 0x7U, 0, 0, 0x401F8260U + +#define IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x401F80F0U, 0x1U, 0x401F83A4U, 0x1U, 0x401F8264U +#define IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x401F80F0U, 0x2U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x401F80F0U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x401F80F0U, 0x7U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x401F80F4U, 0x2U, 0x401F83DCU, 0x1U, 0x401F8268U +#define IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x401F80F4U, 0x3U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_AD_B0_14_WDOG1_WDOG_ANY 0x401F80F4U, 0x7U, 0, 0, 0x401F8268U + +#define IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x401F80F8U, 0x2U, 0x401F83D8U, 0x1U, 0x401F826CU +#define IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x401F80F8U, 0x3U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F826CU + +#define IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x401F8124U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x401F8124U, 0x1U, 0x401F8330U, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x401F8124U, 0x2U, 0x401F83E8U, 0x1U, 0x401F8298U +#define IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x401F8124U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x401F8124U, 0x6U, 0, 0, 0x401F8298U + +#define IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x401F8128U, 0x0U, 0x401F82FCU, 0x1U, 0x401F829CU +#define IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x401F8128U, 0x1U, 0x401F8340U, 0x0U, 0x401F829CU +#define IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x401F8128U, 0x2U, 0x401F83E4U, 0x1U, 0x401F829CU +#define IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x401F8128U, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x401F8128U, 0x6U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x401F812CU, 0x0U, 0x401F848CU, 0x1U, 0x401F82A0U +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x401F812CU, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x401F812CU, 0x6U, 0x401F8334U, 0x0U, 0x401F82A0U + +#define IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x401F8130U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x401F8130U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x401F8130U, 0x6U, 0x401F8344U, 0x0U, 0x401F82A4U + +#define IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x401F8134U, 0x0U, 0x401F837CU, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x401F8134U, 0x4U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x401F8138U, 0x0U, 0x401F8380U, 0x1U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x401F8138U, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B1_15_CCM_DI0_EXT_CLK 0x401F8138U, 0x6U, 0, 0, 0x401F82ACU + +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x401F8158U, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_SD_B1_00_XBAR1_XBAR_INOUT10 0x401F8158U, 0x3U, 0x401F84B0U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x401F8158U, 0x5U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x401F815CU, 0x1U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x401F815CU, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x401F815CU, 0x5U, 0, 0, 0x401F82D0U + +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x401F8160U, 0x1U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x401F8160U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x401F8160U, 0x6U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x401F8164U, 0x1U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x401F8164U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x401F8164U, 0x6U, 0, 0, 0x401F82D8U + +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x401F8168U, 0x1U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_SD_B1_04_EWM_EWM_OUT_B 0x401F8168U, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x401F8168U, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x401F8168U, 0x6U, 0, 0, 0x401F82DCU + +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x401F816CU, 0x1U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x401F816CU, 0x3U, 0x401F846CU, 0x0U, 0x401F82E0U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x401F816CU, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x401F816CU, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x401F816CU, 0x6U, 0x401F8300U, 0x1U, 0x401F82E0U + +#define IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x401F8170U, 0x1U, 0x401F8374U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x401F8170U, 0x3U, 0x401F847CU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F8170U, 0x4U, 0x401F83ACU, 0x2U, 0x401F82E4U +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x401F8170U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x401F8170U, 0x6U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x401F8174U, 0x1U, 0x401F8378U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x401F8174U, 0x3U, 0x401F8480U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F8174U, 0x4U, 0x401F83B0U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x401F8174U, 0x5U, 0, 0, 0x401F82E8U + +#define IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x401F8178U, 0x1U, 0x401F8368U, 0x0U, 0x401F82ECU +#define IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x401F8178U, 0x3U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x401F8178U, 0x4U, 0x401F83B8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x401F8178U, 0x5U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x401F817CU, 0x1U, 0x401F8370U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x401F817CU, 0x3U, 0x401F8470U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F817CU, 0x4U, 0x401F83B4U, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x401F817CU, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_SD_B1_09_CCM_REF_EN_B 0x401F817CU, 0x6U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x401F8180U, 0x1U, 0x401F836CU, 0x0U, 0x401F82F4U +#define IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x401F8180U, 0x3U, 0x401F8478U, 0x0U, 0x401F82F4U +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F8180U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x401F8180U, 0x5U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x401F8184U, 0x1U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x401F8184U, 0x3U, 0x401F8474U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8184U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x401F8184U, 0x5U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ + diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.c b/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.c new file mode 100644 index 0000000000000..a0741cd5c3811 --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.c @@ -0,0 +1,217 @@ +/* +** ################################################################### +** Processors: MIMXRT1015CAF4A +** MIMXRT1015DAF5A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1015RM Rev.0, 12/2018 +** Version: rev. 1.1, 2019-02-20 +** Build: b190220 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2018-11-05) +** Initial version. +** - rev. 1.0 (2019-01-18) +** Rev.0 Header GA +** - rev. 1.1 (2019-02-20) +** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1015 + * @version 1.1 + * @date 2019-02-20 + * @brief Device specific configuration file for MIMXRT1015 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + +/* Watchdog disable */ + +#if (DISABLE_WDOG) + if (WDOG1->WCR & WDOG_WCR_WDE_MASK) + { + WDOG1->WCR &= ~WDOG_WCR_WDE_MASK; + } + if (WDOG2->WCR & WDOG_WCR_WDE_MASK) + { + WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; + } + RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ + RTWDOG->TOVAL = 0xFFFF; + RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; +#endif /* (DISABLE_WDOG) */ + + /* Disable Systick which might be enabled by bootrom */ + if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) + { + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + +/* Enable instruction and data caches */ +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } +#endif +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } +#endif + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t freq; + uint32_t PLL2MainClock; + uint32_t PLL3MainClock; + + /* Check if system pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = CPU_XTAL_CLK_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + /* Check if usb1 pll is bypassed */ + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + PLL3MainClock = CPU_XTAL_CLK_HZ; + } + else + { + PLL3MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = PLL3MainClock; + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CPU_XTAL_CLK_HZ; + break; + + /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CPU_XTAL_CLK_HZ; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = PLL2MainClock; + break; + + /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U; + break; + + /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U; + break; + + /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = 500000000U / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.h b/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.h new file mode 100644 index 0000000000000..c95258a7d343f --- /dev/null +++ b/ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.h @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: MIMXRT1015CAF4A +** MIMXRT1015DAF5A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1015RM Rev.0, 12/2018 +** Version: rev. 1.1, 2019-02-20 +** Build: b190220 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2018-11-05) +** Initial version. +** - rev. 1.0 (2019-01-18) +** Rev.0 Header GA +** - rev. 1.1 (2019-02-20) +** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1015 + * @version 1.1 + * @date 2019-02-20 + * @brief Device specific configuration file for MIMXRT1015 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMXRT1015_H_ +#define _SYSTEM_MIMXRT1015_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ + +#define DEFAULT_SYSTEM_CLOCK 297000000UL /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMXRT1015_H_ */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c index f8eb336c49872..b2fa29b718519 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.c @@ -147,16 +147,16 @@ void ADC_GetDefaultConfig(adc_config_t *config) memset(config, 0, sizeof(*config)); config->enableAsynchronousClockOutput = true; - config->enableOverWrite = false; - config->enableContinuousConversion = false; - config->enableHighSpeed = false; - config->enableLowPower = false; - config->enableLongSample = false; - config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; - config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; - config->clockSource = kADC_ClockSourceAD; - config->clockDriver = kADC_ClockDriver1; - config->resolution = kADC_Resolution12Bit; + config->enableOverWrite = false; + config->enableContinuousConversion = false; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableLongSample = false; + config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + config->clockSource = kADC_ClockSourceAD; + config->clockDriver = kADC_ClockDriver1; + config->resolution = kADC_Resolution12Bit; } /*! @@ -189,7 +189,7 @@ void ADC_GetDefaultConfig(adc_config_t *config) void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) { assert(NULL != config); - assert(channelGroup < ADC_HC_COUNT); + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); uint32_t tmp32; @@ -341,7 +341,7 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con base->GC = tmp32; /* Load the compare values. */ - tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); + tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); base->CV = tmp32; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.h index 99429e60981ff..645e22e3f633a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc.h @@ -17,20 +17,20 @@ */ /******************************************************************************* -* Definitions -******************************************************************************/ + * Definitions + ******************************************************************************/ /*! @brief ADC driver version */ -#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ /*! * @brief Converter's status flags. */ typedef enum _adc_status_flags { - kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ - kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ + kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ + kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ kADC_AsynchronousWakeupInterruptFlag = - ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */ } adc_status_flags_t; /*! @@ -69,7 +69,7 @@ typedef enum _adc_sample_period_mode */ typedef enum _adc_clock_source { - kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ + kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */ #if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */ @@ -93,7 +93,7 @@ typedef enum _adc_clock_drvier */ typedef enum _adc_resolution { - kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ + kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */ kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */ } adc_resolution_t; @@ -120,10 +120,10 @@ typedef enum _adc_hardware_compare_mode */ typedef enum _adc_hardware_average_mode { - kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ - kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ - kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ - kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */ } adc_hardware_average_mode_t; @@ -188,8 +188,8 @@ typedef struct _adc_channel_config bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ } adc_channel_config_t; /******************************************************************************* -* API -******************************************************************************/ + * API + ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif @@ -275,7 +275,7 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann */ static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) { - assert(channelGroup < ADC_R_COUNT); + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); return base->R[channelGroup]; } @@ -299,7 +299,7 @@ static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t ch */ static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) { - assert(channelGroup < ADC_HC_COUNT); + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); /* If flag is set,return 1,otherwise, return 0. */ return (((base->HS) & (1U << channelGroup)) >> channelGroup); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c index 4a81c9fd9fc40..cdd5db1f9dd30 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c @@ -39,7 +39,7 @@ static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS; ******************************************************************************/ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) { - uint32_t instance = 0U; + uint32_t instance = 0U; uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0])); /* Find the instance index from base address mappings. */ @@ -56,11 +56,11 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) #endif /* ADC_ETC_CLOCKS */ /*! -* brief Initialize the ADC_ETC module. -* -* param base ADC_ETC peripheral base address. -* param config Pointer to "adc_etc_config_t" structure. -*/ + * brief Initialize the ADC_ETC module. + * + * param base ADC_ETC peripheral base address. + * param config Pointer to "adc_etc_config_t" structure. + */ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) { assert(NULL != config); @@ -101,10 +101,10 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) } /*! -* brief De-Initialize the ADC_ETC module. -* -* param base ADC_ETC peripheral base address. -*/ + * brief De-Initialize the ADC_ETC module. + * + * param base ADC_ETC peripheral base address. + */ void ADC_ETC_Deinit(ADC_ETC_Type *base) { /* Do software reset to clear all logical. */ @@ -119,26 +119,26 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base) } /*! -* brief Gets an available pre-defined settings for the ADC_ETC's configuration. -* This function initializes the ADC_ETC's configuration structure with available settings. The default values are: -* code -* config->enableTSCBypass = true; -* config->enableTSC0Trigger = false; -* config->enableTSC1Trigger = false; -* config->TSC0triggerPriority = 0U; -* config->TSC1triggerPriority = 0U; -* config->clockPreDivider = 0U; -* config->XBARtriggerMask = 0U; -* endCode -* -* param config Pointer to "adc_etc_config_t" structure. -*/ + * brief Gets an available pre-defined settings for the ADC_ETC's configuration. + * This function initializes the ADC_ETC's configuration structure with available settings. The default values are: + * code + * config->enableTSCBypass = true; + * config->enableTSC0Trigger = false; + * config->enableTSC1Trigger = false; + * config->TSC0triggerPriority = 0U; + * config->TSC1triggerPriority = 0U; + * config->clockPreDivider = 0U; + * config->XBARtriggerMask = 0U; + * endCode + * + * param config Pointer to "adc_etc_config_t" structure. + */ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) { /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableTSCBypass = true; + config->enableTSCBypass = true; config->enableTSC0Trigger = false; config->enableTSC1Trigger = false; #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL @@ -146,17 +146,17 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ config->TSC0triggerPriority = 0U; config->TSC1triggerPriority = 0U; - config->clockPreDivider = 0U; - config->XBARtriggerMask = 0U; + config->clockPreDivider = 0U; + config->XBARtriggerMask = 0U; } /*! -* brief Set the external XBAR trigger configuration. -* -* param base ADC_ETC peripheral base address. -* param triggerGroup Trigger group index. -* param config Pointer to "adc_etc_trigger_config_t" structure. -*/ + * brief Set the external XBAR trigger configuration. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. + * param config Pointer to "adc_etc_trigger_config_t" structure. + */ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config) { assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); @@ -184,15 +184,15 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a } /*! -* brief Set the external XBAR trigger chain configuration. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be -* configurated. -* -* param base ADC_ETC peripheral base address. -* param triggerGroup Trigger group index. Available number is 0~7. -* param chainGroup Trigger chain group index. Available number is 0~7. -* param config Pointer to "adc_etc_trigger_chain_config_t" structure. -*/ + * brief Set the external XBAR trigger chain configuration. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be + * configurated. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. Available number is 0~7. + * param chainGroup Trigger chain group index. Available number is 0~7. + * param config Pointer to "adc_etc_trigger_chain_config_t" structure. + */ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup, @@ -284,13 +284,13 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, } /*! -* brief Gets the interrupt status flags of external XBAR and TSC triggers. -* -* param base ADC_ETC peripheral base address. -* param sourceIndex trigger source index. -* -* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ + * brief Gets the interrupt status flags of external XBAR and TSC triggers. + * + * param base ADC_ETC peripheral base address. + * param sourceIndex trigger source index. + * + * return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex) { uint32_t tmp32 = 0U; @@ -319,12 +319,12 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr } /*! -* brief Clears the ADC_ETC's interrupt status falgs. -* -* param base ADC_ETC peripheral base address. -* param sourceIndex trigger source index. -* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ + * brief Clears the ADC_ETC's interrupt status falgs. + * + * param base ADC_ETC peripheral base address. + * param sourceIndex trigger source index. + * param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask) { if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */ @@ -346,15 +346,15 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig } /*! -* brief Get ADC conversion result from external XBAR sources. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would -* return Trigger0 source's chain1 conversion result. -* -* param base ADC_ETC peripheral base address. -* param triggerGroup Trigger group index. Available number is 0~7. -* param chainGroup Trigger chain group index. Available number is 0~7. -* return ADC conversion result value. -*/ + * brief Get ADC conversion result from external XBAR sources. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would + * return Trigger0 source's chain1 conversion result. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. Available number is 0~7. + * param chainGroup Trigger chain group index. Available number is 0~7. + * return ADC conversion result value. + */ uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup) { assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.h index cdcd7b7d4fefb..4b43f1aa1572b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.h @@ -17,16 +17,16 @@ */ /******************************************************************************* -* Definitions -******************************************************************************/ + * Definitions + ******************************************************************************/ /*! @brief ADC_ETC driver version */ #define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ /*! @brief The mask of status flags cleared by writing 1. */ #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U /*! -* @brief ADC_ETC customized status flags mask. -*/ + * @brief ADC_ETC customized status flags mask. + */ enum _adc_etc_status_flag_mask { kADC_ETC_Done0StatusFlagMask = 1U, @@ -36,8 +36,8 @@ enum _adc_etc_status_flag_mask }; /*! -* @brief External triggers sources. -*/ + * @brief External triggers sources. + */ typedef enum _adc_etc_external_trigger_source { /* External XBAR sources. Support HW or SW mode. */ @@ -55,11 +55,11 @@ typedef enum _adc_etc_external_trigger_source } adc_etc_external_trigger_source_t; /*! -* @brief Interrupt enable/disable mask. -*/ + * @brief Interrupt enable/disable mask. + */ typedef enum _adc_etc_interrupt_enable { - kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */ + kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */ kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */ kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */ kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */ @@ -67,8 +67,8 @@ typedef enum _adc_etc_interrupt_enable #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL /*! -* @brief DMA mode selection. -*/ + * @brief DMA mode selection. + */ typedef enum _adc_etc_dma_mode_selection { kADC_ETC_TrigDMAWithLatchedSignal = @@ -100,8 +100,8 @@ typedef struct _adc_etc_config } adc_etc_config_t; /*! -* @brief ADC_ETC trigger chain configuration. -*/ + * @brief ADC_ETC trigger chain configuration. + */ typedef struct _adc_etc_trigger_chain_config { bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode, @@ -112,8 +112,8 @@ typedef struct _adc_etc_trigger_chain_config } adc_etc_trigger_chain_config_t; /*! -* @brief ADC_ETC trigger configuration. -*/ + * @brief ADC_ETC trigger configuration. + */ typedef struct _adc_etc_trigger_config { bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source. @@ -126,8 +126,8 @@ typedef struct _adc_etc_trigger_config } adc_etc_trigger_config_t; /******************************************************************************* -* API -******************************************************************************/ + * API + ******************************************************************************/ #if defined(__cplusplus) extern "C" { #endif @@ -138,88 +138,88 @@ extern "C" { */ /*! -* @brief Initialize the ADC_ETC module. -* -* @param base ADC_ETC peripheral base address. -* @param config Pointer to "adc_etc_config_t" structure. -*/ + * @brief Initialize the ADC_ETC module. + * + * @param base ADC_ETC peripheral base address. + * @param config Pointer to "adc_etc_config_t" structure. + */ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config); /*! -* @brief De-Initialize the ADC_ETC module. -* -* @param base ADC_ETC peripheral base address. -*/ + * @brief De-Initialize the ADC_ETC module. + * + * @param base ADC_ETC peripheral base address. + */ void ADC_ETC_Deinit(ADC_ETC_Type *base); /*! -* @brief Gets an available pre-defined settings for the ADC_ETC's configuration. -* This function initializes the ADC_ETC's configuration structure with available settings. The default values are: -* @code -* config->enableTSCBypass = true; -* config->enableTSC0Trigger = false; -* config->enableTSC1Trigger = false; -* config->TSC0triggerPriority = 0U; -* config->TSC1triggerPriority = 0U; -* config->clockPreDivider = 0U; -* config->XBARtriggerMask = 0U; -* @endCode -* -* @param config Pointer to "adc_etc_config_t" structure. -*/ + * @brief Gets an available pre-defined settings for the ADC_ETC's configuration. + * This function initializes the ADC_ETC's configuration structure with available settings. The default values are: + * @code + * config->enableTSCBypass = true; + * config->enableTSC0Trigger = false; + * config->enableTSC1Trigger = false; + * config->TSC0triggerPriority = 0U; + * config->TSC1triggerPriority = 0U; + * config->clockPreDivider = 0U; + * config->XBARtriggerMask = 0U; + * @endCode + * + * @param config Pointer to "adc_etc_config_t" structure. + */ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config); /*! -* @brief Set the external XBAR trigger configuration. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. -* @param config Pointer to "adc_etc_trigger_config_t" structure. -*/ + * @brief Set the external XBAR trigger configuration. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. + * @param config Pointer to "adc_etc_trigger_config_t" structure. + */ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config); /*! -* @brief Set the external XBAR trigger chain configuration. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be -* configurated. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -* @param chainGroup Trigger chain group index. Available number is 0~7. -* @param config Pointer to "adc_etc_trigger_chain_config_t" structure. -*/ + * @brief Set the external XBAR trigger chain configuration. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be + * configurated. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + * @param chainGroup Trigger chain group index. Available number is 0~7. + * @param config Pointer to "adc_etc_trigger_chain_config_t" structure. + */ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup, const adc_etc_trigger_chain_config_t *config); /*! -* @brief Gets the interrupt status flags of external XBAR and TSC triggers. -* -* @param base ADC_ETC peripheral base address. -* @param sourceIndex trigger source index. -* -* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ + * @brief Gets the interrupt status flags of external XBAR and TSC triggers. + * + * @param base ADC_ETC peripheral base address. + * @param sourceIndex trigger source index. + * + * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex); /*! -* @brief Clears the ADC_ETC's interrupt status falgs. -* -* @param base ADC_ETC peripheral base address. -* @param sourceIndex trigger source index. -* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". -*/ + * @brief Clears the ADC_ETC's interrupt status falgs. + * + * @param base ADC_ETC peripheral base address. + * @param sourceIndex trigger source index. + * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask); /*! -* @brief Enable the DMA corresponding to each trigger source. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ + * @brief Enable the DMA corresponding to each trigger source. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) { /* Avoid clearing status flags at the same time. */ @@ -228,11 +228,11 @@ static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) } /*! -* @brief Disable the DMA corresponding to each trigger sources. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ + * @brief Disable the DMA corresponding to each trigger sources. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) { /* Avoid clearing status flags at the same time. */ @@ -265,11 +265,11 @@ static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask } /*! -* @brief When enable ,all logical will be reset. -* -* @param base ADC_ETC peripheral base address. -* @param enable Enable/Disable the software reset. -*/ + * @brief When enable ,all logical will be reset. + * + * @param base ADC_ETC peripheral base address. + * @param enable Enable/Disable the software reset. + */ static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable) { if (enable) @@ -283,14 +283,14 @@ static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable) } /*! -* @brief Do software trigger corresponding to each XBAR trigger sources. -* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, -* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources -* can only work in hardware trigger mode. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -*/ + * @brief Do software trigger corresponding to each XBAR trigger sources. + * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, + * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources + * can only work in hardware trigger mode. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup) { assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); @@ -299,15 +299,15 @@ static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t trigge } /*! -* @brief Get ADC conversion result from external XBAR sources. -* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would -* return Trigger0 source's chain1 conversion result. -* -* @param base ADC_ETC peripheral base address. -* @param triggerGroup Trigger group index. Available number is 0~7. -* @param chainGroup Trigger chain group index. Available number is 0~7. -* @return ADC conversion result value. -*/ + * @brief Get ADC conversion result from external XBAR sources. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would + * return Trigger0 source's chain1 conversion result. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + * @param chainGroup Trigger chain group index. Available number is 0~7. + * @return ADC conversion result value. + */ uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup); #if defined(__cplusplus) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c index d124af4728f30..cef6997595597 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c @@ -29,9 +29,9 @@ */ void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig) { - uint32_t mask = ((uint32_t)master >> 8) - 1; + uint32_t mask = ((uint32_t)master >> 8) - 1; uint32_t shift = (uint32_t)master & 0xFF; - base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); + base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); } /*! @@ -44,8 +44,8 @@ void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl) { volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16)); - uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1; - uint32_t shift = (uint32_t)peripheral & 0xFF; + uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1; + uint32_t shift = (uint32_t)peripheral & 0xFF; *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.h b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.h index 3926e11bcaa0a..432e0d52efb0f 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.h @@ -25,15 +25,17 @@ /*@}*/ /*! @brief List of AIPSTZ privilege configuration.*/ -typedef enum _aipstz_master_privilege_level { - kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */ - kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */ +typedef enum _aipstz_master_privilege_level +{ + kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */ + kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */ kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */ - kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */ + kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */ } aipstz_master_privilege_level_t; /*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/ -typedef enum _aipstz_master { +typedef enum _aipstz_master +{ kAIPSTZ_Master0 = (0x400U | 28U), kAIPSTZ_Master1 = (0x400U | 24U), kAIPSTZ_Master2 = (0x400U | 20U), @@ -42,47 +44,50 @@ typedef enum _aipstz_master { } aipstz_master_t; /*! @brief List of AIPSTZ peripheral access control configuration.*/ -typedef enum _aipstz_peripheral_access_control { +typedef enum _aipstz_peripheral_access_control +{ kAIPSTZ_PeripheralAllowUntrustedMaster = 1U, - kAIPSTZ_PeripheralWriteProtected = (1U << 1), - kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), - kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) + kAIPSTZ_PeripheralWriteProtected = (1U << 1), + kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), + kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) } aipstz_peripheral_access_control_t; -/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/ -typedef enum _aipstz_peripheral { +/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and + * shift for lower 8 bits.*/ +typedef enum _aipstz_peripheral +{ kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28), kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24), kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20), kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16), kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0), kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28), kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24), kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20), kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16), kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0), kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28), kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24), kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20), kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16), kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0), kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28), kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24), kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20), kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16), kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12), - kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8), - kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4), - kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0), kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28), kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24) } aipstz_peripheral_t; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.h index 3138fec3d7c42..ca6cd73b79148 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_aoi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_AOI_H_ @@ -15,7 +15,6 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ @@ -32,13 +31,13 @@ * @brief AOI input configurations. * * The selection item represents the Boolean evaluations. -*/ + */ typedef enum _aoi_input_config { - kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ - kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ + kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ - kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ + kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ } aoi_input_config_t; /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c index 8342476a19739..3632743903da4 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.c @@ -27,7 +27,7 @@ static void aligned_memcpy(void *dst, const void *src, size_t size) { - register uint32_t *to32 = (uint32_t *)(uintptr_t)dst; + register uint32_t *to32 = (uint32_t *)(uintptr_t)dst; register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src; while (size >= sizeof(uint32_t)) @@ -99,16 +99,16 @@ void BEE_GetDefaultConfig(bee_region_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->region0Mode = kBEE_AesCtrMode; - config->region1Mode = kBEE_AesCtrMode; + config->region0Mode = kBEE_AesCtrMode; + config->region1Mode = kBEE_AesCtrMode; config->region0AddrOffset = 0U; config->region1AddrOffset = 0U; - config->region0SecLevel = kBEE_SecurityLevel3; - config->region1SecLevel = kBEE_SecurityLevel3; - config->region1Bot = 0U; - config->region1Top = 0U; - config->accessPermission = kBEE_AccessProtDisabled; - config->endianSwapEn = kBEE_EndianSwapEnabled; + config->region0SecLevel = kBEE_SecurityLevel3; + config->region1SecLevel = kBEE_SecurityLevel3; + config->region1Bot = 0U; + config->region1Top = 0U; + config->accessPermission = kBEE_AccessProtDisabled; + config->endianSwapEn = kBEE_EndianSwapEnabled; } /*! @@ -145,11 +145,11 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config) BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode); /* Load values to registers */ - base->CTRL = beeCtrlVal; + base->CTRL = beeCtrlVal; base->ADDR_OFFSET0 = config->region0AddrOffset; base->ADDR_OFFSET1 = config->region1AddrOffset; - base->REGION1_BOT = config->region1Bot; - base->REGION1_TOP = config->region1Top; + base->REGION1_BOT = config->region1Bot; + base->REGION1_TOP = config->region1Top; /* Reenable BEE if it was enabled before. */ if (reenable) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.h b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.h index 4f94124b32dcf..77068a7ab64f6 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_bee.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_bee.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,13 +48,13 @@ typedef enum _bee_region typedef enum _bee_ac_prot_enable { kBEE_AccessProtDisabled = 0U, /*!< BEE access permission control disabled */ - kBEE_AccessProtEnabled = 1U /*!< BEE access permission control enabled */ + kBEE_AccessProtEnabled = 1U /*!< BEE access permission control enabled */ } bee_ac_prot_enable; typedef enum _bee_endian_swap_enable { kBEE_EndianSwapDisabled = 1U, /*!< BEE endian swap disabled */ - kBEE_EndianSwapEnabled = 0U /*!< BEE endian swap enabled */ + kBEE_EndianSwapEnabled = 0U /*!< BEE endian swap enabled */ } bee_endian_swap_enable; typedef enum _bee_security_level @@ -67,13 +67,13 @@ typedef enum _bee_security_level typedef enum _bee_status_flags { - kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */ - kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */ - kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */ - kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */ - kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */ - kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */ - kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */ + kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */ + kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */ + kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */ + kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */ + kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */ + kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */ + kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */ } bee_status_flags_t; /*! @brief BEE region configuration structure. */ @@ -186,8 +186,7 @@ void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config); * @param key AES key (in little-endian format). * @param keySize Size of AES key. */ -status_t BEE_SetRegionKey( - BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize); +status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize); /*! * @brief Loads the nonce for selected region into BEE nonce registers. @@ -200,8 +199,7 @@ status_t BEE_SetRegionKey( * @param nonce AES nonce (in little-endian format). * @param nonceSize Size of AES nonce. */ -status_t BEE_SetRegionNonce( - BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize); +status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize); /*! * @brief Gets the BEE status flags. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c index d4ce59e103934..259f299466b37 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.c @@ -26,8 +26,8 @@ #define L2CACHE_SAMLLWAYS_SIZE 16U #define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ /******************************************************************************* - * Prototypes - ******************************************************************************/ + * Prototypes + ******************************************************************************/ /*! * @brief Set for all ways and waiting for the operation finished. * This is provided for all the background operations. @@ -98,7 +98,7 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way); ******************************************************************************/ static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr) { - uint16_t mask = L2CACHE_8WAYS_MASK; + uint16_t mask = L2CACHE_8WAYS_MASK; uint32_t timeout = L2CACHE_OPERATION_TIMEOUT; /* Check the ways used at first. */ @@ -256,14 +256,14 @@ void L2CACHE_GetDefaultConfig(l2cache_config_t *config) L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; /* Get the default value */ - config->wayNum = (l2cache_way_num_t)number; - config->waySize = (l2cache_way_size)size; - config->repacePolicy = kL2CACHE_Roundrobin; - config->lateConfig = NULL; + config->wayNum = (l2cache_way_num_t)number; + config->waySize = (l2cache_way_size)size; + config->repacePolicy = kL2CACHE_Roundrobin; + config->lateConfig = NULL; config->istrPrefetchEnable = false; config->dataPrefetchEnable = false; - config->nsLockdownEnable = false; - config->writeAlloc = kL2CACHE_UseAwcache; + config->nsLockdownEnable = false; + config->writeAlloc = kL2CACHE_UseAwcache; } /*! @@ -377,7 +377,7 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) { uint32_t num_ways = 0; uint32_t size_way = 0; - uint32_t endAddr = address + size_byte; + uint32_t endAddr = address + size_byte; /* Get the number and size of the cache way. */ L2CACHE_GetWayNumSize(&num_ways, &size_way); @@ -415,7 +415,7 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) { uint32_t num_ways = 0; uint32_t size_way = 0; - uint32_t endAddr = address + size_byte; + uint32_t endAddr = address + size_byte; /* Get the number and size of the cache way. */ L2CACHE_GetWayNumSize(&num_ways, &size_way); @@ -497,8 +497,8 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) { #if (__DCACHE_PRESENT == 1U) - uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); - int32_t size = size_byte + address - addr; + uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); + int32_t size = size_byte + address - addr; uint32_t linesize = 32U; __DSB(); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.h b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.h index f8a72507e2ee9..17e30a61d2ee5 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_cache.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_cache.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CACHE_H_ @@ -27,7 +27,7 @@ #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT -#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 +#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 #endif #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* @@ -38,80 +38,80 @@ /*! @brief Number of level 2 cache controller ways. */ typedef enum _l2cache_way_num { - kL2CACHE_8ways = 0, /*!< 8 ways. */ + kL2CACHE_8ways = 0, /*!< 8 ways. */ #if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY - kL2CACHE_16ways /*!< 16 ways. */ -#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ + kL2CACHE_16ways /*!< 16 ways. */ +#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ } l2cache_way_num_t; /*! @brief Level 2 cache controller way size. */ typedef enum _l2cache_way_size { - kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ - kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ - kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ - kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ - kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ - kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ + kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ + kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ + kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ + kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ + kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ + kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ } l2cache_way_size; /*! @brief Level 2 cache controller replacement policy. */ typedef enum _l2cache_replacement { - kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ - kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ + kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ + kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ } l2cache_replacement_t; /*! @brief Level 2 cache controller force write allocate options. */ typedef enum _l2cache_writealloc { - kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ - kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ - kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ + kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ + kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ + kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ } l2cache_writealloc_t; /*! @brief Level 2 cache controller tag/data ram latency. */ typedef enum _l2cache_latency { - kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ - kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ - kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ - kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ - kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ - kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ - kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ - kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ + kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ + kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ + kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ + kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ + kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ + kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ + kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ + kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ } l2cache_latency_t; /*! @brief Level 2 cache controller tag/data ram latency configure structure. */ typedef struct _l2cache_latency_config { - l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ - l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ - l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ - l2cache_latency_t dataWriteLate; /*!< Data write latency. */ - l2cache_latency_t dataReadLate; /*!< Data Read latency. */ - l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ + l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ + l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ + l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ + l2cache_latency_t dataWriteLate; /*!< Data write latency. */ + l2cache_latency_t dataReadLate; /*!< Data Read latency. */ + l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ } L2cache_latency_config_t; /*! @brief Level 2 cache controller configure structure. */ typedef struct _l2cache_config { /* ------------------------ l2 cachec basic settings ---------------------------- */ - l2cache_way_num_t wayNum; /*!< The number of ways. */ - l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ - l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ + l2cache_way_num_t wayNum; /*!< The number of ways. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */ /* ------------------------ tag/data ram latency settings ----------------------- */ L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ /* ------------------------ Prefetch enable settings ---------------------------- */ - bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ - bool dataPrefetchEnable; /*!< Data prefetch enable. */ + bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ + bool dataPrefetchEnable; /*!< Data prefetch enable. */ /* ------------------------ Non-secure access settings -------------------------- */ - bool nsLockdownEnable; /*!< None-secure lockdown enable. */ + bool nsLockdownEnable; /*!< None-secure lockdown enable. */ /* ------------------------ other settings -------------------------------------- */ - l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ + l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */ } l2cache_config_t; -#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ /******************************************************************************* * API ******************************************************************************/ @@ -157,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 I-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. @@ -214,15 +214,15 @@ static inline void L1CACHE_CleanInvalidateDCache(void) * * @param address The start address of the memory to be invalidated. * @param size_byte The memory size. - * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. * The startAddr here will be forced to align to L1 D-cache line size if * startAddr is not aligned. For the size_byte, application should make sure the * alignment or make sure the right operation order if the size_byte is not aligned. */ static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); } @@ -239,8 +239,8 @@ static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t si */ static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); } @@ -257,8 +257,8 @@ static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_by */ static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) { - uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); - uint32_t size = size_byte + address - startAddr; + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); } @@ -280,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config); /*! * @brief Gets an available default settings for the cache controller. * - * This function initializes the cache controller configuration structure with default settings. + * This function initializes the cache controller configuration structure with default settings. * The default values are: * @code * config->waysNum = kL2CACHE_8ways; @@ -290,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config); * config->istrPrefetchEnable = false; * config->dataPrefetchEnable = false; * config->nsLockdownEnable = false; - * config->writeAlloc = kL2CACHE_UseAwcache; + * config->writeAlloc = kL2CACHE_UseAwcache; * @endcode * @param config Pointer to the configuration structure. */ @@ -458,7 +458,6 @@ void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); /*@}*/ - #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_common.c b/ext/hal/nxp/mcux/drivers/imx/fsl_common.c index 39e78bcd9f2bb..deca9c626e823 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_common.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_common.c @@ -1,11 +1,11 @@ /* -* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP -* All rights reserved. -* -* -* SPDX-License-Identifier: BSD-3-Clause -*/ + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ #include "fsl_common.h" #define SDK_MEM_MAGIC_NUMBER 12345U @@ -127,16 +127,16 @@ void *SDK_Malloc(size_t size, size_t alignbytes) p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; return (void *)p_align_addr; } void SDK_Free(void *ptr) { - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) { diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_common.h b/ext/hal/nxp/mcux/drivers/imx/fsl_common.h index d8a74ce412b86..73a309e696b3c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_common.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_common.h @@ -2,7 +2,7 @@ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -123,10 +123,11 @@ enum _status_groups kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ @@ -166,20 +167,6 @@ enum _generic_status /*! @brief Type used for all status and error return values. */ typedef int32_t status_t; -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - /* * Macro guard for whether to use default weak IRQ implementation in drivers */ @@ -190,11 +177,11 @@ typedef int32_t status_t; /*! @name Min/max macros */ /* @{ */ #if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) #endif #if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif /* @} */ @@ -371,7 +358,7 @@ _Pragma("diag_suppress=Pm120") #define AT_QUICKACCESS_SECTION_DATA(func) func #else #error Toolchain not supported. -#endif +#endif #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ /* @} */ @@ -386,6 +373,21 @@ _Pragma("diag_suppress=Pm120") #error Toolchain not supported. #endif /* defined(__ICCARM__) */ /* @} */ + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + /******************************************************************************* * API ******************************************************************************/ @@ -525,7 +527,7 @@ _Pragma("diag_suppress=Pm120") */ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); #endif /* ENABLE_RAM_VECTOR_TABLE. */ - + #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. @@ -566,15 +568,15 @@ _Pragma("diag_suppress=Pm120") * @param size The length required to malloc. * @param alignbytes The alignment size. * @retval The allocated memory. - */ + */ void *SDK_Malloc(size_t size, size_t alignbytes); - + /*! * @brief Free memory. * * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); + */ + void SDK_Free(void *ptr); #if defined(__cplusplus) } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c index 272cd482f3e51..a05f39411b93a 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c @@ -56,10 +56,10 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base) } /*! -* brief Enable the access to DCDC registers. -* -* param base DCDC peripheral base address. -*/ + * brief Enable the access to DCDC registers. + * + * param base DCDC peripheral base address. + */ void DCDC_Init(DCDC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -69,10 +69,10 @@ void DCDC_Init(DCDC_Type *base) } /*! -* brief Disable the access to DCDC registers. -* -* param base DCDC peripheral base address. -*/ + * brief Disable the access to DCDC registers. + * + * param base DCDC peripheral base address. + */ void DCDC_Deinit(DCDC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -82,19 +82,18 @@ void DCDC_Deinit(DCDC_Type *base) } /*! -* brief Configure the DCDC clock source. -* -* param base DCDC peripheral base address. -* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". -*/ + * brief Configure the DCDC clock source. + * + * param base DCDC peripheral base address. + * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". + */ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) { uint32_t tmp32; /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | - DCDC_REG0_PWD_OSC_INT_MASK); + tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | + DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK); switch (clockSource) { case kDCDC_ClockInternalOsc: @@ -115,23 +114,23 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) } /*! -* brief Get the default setting for detection configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* code -* config->enableXtalokDetection = false; -* config->powerDownOverVoltageDetection = true; -* config->powerDownLowVlotageDetection = false; -* config->powerDownOverCurrentDetection = true; -* config->powerDownPeakCurrentDetection = true; -* config->powerDownZeroCrossDetection = true; -* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; -* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; -* endcode -* -* param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ + * brief Get the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageDetection = true; + * config->powerDownLowVlotageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) { assert(NULL != config); @@ -139,22 +138,22 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableXtalokDetection = false; + config->enableXtalokDetection = false; config->powerDownOverVoltageDetection = true; - config->powerDownLowVlotageDetection = false; + config->powerDownLowVlotageDetection = false; config->powerDownOverCurrentDetection = true; config->powerDownPeakCurrentDetection = true; - config->powerDownZeroCrossDetection = true; - config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; - config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + config->powerDownZeroCrossDetection = true; + config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; } /*! -* breif Configure the DCDC detection. -* -* param base DCDC peripheral base address. -* param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ + * breif Configure the DCDC detection. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) { assert(NULL != config); @@ -196,19 +195,19 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con } /*! -* brief Get the default setting for low power configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* code -* config->enableOverloadDetection = true; -* config->enableAdjustHystereticValue = false; -* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; -* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; -* endcode -* -* param config Pointer to configuration structure. See to "dcdc_low_power_config_t" -*/ + * brief Get the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableOverloadDetection = true; + * config->enableAdjustHystereticValue = false; + * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t" + */ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) { assert(NULL != config); @@ -216,27 +215,26 @@ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableOverloadDetection = true; + config->enableOverloadDetection = true; config->enableAdjustHystereticValue = false; - config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; - config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; + config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; } /*! -* brief Configure the DCDC low power. -* -* param base DCDC peripheral base address. -* param config Pointer to configuration structure. See to "dcdc_low_power_config_t". -*/ + * brief Configure the DCDC low power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t". + */ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) { assert(NULL != config); uint32_t tmp32; /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | - DCDC_REG0_LP_OVERLOAD_THRSH_MASK); + tmp32 = base->REG0 & ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | + DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK); tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) | DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold); if (config->enableOverloadDetection) @@ -251,11 +249,11 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf } /*! -* brief Get DCDC status flags. -* -* param base peripheral base address. -* return Mask of asserted status flags. See to "_dcdc_status_flags_t". -*/ + * brief Get DCDC status flags. + * + * param base peripheral base address. + * return Mask of asserted status flags. See to "_dcdc_status_flags_t". + */ uint32_t DCDC_GetstatusFlags(DCDC_Type *base) { uint32_t tmp32 = 0U; @@ -269,11 +267,11 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base) } /*! -* brief Reset current alert signal. Alert signal is generate by peak current detection. -* -* param base DCDC peripheral base address. -* param enable Switcher to reset signal. True means reset signal. False means don't reset signal. -*/ + * brief Reset current alert signal. Alert signal is generate by peak current detection. + * + * param base DCDC peripheral base address. + * param enable Switcher to reset signal. True means reset signal. False means don't reset signal. + */ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) { if (enable) @@ -287,23 +285,23 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) } /*! -* brief Get the default setting for loop control configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* code -* config->enableCommonHysteresis = false; -* config->enableCommonThresholdDetection = false; -* config->enableInvertHysteresisSign = false; -* config->enableRCThresholdDetection = false; -* config->enableRCScaleCircuit = 0U; -* config->complementFeedForwardStep = 0U; -* config->controlParameterMagnitude = 2U; -* config->integralProportionalRatio = 2U; -* endcode -* -* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" -*/ + * brief Get the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" + */ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) { assert(NULL != config); @@ -311,22 +309,22 @@ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableCommonHysteresis = false; + config->enableCommonHysteresis = false; config->enableCommonThresholdDetection = false; - config->enableInvertHysteresisSign = false; - config->enableRCThresholdDetection = false; - config->enableRCScaleCircuit = 0U; - config->complementFeedForwardStep = 0U; - config->controlParameterMagnitude = 2U; - config->integralProportionalRatio = 2U; + config->enableInvertHysteresisSign = false; + config->enableRCThresholdDetection = false; + config->enableRCScaleCircuit = 0U; + config->complementFeedForwardStep = 0U; + config->controlParameterMagnitude = 2U; + config->integralProportionalRatio = 2U; } /*! -* brief Configure the DCDC loop control. -* -* param base DCDC peripheral base address. -* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". -*/ + * brief Configure the DCDC loop control. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". + */ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) { assert(NULL != config); @@ -346,10 +344,9 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t base->REG1 = tmp32; /* configure the DCDC_REG2 register. */ - tmp32 = base->REG2 & - ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | - DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK | - DCDC_REG2_LOOPCTRL_DC_C_MASK); + tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | + DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | + DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK); tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) | DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) | DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) | @@ -386,17 +383,17 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf } /*! -* brief Adjust the target voltage of VDD_SOC in run mode and low power mode. -* -* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is -* stabled. -* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch -* back to run mode if it detects the current loading is larger than about 50 mA(typical value). -* -* param base DCDC peripheral base address. -* param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. -* param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. -*/ + * brief Adjust the target voltage of VDD_SOC in run mode and low power mode. + * + * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is + * stabled. + * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch + * back to run mode if it detects the current loading is larger than about 50 mA(typical value). + * + * param base DCDC peripheral base address. + * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. + * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. + */ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby) { uint32_t tmp32; @@ -418,11 +415,11 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan } /*! -* brief Configure the DCDC internal regulator. -* -* param base DCDC peripheral base address. -* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". -*/ + * brief Configure the DCDC internal regulator. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". + */ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) { assert(NULL != config); @@ -440,15 +437,15 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula } /*! -* brief Boot DCDC into DCM(discontinous conduction mode). -* -* pwd_zcd=0x0; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3 or 0x5; -* DCM_set_ctrl=1'b1; -* -* param base DCDC peripheral base address. -*/ + * brief Boot DCDC into DCM(discontinous conduction mode). + * + * pwd_zcd=0x0; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * + * param base DCDC peripheral base address. + */ void DCDC_BootIntoDCM(DCDC_Type *base) { base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); @@ -457,14 +454,14 @@ void DCDC_BootIntoDCM(DCDC_Type *base) } /*! -* brief Boot DCDC into CCM(continous conduction mode). -* -* pwd_zcd=0x1; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3; -* -* param base DCDC peripheral base address. -*/ + * brief Boot DCDC into CCM(continous conduction mode). + * + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * + * param base DCDC peripheral base address. + */ void DCDC_BootIntoCCM(DCDC_Type *base) { base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.h index 86ba500356092..217a8eaffc44e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.h @@ -2,7 +2,7 @@ * Copyright (c) 2017, NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,27 +22,27 @@ /*! @brief DCDC driver version. */ #define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ /*! - * @brief DCDC status flags. - */ + * @brief DCDC status flags. + */ enum _dcdc_status_flags_t { kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */ }; /*! -* @brief The current bias of low power comparator. -*/ + * @brief The current bias of low power comparator. + */ typedef enum _dcdc_comparator_current_bias { - kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ + kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */ kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */ kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ } dcdc_comparator_current_bias_t; /*! -* @brief The threshold of over current detection. -*/ + * @brief The threshold of over current detection. + */ typedef enum _dcdc_over_current_threshold { kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */ @@ -52,8 +52,8 @@ typedef enum _dcdc_over_current_threshold } dcdc_over_current_threshold_t; /*! -* @brief The threshold if peak current detection. -*/ + * @brief The threshold if peak current detection. + */ typedef enum _dcdc_peak_current_threshold { kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */ @@ -65,23 +65,23 @@ typedef enum _dcdc_peak_current_threshold } dcdc_peak_current_threshold_t; /*! -* @brief The period of counting the charging times in power save mode. -*/ + * @brief The period of counting the charging times in power save mode. + */ typedef enum _dcdc_count_charging_time_period { - kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ + kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */ } dcdc_count_charging_time_period_t; /*! -* @brief The threshold of the counting number of charging times -*/ + * @brief The threshold of the counting number of charging times + */ typedef enum _dcdc_count_charging_time_threshold { kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */ kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */ kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */ - kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ + kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ } dcdc_count_charging_time_threshold_t; /*! @@ -89,14 +89,14 @@ typedef enum _dcdc_count_charging_time_threshold */ typedef enum _dcdc_clock_source { - kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ + kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */ kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */ } dcdc_clock_source_t; /*! -* @brief Configuration for DCDC detection. -*/ + * @brief Configuration for DCDC detection. + */ typedef struct _dcdc_detection_config { bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */ @@ -111,8 +111,8 @@ typedef struct _dcdc_detection_config } dcdc_detection_config_t; /*! -* @brief Configuration for the loop control. -*/ + * @brief Configuration for the loop control. + */ typedef struct _dcdc_loop_control_config { bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators. @@ -134,8 +134,8 @@ typedef struct _dcdc_loop_control_config optimize efficiency and loop response. */ } dcdc_loop_control_config_t; /*! -* @brief Configuration for DCDC low power. -*/ + * @brief Configuration for DCDC low power. + */ typedef struct _dcdc_low_power_config { bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the @@ -150,8 +150,8 @@ typedef struct _dcdc_low_power_config } dcdc_low_power_config_t; /*! -* @brief Configuration for DCDC internal regulator. -*/ + * @brief Configuration for DCDC internal regulator. + */ typedef struct _dcdc_internal_regulator_config { bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is @@ -180,17 +180,17 @@ extern "C" { */ /*! -* @brief Enable the access to DCDC registers. -* -* @param base DCDC peripheral base address. -*/ + * @brief Enable the access to DCDC registers. + * + * @param base DCDC peripheral base address. + */ void DCDC_Init(DCDC_Type *base); /*! -* @brief Disable the access to DCDC registers. -* -* @param base DCDC peripheral base address. -*/ + * @brief Disable the access to DCDC registers. + * + * @param base DCDC peripheral base address. + */ void DCDC_Deinit(DCDC_Type *base); /* @} */ @@ -201,11 +201,11 @@ void DCDC_Deinit(DCDC_Type *base); */ /*! -* @brief Get DCDC status flags. -* -* @param base peripheral base address. -* @return Mask of asserted status flags. See to "_dcdc_status_flags_t". -*/ + * @brief Get DCDC status flags. + * + * @param base peripheral base address. + * @return Mask of asserted status flags. See to "_dcdc_status_flags_t". + */ uint32_t DCDC_GetstatusFlags(DCDC_Type *base); /* @} */ @@ -236,79 +236,79 @@ static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable } /*! -* @brief Configure the DCDC clock source. -* -* @param base DCDC peripheral base address. -* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". -*/ + * @brief Configure the DCDC clock source. + * + * @param base DCDC peripheral base address. + * @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". + */ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); /*! -* @brief Get the default setting for detection configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableXtalokDetection = false; -* config->powerDownOverVoltageDetection = true; -* config->powerDownLowVlotageDetection = false; -* config->powerDownOverCurrentDetection = true; -* config->powerDownPeakCurrentDetection = true; -* config->powerDownZeroCrossDetection = true; -* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; -* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ + * @brief Get the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageDetection = true; + * config->powerDownLowVlotageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config); /*! -* @breif Configure the DCDC detection. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_detection_config_t" -*/ + * @breif Configure the DCDC detection. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config); /*! -* @brief Get the default setting for low power configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableOverloadDetection = true; -* config->enableAdjustHystereticValue = false; -* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; -* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t" -*/ + * @brief Get the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableOverloadDetection = true; + * config->enableAdjustHystereticValue = false; + * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t" + */ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config); /*! -* @brief Configure the DCDC low power. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t". -*/ + * @brief Configure the DCDC low power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t". + */ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config); /*! -* @brief Reset current alert signal. Alert signal is generate by peak current detection. -* -* @param base DCDC peripheral base address. -* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal. -*/ + * @brief Reset current alert signal. Alert signal is generate by peak current detection. + * + * @param base DCDC peripheral base address. + * @param enable Switcher to reset signal. True means reset signal. False means don't reset signal. + */ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable); /*! -* @brief Set the bangap trim value to trim bandgap voltage. -* -* @param base DCDC peripheral base address. -* @param TrimValue The bangap trim value. Available range is 0U-31U. -*/ + * @brief Set the bangap trim value to trim bandgap voltage. + * + * @param base DCDC peripheral base address. + * @param TrimValue The bangap trim value. Available range is 0U-31U. + */ static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue) { base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; @@ -316,31 +316,31 @@ static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t tri } /*! -* @brief Get the default setting for loop control configuration. -* -* The default configuration are set according to responding registers' setting when powered on. -* They are: -* @code -* config->enableCommonHysteresis = false; -* config->enableCommonThresholdDetection = false; -* config->enableInvertHysteresisSign = false; -* config->enableRCThresholdDetection = false; -* config->enableRCScaleCircuit = 0U; -* config->complementFeedForwardStep = 0U; -* config->controlParameterMagnitude = 2U; -* config->integralProportionalRatio = 2U; -* @endcode -* -* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" -*/ + * @brief Get the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" + */ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config); /*! -* @brief Configure the DCDC loop control. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". -*/ + * @brief Configure the DCDC loop control. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". + */ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config); /*! @@ -352,11 +352,11 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config); /*! -* @brief Set the current bias of low power comparator. -* -* @param base DCDC peripheral base address. -* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t". -*/ + * @brief Set the current bias of low power comparator. + * + * @param base DCDC peripheral base address. + * @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t". + */ static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule) { base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; @@ -369,33 +369,33 @@ static inline void DCDC_LockTargetVoltage(DCDC_Type *base) } /*! -* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode. -* -* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is -* stabled. -* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch -* back to run mode if it detects the current loading is larger than about 50 mA(typical value). -* -* @param base DCDC peripheral base address. -* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. -* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. -*/ + * @brief Adjust the target voltage of VDD_SOC in run mode and low power mode. + * + * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is + * stabled. + * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch + * back to run mode if it detects the current loading is larger than about 50 mA(typical value). + * + * @param base DCDC peripheral base address. + * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. + * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. + */ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby); /*! -* @brief Configure the DCDC internal regulator. -* -* @param base DCDC peripheral base address. -* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". -*/ + * @brief Configure the DCDC internal regulator. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". + */ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config); /*! -* @brief Ajust delay to reduce ground noise. -* -* @param base DCDC peripheral base address. -* @param enable Enable the feature or not. -*/ + * @brief Ajust delay to reduce ground noise. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) { if (enable) @@ -409,12 +409,12 @@ static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) } /*! -* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero -* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM. -* -* @param base DCDC peripheral base address. -* @param enable Enable the feature or not. -*/ + * @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero + * cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) { if (enable) @@ -435,26 +435,26 @@ static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) */ /*! -* @brief Boot DCDC into DCM(discontinous conduction mode). -* -* pwd_zcd=0x0; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3 or 0x5; -* DCM_set_ctrl=1'b1; -* -* @param base DCDC peripheral base address. -*/ + * @brief Boot DCDC into DCM(discontinous conduction mode). + * + * pwd_zcd=0x0; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * + * @param base DCDC peripheral base address. + */ void DCDC_BootIntoDCM(DCDC_Type *base); /*! -* @brief Boot DCDC into CCM(continous conduction mode). -* -* pwd_zcd=0x1; -* pwd_cmp_offset=0x0; -* dcdc_loopctrl_en_rcscale=0x3; -* -* @param base DCDC peripheral base address. -*/ + * @brief Boot DCDC into CCM(continous conduction mode). + * + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * + * @param base DCDC peripheral base address. + */ void DCDC_BootIntoCCM(DCDC_Type *base); #if defined(__cplusplus) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c index 67fba7fbd2a7e..9f6de532d7a5e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c @@ -52,20 +52,20 @@ typedef struct _dcp_hash_ctx_internal /*!< SHA-1/SHA-2 digest length in bytes */ enum _dcp_hash_digest_len { - kDCP_OutLenSha1 = 20u, + kDCP_OutLenSha1 = 20u, kDCP_OutLenSha256 = 32u, - kDCP_OutLenCrc32 = 4u, + kDCP_OutLenCrc32 = 4u, }; enum _dcp_work_packet_bit_definitions { - kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */ - kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */ - kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */ - kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */ + kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */ + kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */ + kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */ + kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */ kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16, - kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16, - kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16, + kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16, + kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16, }; /*! 64-byte block represented as byte array of 16 32-bit words */ @@ -106,7 +106,7 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel) { uint32_t statReg = 0; uint32_t semaReg = 0; - status_t status = kStatus_Fail; + status_t status = kStatus_Fail; switch (channel) { @@ -145,7 +145,7 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel) static void dcp_clear_status(DCP_Type *base) { volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u; - *dcpStatClrPtr = 0xFFu; + *dcpStatClrPtr = 0xFFu; } static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask) @@ -154,22 +154,22 @@ static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask) if (mask & kDCP_Channel0) { - chStatClrPtr = &base->CH0STAT + 2u; + chStatClrPtr = &base->CH0STAT + 2u; *chStatClrPtr = 0xFFu; } if (mask & kDCP_Channel1) { - chStatClrPtr = &base->CH1STAT + 2u; + chStatClrPtr = &base->CH1STAT + 2u; *chStatClrPtr = 0xFFu; } if (mask & kDCP_Channel2) { - chStatClrPtr = &base->CH2STAT + 2u; + chStatClrPtr = &base->CH2STAT + 2u; *chStatClrPtr = 0xFFu; } if (mask & kDCP_Channel3) { - chStatClrPtr = &base->CH3STAT + 2u; + chStatClrPtr = &base->CH3STAT + 2u; *chStatClrPtr = 0xFFu; } } @@ -178,7 +178,7 @@ static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle, { base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0); /* move the key by 32-bit words */ - int i = 0; + int i = 0; size_t keySize = 16u; while (keySize) { @@ -360,19 +360,19 @@ status_t DCP_AES_EncryptEcb( } /*! -* brief Encrypts AES using the ECB block mode. -* -* Puts AES ECB encrypt work packet to DCP channel. -* -* param base DCP peripheral base address -* param handle Handle used for this request. -* param[out] dcpPacket Memory for the DCP work packet. -* param plaintext Input plain text to encrypt. -* param[out] ciphertext Output cipher text -* param size Size of input and output data in bytes. Must be multiple of 16 bytes. -* return kStatus_Success The work packet has been scheduled at DCP channel. -* return kStatus_DCP_Again The DCP channel is busy processing previous request. -*/ + * brief Encrypts AES using the ECB block mode. + * + * Puts AES ECB encrypt work packet to DCP channel. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param[out] dcpPacket Memory for the DCP work packet. + * param plaintext Input plain text to encrypt. + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, @@ -388,9 +388,9 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, dcpPacket->control0 = 0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; - dcpPacket->bufferSize = (uint32_t)size; + dcpPacket->bufferSize = (uint32_t)size; if (handle->keySlot == kDCP_OtpKey) { @@ -475,10 +475,10 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, return kStatus_InvalidArgument; } - dcpPacket->control0 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->control0 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; dcpPacket->destinationBufferAddress = (uint32_t)plaintext; - dcpPacket->bufferSize = (uint32_t)size; + dcpPacket->bufferSize = (uint32_t)size; if (handle->keySlot == kDCP_OtpKey) { @@ -572,10 +572,10 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, dcpPacket->control0 = 0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ - dcpPacket->control1 = 0x10u; /* CBC */ - dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; - dcpPacket->bufferSize = (uint32_t)size; + dcpPacket->bufferSize = (uint32_t)size; if (handle->keySlot == kDCP_OtpKey) { @@ -674,9 +674,9 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */ dcpPacket->control1 = 0x10u; /* CBC */ - dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; dcpPacket->destinationBufferAddress = (uint32_t)plaintext; - dcpPacket->bufferSize = (uint32_t)size; + dcpPacket->bufferSize = (uint32_t)size; if (handle->keySlot == kDCP_OtpKey) { @@ -892,7 +892,7 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo)) { ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; - status = kStatus_Success; + status = kStatus_Success; } return status; @@ -919,10 +919,10 @@ static status_t dcp_hash_update_non_blocking( { return kStatus_Fail; } - dcpPacket->sourceBufferAddress = (uint32_t)msg; + dcpPacket->sourceBufferAddress = (uint32_t)msg; dcpPacket->destinationBufferAddress = 0; - dcpPacket->bufferSize = size; - dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash; + dcpPacket->bufferSize = size; + dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash; return dcp_schedule_work(base, ctxInternal->handle, dcpPacket); } @@ -1107,16 +1107,16 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx } /* set algorithm in context struct for later use */ - ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - ctxInternal->algo = algo; + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + ctxInternal->algo = algo; ctxInternal->blksz = 0u; for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) { ctxInternal->blk.w[0] = 0u; } - ctxInternal->state = kDCP_StateHashInit; + ctxInternal->state = kDCP_StateHashInit; ctxInternal->fullMessageSize = 0; - ctxInternal->handle = handle; + ctxInternal->handle = handle; return status; } @@ -1148,7 +1148,7 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp } ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - status = dcp_hash_check_context(ctxInternal, input); + status = dcp_hash_check_context(ctxInternal, input); if (kStatus_Success != status) { return status; @@ -1206,7 +1206,7 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s dcp_hash_ctx_internal_t *ctxInternal; ctxInternal = (dcp_hash_ctx_internal_t *)ctx; - status = dcp_hash_check_context(ctxInternal, output); + status = dcp_hash_check_context(ctxInternal, output); if (kStatus_Success != status) { return status; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h index cadfe8c76cb8d..654c9ec51b437 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h @@ -2,7 +2,7 @@ * Copyright 2017 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,11 +46,11 @@ enum _dcp_status */ typedef enum _dcp_ch_enable { - kDCP_chDisable = 0U, /*!< DCP channel disable */ - kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */ - kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */ - kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */ - kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */ + kDCP_chDisable = 0U, /*!< DCP channel disable */ + kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */ + kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */ + kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */ + kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */ kDCP_chEnableAll = 15U, /*!< DCP channel enable all */ } _dcp_ch_enable_t; @@ -82,13 +82,13 @@ typedef enum _dcp_channel */ typedef enum _dcp_key_slot { - kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */ - kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */ - kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/ - kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */ - kDCP_OtpKey = 4U, /*!< DCP OTP key. */ + kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */ + kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */ + kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/ + kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */ + kDCP_OtpKey = 4U, /*!< DCP OTP key. */ kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */ - kDCP_PayloadKey = 6U, /*!< DCP payload key. */ + kDCP_PayloadKey = 6U, /*!< DCP payload key. */ } dcp_key_slot_t; /*! @brief DCP key, input & output swap options @@ -96,11 +96,11 @@ typedef enum _dcp_key_slot */ typedef enum _dcp_swap { - kDCP_NoSwap = 0x0U, - kDCP_KeyByteSwap = 0x40000U, - kDCP_KeyWordSwap = 0x80000U, - kDCP_InputByteSwap = 0x100000U, - kDCP_InputWordSwap = 0x200000U, + kDCP_NoSwap = 0x0U, + kDCP_KeyByteSwap = 0x40000U, + kDCP_KeyWordSwap = 0x80000U, + kDCP_InputByteSwap = 0x100000U, + kDCP_InputWordSwap = 0x200000U, kDCP_OutputByteSwap = 0x400000U, kDCP_OutputWordSwap = 0x800000U, } dcp_swap_t; @@ -374,19 +374,19 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base, * @{ */ /*! -* @brief Encrypts AES using the ECB block mode. -* -* Puts AES ECB encrypt work packet to DCP channel. -* -* @param base DCP peripheral base address -* @param handle Handle used for this request. -* @param[out] dcpPacket Memory for the DCP work packet. -* @param plaintext Input plain text to encrypt. -* @param[out] ciphertext Output cipher text -* @param size Size of input and output data in bytes. Must be multiple of 16 bytes. -* @return kStatus_Success The work packet has been scheduled at DCP channel. -* @return kStatus_DCP_Again The DCP channel is busy processing previous request. -*/ + * @brief Encrypts AES using the ECB block mode. + * + * Puts AES ECB encrypt work packet to DCP channel. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param plaintext Input plain text to encrypt. + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.h b/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.h index f458f8de2d6a7..096bb851bf819 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,15 +16,14 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief DMAMUX driver version 2.0.2. */ -#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief DMAMUX driver version 2.0.3. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /******************************************************************************* @@ -75,7 +74,7 @@ void DMAMUX_Deinit(DMAMUX_Type *base); */ static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; } @@ -91,9 +90,9 @@ static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) */ static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; + base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK; } /*! @@ -105,9 +104,9 @@ static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) */ static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); + base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); } #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U @@ -121,7 +120,7 @@ static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_ */ static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; } @@ -136,9 +135,9 @@ static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channe */ static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; + base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK; } #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c index cd4b56b5e9b24..4d1c6ce2aa620 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.c @@ -79,23 +79,23 @@ static uint32_t EDMA_GetInstance(DMA_Type *base) */ void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); /* Push tcd into hardware TCD register */ - base->TCD[channel].SADDR = tcd->SADDR; - base->TCD[channel].SOFF = tcd->SOFF; - base->TCD[channel].ATTR = tcd->ATTR; - base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; - base->TCD[channel].SLAST = tcd->SLAST; - base->TCD[channel].DADDR = tcd->DADDR; - base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; base->TCD[channel].CITER_ELINKNO = tcd->CITER; - base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; /* Clear DONE bit first, otherwise ESG cannot be set */ - base->TCD[channel].CSR = 0; - base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; base->TCD[channel].BITER_ELINKNO = tcd->BITER; } @@ -128,7 +128,7 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config) tmpreg = base->CR; tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | - DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U)); base->CR = tmpreg; } @@ -166,12 +166,12 @@ void EDMA_GetDefaultConfig(edma_config_t *config) assert(config != NULL); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); config->enableRoundRobinArbitration = false; - config->enableHaltOnError = true; - config->enableContinuousLinkMode = false; - config->enableDebugMode = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; } /*! @@ -187,9 +187,9 @@ void EDMA_GetDefaultConfig(edma_config_t *config) */ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); + EDMA_TcdReset((edma_tcd_t *)(uint32_t)&base->TCD[channel]); } /*! @@ -219,11 +219,11 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) */ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); - EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); + EDMA_TcdSetTransferConfig((edma_tcd_t *)(uint32_t)&base->TCD[channel], config, nextTcd); } /*! @@ -238,7 +238,7 @@ void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfe */ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); assert(config != NULL); uint32_t tmpreg; @@ -269,10 +269,10 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino */ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); + EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel); } /*! @@ -291,9 +291,9 @@ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_typ */ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); + base->TCD[channel].CSR = (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); } /*! @@ -310,11 +310,11 @@ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWi */ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); - uint32_t tmpreg; + uint16_t tmpreg; - tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tmpreg = base->TCD[channel].ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } @@ -328,22 +328,22 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e */ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); /* Enable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) { - base->EEI |= (0x1U << channel); + base->EEI |= ((uint32_t)0x1U << channel); } /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; } /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; } @@ -359,24 +359,24 @@ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mas */ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); /* Disable error interrupt */ - if (mask & kEDMA_ErrorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) { - base->EEI &= ~(0x1U << channel); + base->EEI &= (uint32_t)(~(0x1U << channel)); } /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; + base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; } /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; + base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; } } @@ -391,20 +391,20 @@ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t ma void EDMA_TcdReset(edma_tcd_t *tcd) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); /* Reset channel TCD */ - tcd->SADDR = 0U; - tcd->SOFF = 0U; - tcd->ATTR = 0U; - tcd->NBYTES = 0U; - tcd->SLAST = 0U; - tcd->DADDR = 0U; - tcd->DOFF = 0U; - tcd->CITER = 0U; + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; tcd->DLAST_SGA = 0U; /* Enable auto disable request feature */ - tcd->CSR = DMA_CSR_DREQ(true); + tcd->CSR = DMA_CSR_DREQ(true); tcd->BITER = 0U; } @@ -438,9 +438,9 @@ void EDMA_TcdReset(edma_tcd_t *tcd) void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); assert(config != NULL); - assert(((uint32_t)nextTcd & 0x1FU) == 0); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); /* source address */ tcd->SADDR = config->srcAddr; @@ -449,15 +449,15 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co /* Source data and destination data transfer size */ tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); /* Source address signed offset */ - tcd->SOFF = config->srcOffset; + tcd->SOFF = (uint16_t)config->srcOffset; /* Destination address signed offset */ - tcd->DOFF = config->destOffset; + tcd->DOFF = (uint16_t)config->destOffset; /* Minor byte transfer count */ tcd->NBYTES = config->minorLoopBytes; /* Current major iteration count */ - tcd->CITER = config->majorLoopCounts; + tcd->CITER = (uint16_t)config->majorLoopCounts; /* Starting major iteration count */ - tcd->BITER = config->majorLoopCounts; + tcd->BITER = (uint16_t)config->majorLoopCounts; /* Enable scatter/gather processing */ if (nextTcd != NULL) { @@ -471,7 +471,7 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co previous transfer is not the last transfer, and channel request should be enabled at the next transfer(the next TCD). */ - tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; } } @@ -487,7 +487,7 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); uint32_t tmpreg; @@ -517,39 +517,39 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); - assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); if (type == kEDMA_MinorLink) /* Minor link config */ { - uint32_t tmpreg; + uint16_t tmpreg; /* Enable minor link */ tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; /* Set linked channel */ - tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); tcd->CITER = tmpreg; - tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); tcd->BITER = tmpreg; } else if (type == kEDMA_MajorLink) /* Major link config */ { - uint32_t tmpreg; + uint16_t tmpreg; /* Enable major link */ tcd->CSR |= DMA_CSR_MAJORELINK_MASK; /* Set major linked channel */ - tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); } else /* Link none */ { - tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; - tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; - tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; } } @@ -567,11 +567,11 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); - uint32_t tmpreg; + uint16_t tmpreg; - tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); } @@ -587,13 +587,13 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) assert(tcd != NULL); /* Enable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { tcd->CSR |= DMA_CSR_INTMAJOR_MASK; } /* Enable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { tcd->CSR |= DMA_CSR_INTHALF_MASK; } @@ -611,15 +611,15 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) assert(tcd != NULL); /* Disable Major interrupt */ - if (mask & kEDMA_MajorInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) { - tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; } /* Disable Half major interrupt */ - if (mask & kEDMA_HalfInterruptEnable) + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) { - tcd->CSR &= ~DMA_CSR_INTHALF_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; } } @@ -646,26 +646,26 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) */ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); uint32_t remainingCount = 0; - if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) + if (0U != (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)) { remainingCount = 0; } else { /* Calculate the unfinished bytes */ - if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) + if (0U != (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)) { - remainingCount = - (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; + remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT); } else { - remainingCount = - (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; + remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> + DMA_CITER_ELINKNO_CITER_SHIFT); } } @@ -682,16 +682,16 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) */ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); uint32_t retval = 0; /* Get DONE bit flag */ - retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + retval |= (((uint32_t)base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); /* Get ERROR bit flag */ - retval |= (((base->ERR >> channel) & 0x1U) << 1U); + retval |= ((((uint32_t)base->ERR >> channel) & 0x1U) << 1U); /* Get INT bit flag */ - retval |= (((base->INT >> channel) & 0x1U) << 2U); + retval |= ((((uint32_t)base->INT >> channel) & 0x1U) << 2U); return retval; } @@ -706,22 +706,22 @@ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) */ void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); /* Clear DONE bit flag */ - if (mask & kEDMA_DoneFlag) + if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) { - base->CDNE = channel; + base->CDNE = (uint8_t)channel; } /* Clear ERROR bit flag */ - if (mask & kEDMA_ErrorFlag) + if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) { - base->CERR = channel; + base->CERR = (uint8_t)channel; } /* Clear INT bit flag */ - if (mask & kEDMA_InterruptFlag) + if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) { - base->CINT = channel; + base->CINT = (uint8_t)channel; } } @@ -730,7 +730,7 @@ static uint8_t Get_StartInstance(void) static uint8_t StartInstanceNum; #if defined(DMA0) - StartInstanceNum = EDMA_GetInstance(DMA0); + StartInstanceNum = (uint8_t)EDMA_GetInstance(DMA0); #elif defined(DMA1) StartInstanceNum = EDMA_GetInstance(DMA1); #elif defined(DMA2) @@ -756,7 +756,7 @@ static uint8_t Get_StartInstance(void) void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) { assert(handle != NULL); - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); uint32_t edmaInstance; uint32_t channelIndex; @@ -764,36 +764,36 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) edma_tcd_t *tcdRegs; /* Zero the handle */ - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); - handle->base = base; - handle->channel = channel; + handle->base = base; + handle->channel = (uint8_t)channel; /* Get the DMA instance number */ - edmaInstance = EDMA_GetInstance(base); - StartInstance = Get_StartInstance(); - channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + edmaInstance = EDMA_GetInstance(base); + StartInstance = Get_StartInstance(); + channelIndex = ((edmaInstance - StartInstance) * (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; s_EDMAHandle[channelIndex] = handle; /* Enable NVIC interrupt */ - EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); /* Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), CSR will be 0. Because in order to suit EDMA busy check mechanism in EDMA_SubmitTransfer, CSR must be set 0. */ - tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; - tcdRegs->SADDR = 0; - tcdRegs->SOFF = 0; - tcdRegs->ATTR = 0; - tcdRegs->NBYTES = 0; - tcdRegs->SLAST = 0; - tcdRegs->DADDR = 0; - tcdRegs->DOFF = 0; - tcdRegs->CITER = 0; + tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; tcdRegs->DLAST_SGA = 0; - tcdRegs->CSR = 0; - tcdRegs->BITER = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; } /*! @@ -811,14 +811,14 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) { assert(handle != NULL); - assert(((uint32_t)tcdPool & 0x1FU) == 0); + assert(((uint32_t)tcdPool & 0x1FU) == 0U); /* Initialize tcd queue attribute. */ - handle->header = 0; - handle->tail = 0; + handle->header = 0; + handle->tail = 0; handle->tcdUsed = 0; - handle->tcdSize = tcdSize; - handle->flags = 0; + handle->tcdSize = (int8_t)tcdSize; + handle->flags = 0; handle->tcdPool = tcdPool; } @@ -869,16 +869,18 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, assert(config != NULL); assert(srcAddr != NULL); assert(destAddr != NULL); - assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); - assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); - assert(transferBytes % bytesEachRequest == 0); + assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 8U) || (srcWidth == 16U) || + (srcWidth == 32U)); + assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 8U) || (destWidth == 16U) || + (destWidth == 32U)); + assert((transferBytes % bytesEachRequest) == 0U); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); - config->destAddr = (uint32_t)destAddr; - config->srcAddr = (uint32_t)srcAddr; - config->minorLoopBytes = bytesEachRequest; + config->destAddr = (uint32_t)(uint32_t *)destAddr; + config->srcAddr = (uint32_t)(uint32_t *)srcAddr; + config->minorLoopBytes = bytesEachRequest; config->majorLoopCounts = transferBytes / bytesEachRequest; switch (srcWidth) { @@ -891,13 +893,22 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, case 4U: config->srcTransferSize = kEDMA_TransferSize4Bytes; break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + case 8U: + config->srcTransferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) case 16U: config->srcTransferSize = kEDMA_TransferSize16Bytes; break; +#endif case 32U: config->srcTransferSize = kEDMA_TransferSize32Bytes; break; default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); break; } switch (destWidth) @@ -911,30 +922,41 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config, case 4U: config->destTransferSize = kEDMA_TransferSize4Bytes; break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + case 8U: + config->destTransferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) case 16U: config->destTransferSize = kEDMA_TransferSize16Bytes; break; +#endif case 32U: config->destTransferSize = kEDMA_TransferSize32Bytes; break; default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); break; } switch (type) { case kEDMA_MemoryToMemory: - config->destOffset = destWidth; - config->srcOffset = srcWidth; + config->destOffset = (int16_t)destWidth; + config->srcOffset = (int16_t)srcWidth; break; case kEDMA_MemoryToPeripheral: - config->destOffset = 0U; - config->srcOffset = srcWidth; + config->destOffset = 0; + config->srcOffset = (int16_t)srcWidth; break; case kEDMA_PeripheralToMemory: - config->destOffset = destWidth; - config->srcOffset = 0U; + config->destOffset = (int16_t)destWidth; + config->srcOffset = 0; break; default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); break; } } @@ -956,8 +978,9 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t { assert(handle != NULL); assert(config != NULL); + uint32_t tmpCSR = 0; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; if (handle->tcdPool == NULL) { @@ -966,7 +989,8 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit this check mechanism, EDMA_CreatHandle will clear CSR register. */ - if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) + tmpCSR = tcdRegs->CSR; + if ((tmpCSR != 0U) && ((tmpCSR & DMA_CSR_DONE_MASK) == 0U)) { return kStatus_EDMA_Busy; } @@ -984,14 +1008,18 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t else /* Use the TCD queue. */ { uint32_t primask; - uint32_t csr; + uint16_t csr; int8_t currentTcd; int8_t previousTcd; int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; /* Check if tcd pool is full. */ - primask = DisableGlobalIRQ(); - if (handle->tcdUsed >= handle->tcdSize) + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) { EnableGlobalIRQ(primask); @@ -1000,16 +1028,16 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t currentTcd = handle->tail; handle->tcdUsed++; /* Calculate index of next TCD */ - nextTcd = currentTcd + 1U; + nextTcd = currentTcd + 1; if (nextTcd == handle->tcdSize) { - nextTcd = 0U; + nextTcd = 0; } /* Advance queue tail index */ handle->tail = nextTcd; EnableGlobalIRQ(primask); /* Calculate index of previous TCD */ - previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); /* Configure current TCD block. */ EDMA_TcdReset(&handle->tcdPool[currentTcd]); EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); @@ -1021,7 +1049,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t if (currentTcd != previousTcd) { /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + csr = (uint16_t)((handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK); handle->tcdPool[previousTcd].CSR = csr; /* Check if the TCD block in the registers is the previous one (points to current TCD block). It @@ -1047,9 +1075,9 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic link succeed. */ - if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) { - tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK; + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; return kStatus_Success; } /* @@ -1066,7 +1094,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t So shall configure TCD registers. */ } - else if (tcdRegs->DLAST_SGA != 0) + else if (tcdRegs->DLAST_SGA != 0U) { /* The current TCD block has been linked successfully. */ return kStatus_Success; @@ -1082,7 +1110,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t /* There is no live chain, TCD block need to be installed in TCD registers. */ EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); /* Enable channel request again. */ - if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) + if (0U != (handle->flags & EDMA_TRANSFER_ENABLED_MASK)) { handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); } @@ -1102,6 +1130,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t void EDMA_StartTransfer(edma_handle_t *handle) { assert(handle != NULL); + uint32_t tmpCSR = 0; if (handle->tcdPool == NULL) { @@ -1110,7 +1139,7 @@ void EDMA_StartTransfer(edma_handle_t *handle) else /* Use the TCD queue. */ { uint32_t primask; - edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; handle->flags |= EDMA_TRANSFER_ENABLED_MASK; @@ -1119,10 +1148,11 @@ void EDMA_StartTransfer(edma_handle_t *handle) { primask = DisableGlobalIRQ(); /* Check if channel request is actually disable. */ - if ((handle->base->ERQ & (1U << handle->channel)) == 0U) + if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U) { /* Check if transfer is paused. */ - if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + tmpCSR = tcdRegs->CSR; + if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK))) { /* Re-enable channel request must be as soon as possible, so must put it into @@ -1148,7 +1178,7 @@ void EDMA_StopTransfer(edma_handle_t *handle) { assert(handle != NULL); - handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); + handle->flags &= (~(uint8_t)EDMA_TRANSFER_ENABLED_MASK); handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); } @@ -1175,8 +1205,8 @@ void EDMA_AbortTransfer(edma_handle_t *handle) /* Handle the tcd */ if (handle->tcdPool != NULL) { - handle->header = 0; - handle->tail = 0; + handle->header = 0; + handle->tail = 0; handle->tcdUsed = 0; } } @@ -1213,11 +1243,19 @@ void EDMA_HandleIRQ(edma_handle_t *handle) { assert(handle != NULL); + bool transfer_done; + /* Clear EDMA interrupt flag */ handle->base->CINT = handle->channel; - if ((handle->tcdPool == NULL) && (handle->callback != NULL)) + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0U); + + if (handle->tcdPool == NULL) { - (handle->callback)(handle, handle->userData, true, 0); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, transfer_done, 0); + } } else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ { @@ -1225,10 +1263,7 @@ void EDMA_HandleIRQ(edma_handle_t *handle) uint32_t sga_index; int32_t tcds_done; uint8_t new_header; - bool transfer_done; - /* Check if transfer is already finished. */ - transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ sga -= (uint32_t)handle->tcdPool; /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ @@ -1237,17 +1272,20 @@ void EDMA_HandleIRQ(edma_handle_t *handle) if (transfer_done) { /* New header shall point to the next TCD to be loaded (current one is already finished) */ - new_header = sga_index; + new_header = (uint8_t)sga_index; } else { /* New header shall point to this descriptor currently loaded (not finished yet) */ - new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; } /* Calculate the number of finished TCDs */ - if (new_header == handle->header) + if (new_header == (uint8_t)handle->header) { - if (handle->tcdUsed == handle->tcdSize) + int8_t tmpTcdUsed = handle->tcdUsed; + int8_t tmpTcdSize = handle->tcdSize; + + if (tmpTcdUsed == tmpTcdSize) { tcds_done = handle->tcdUsed; } @@ -1259,18 +1297,18 @@ void EDMA_HandleIRQ(edma_handle_t *handle) } else { - tcds_done = new_header - handle->header; + tcds_done = (uint32_t)new_header - (uint32_t)handle->header; if (tcds_done < 0) { tcds_done += handle->tcdSize; } } /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ - handle->header = new_header; + handle->header = (int8_t)new_header; /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ - handle->tcdUsed -= tcds_done; + handle->tcdUsed -= (int8_t)tcds_done; /* Invoke callback function. */ - if (handle->callback) + if (NULL != handle->callback) { (handle->callback)(handle, handle->userData, transfer_done, tcds_done); } @@ -1290,8 +1328,10 @@ void EDMA_HandleIRQ(edma_handle_t *handle) } } +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4) /* 8 channels (Shared): kl28 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U) #if defined(DMA0) void DMA0_04_DriverIRQHandler(void) @@ -1505,9 +1545,12 @@ void DMA1_37_DriverIRQHandler(void) #endif #endif #endif /* 8 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 8) /* 16 channels (Shared): K32H844P */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U) void DMA0_08_DriverIRQHandler(void) { @@ -1783,7 +1826,10 @@ void DMA1_715_DriverIRQHandler(void) } #endif #endif /* 16 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 16) /* 32 channels (Shared): k80 */ #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U @@ -2059,9 +2105,12 @@ void DMA15_DMA31_DriverIRQHandler(void) #endif } #endif /* 32 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4) /* 32 channels (Shared): MCIMX7U5_M4 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U) void DMA0_0_4_DriverIRQHandler(void) { @@ -2335,9 +2384,12 @@ void DMA0_27_31_DriverIRQHandler(void) #endif } #endif /* 32 channels (Shared): MCIMX7U5 */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 0) /* 4 channels (No Shared): kv10 */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 0) void DMA0_DriverIRQHandler(void) { @@ -2380,7 +2432,7 @@ void DMA3_DriverIRQHandler(void) } /* 8 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U) void DMA4_DriverIRQHandler(void) { @@ -2424,7 +2476,7 @@ void DMA7_DriverIRQHandler(void) #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ /* 16 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U) void DMA8_DriverIRQHandler(void) { @@ -2508,7 +2560,7 @@ void DMA15_DriverIRQHandler(void) #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ /* 32 channels (No Shared) */ -#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U) void DMA16_DriverIRQHandler(void) { @@ -2672,3 +2724,4 @@ void DMA31_DriverIRQHandler(void) #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ #endif /* 4/8/16/32 channels (No Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h index 802f130359828..47f0d4d768fc2 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_edma.h @@ -23,22 +23,22 @@ /*! @name Driver version */ /*@{*/ /*! @brief eDMA driver version */ -#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7. */ /*@}*/ /*! @brief Compute the offset unit from DCHPRI3 */ -#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U))) /*! @brief Get the pointer of DCHPRIn */ -#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] +#define DMA_DCHPRIn(reg, channel) ((volatile uint8_t *)&(reg))[DMA_DCHPRI_INDEX(channel)] /*! @brief eDMA transfer configuration */ typedef enum _edma_transfer_size { - kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ - kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ - kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ - kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ } edma_transfer_size_t; @@ -83,7 +83,7 @@ typedef enum _edma_modulo /*! @brief Bandwidth control */ typedef enum _edma_bandwidth { - kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ } edma_bandwidth_t; @@ -99,26 +99,26 @@ typedef enum _edma_channel_link_type /*!@brief eDMA channel status flags. */ enum _edma_channel_status_flags { - kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ - kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ }; /*! @brief eDMA channel error status flags. */ enum _edma_error_status_flags { - kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ - kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ - kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ - kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ - kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ - kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ - kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ - kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ - kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ -#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ #endif kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ @@ -129,7 +129,7 @@ typedef enum _edma_interrupt_enable { kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ - kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ } edma_interrupt_enable_t; /*! @brief eDMA transfer type */ @@ -144,7 +144,7 @@ typedef enum _edma_transfer_type enum _edma_transfer_status { kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ - kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the transfer request. */ }; @@ -389,12 +389,17 @@ static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) { - assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); assert(config != NULL); - DMA_DCHPRIn(base, channel) = - (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | - DMA_DCHPRI0_CHPRI(config->channelPriority)); + bool tmpEnablePreemptAbility = config->enablePreemptAbility; + bool tmpEnableChannelPreemption = config->enableChannelPreemption; + uint8_t tmpChannelPriority = config->channelPriority; + uint8_t tmpReg = base->DCHPRI3; + + DMA_DCHPRIn(tmpReg, channel) = + (DMA_DCHPRI0_DPA((false == tmpEnablePreemptAbility ? 0U : 1U)) | + DMA_DCHPRI0_ECP((true == tmpEnableChannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority)); } /*! @@ -455,9 +460,9 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e */ static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); + base->EARS = (base->EARS & (uint32_t)(~(1U << channel))) | ((true == enable ? 1U : 0U) << channel); } #endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ @@ -472,9 +477,10 @@ static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, boo */ static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); - base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); + base->TCD[channel].CSR = + (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); } /*! @@ -585,9 +591,9 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); - tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); } /*! @@ -614,9 +620,9 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) { assert(tcd != NULL); - assert(((uint32_t)tcd & 0x1FU) == 0); + assert(((uint32_t)tcd & 0x1FU) == 0U); - tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); } /*! @@ -653,7 +659,7 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); */ static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); base->SERQ = DMA_SERQ_SERQ(channel); } @@ -668,7 +674,7 @@ static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) */ static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); base->CERQ = DMA_CERQ_CERQ(channel); } @@ -683,7 +689,7 @@ static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) */ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); base->SSRT = DMA_SSRT_SSRT(channel); } @@ -722,7 +728,7 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); * * @param base eDMA peripheral base address. * @return The mask of error status flags. Users need to use the -* _edma_error_status_flags type to decode the return variables. + * _edma_error_status_flags type to decode the return variables. */ static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) { @@ -874,7 +880,9 @@ void EDMA_AbortTransfer(edma_handle_t *handle); */ static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) { - return (handle->tcdSize - handle->tcdUsed); + int8_t tmpTcdSize = handle->tcdSize; + int8_t tmpTcdUsed = handle->tcdUsed; + return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed); } /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c index e9d7e048880e7..0c90627759096 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.c @@ -210,22 +210,22 @@ void ENC_GetDefaultConfig(enc_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableReverseDirection = false; - config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; - config->HOMETriggerMode = kENC_HOMETriggerDisabled; - config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; - config->enableTRIGGERClearPositionCounter = false; + config->enableReverseDirection = false; + config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kENC_HOMETriggerDisabled; + config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; config->enableTRIGGERClearHoldPositionCounter = false; - config->enableWatchdog = false; - config->watchdogTimeoutValue = 0U; - config->filterCount = 0U; - config->filterSamplePeriod = 0U; - config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; - config->positionCompareValue = 0xFFFFFFFFU; - config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; - config->enableModuloCountMode = false; - config->positionModulusValue = 0U; - config->positionInitialValue = 0U; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; } /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.h index 52b8b1895e9cb..badd234cf2456 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_enc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_enc.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,13 +25,13 @@ */ enum _enc_interrupt_enable { - kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ - kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ - kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ + kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ kENC_SimultBothPhaseChangeInterruptEnable = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ - kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ }; @@ -42,14 +42,14 @@ enum _enc_interrupt_enable */ enum _enc_status_flags { - kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ - kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ - kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ - kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ + kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ - kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ - kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ - kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ + kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ }; /*! @@ -59,14 +59,14 @@ enum _enc_status_flags */ enum _enc_signal_status_flags { - kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ - kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ - kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ - kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ - kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ - kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ - kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ - kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ + kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ }; /*! @@ -151,7 +151,7 @@ typedef struct _enc_config enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. - */ + */ /* Watchdog. */ bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c index 28dda26746643..15182e15fa3f3 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c @@ -35,7 +35,7 @@ * * param base EWM peripheral base address * param config The configuration of the EWM -*/ + */ void EWM_Init(EWM_Type *base, const ewm_config_t *config) { assert(config); @@ -69,7 +69,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config) * This function is used to shut down the EWM. * * param base EWM peripheral base address -*/ + */ void EWM_Deinit(EWM_Type *base) { EWM_DisableInterrupts(base, kEWM_InterruptEnable); @@ -107,17 +107,17 @@ void EWM_GetDefaultConfig(ewm_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableEwm = true; - config->enableEwmInput = false; + config->enableEwm = true; + config->enableEwmInput = false; config->setInputAssertLogic = false; - config->enableInterrupt = false; + config->enableInterrupt = false; #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT config->clockSource = kEWM_LpoClockSource0; #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER config->prescaler = 0U; #endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ - config->compareLowValue = 0U; + config->compareLowValue = 0U; config->compareHighValue = 0xFEU; } @@ -127,14 +127,14 @@ void EWM_GetDefaultConfig(ewm_config_t *config) * This function resets the EWM counter to zero. * * param base EWM peripheral base address -*/ + */ void EWM_Refresh(EWM_Type *base) { uint32_t primaskValue = 0U; /* Disable the global interrupt to protect refresh sequence */ primaskValue = DisableGlobalIRQ(); - base->SERV = (uint8_t)0xB4U; - base->SERV = (uint8_t)0x2CU; + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; EnableGlobalIRQ(primaskValue); } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.h b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.h index 15a9e61d25232..3b5fd3a7de4b9 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_ewm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_EWM_H_ @@ -15,7 +15,6 @@ * @{ */ - /******************************************************************************* * Definitions *******************************************************************************/ @@ -38,10 +37,10 @@ typedef enum _ewm_lpo_clock_source #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ /*! -* @brief Data structure for EWM configuration. -* -* This structure is used to configure the EWM. -*/ + * @brief Data structure for EWM configuration. + * + * This structure is used to configure the EWM. + */ typedef struct _ewm_config { bool enableEwm; /*!< Enable EWM module */ @@ -109,7 +108,7 @@ extern "C" { * * @param base EWM peripheral base address * @param config The configuration of the EWM -*/ + */ void EWM_Init(EWM_Type *base, const ewm_config_t *config); /*! @@ -118,7 +117,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config); * This function is used to shut down the EWM. * * @param base EWM peripheral base address -*/ + */ void EWM_Deinit(EWM_Type *base); /*! @@ -205,7 +204,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) * This function resets the EWM counter to zero. * * @param base EWM peripheral base address -*/ + */ void EWM_Refresh(EWM_Type *base); /*@}*/ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c index f3c45f624cdf3..9cb5046e050ea 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c @@ -113,7 +113,7 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) * note After calling this API, call the FLEXO_Init to use the FlexIO module. * * param base FlexIO peripheral base address -*/ + */ void FLEXIO_Deinit(FLEXIO_Type *base) { FLEXIO_Enable(base, false); @@ -141,9 +141,9 @@ void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) /* Initializes the configure structure to zero. */ memset(userConfig, 0, sizeof(*userConfig)); - userConfig->enableFlexio = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; userConfig->enableFastAccess = false; } @@ -151,7 +151,7 @@ void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) * brief Resets the FlexIO module. * * param base FlexIO peripheral base address -*/ + */ void FLEXIO_Reset(FLEXIO_Type *base) { /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ @@ -166,7 +166,7 @@ void FLEXIO_Reset(FLEXIO_Type *base) * param type Shifter type of flexio_shifter_buffer_type_t * param index Shifter index * return Corresponding shifter buffer index -*/ + */ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) { assert(index < FLEXIO_SHIFTBUF_COUNT); @@ -310,7 +310,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_ * param isr FlexIO simulated peripheral interrupt handler. * retval kStatus_Success Successfully create the handle. * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ + */ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) { assert(base); @@ -325,9 +325,9 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) if (s_flexioHandle[index] == NULL) { /* Register FLEXIO simulated driver base, handle and isr. */ - s_flexioType[index] = base; + s_flexioType[index] = base; s_flexioHandle[index] = handle; - s_flexioIsr[index] = isr; + s_flexioIsr[index] = isr; break; } } @@ -348,7 +348,7 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) * param base Pointer to the FlexIO simulated peripheral type. * retval kStatus_Success Successfully create the handle. * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ + */ status_t FLEXIO_UnregisterHandleIRQ(void *base) { assert(base); @@ -361,9 +361,9 @@ status_t FLEXIO_UnregisterHandleIRQ(void *base) if (s_flexioType[index] == base) { /* Unregister FLEXIO simulated driver handle and isr. */ - s_flexioType[index] = NULL; + s_flexioType[index] = NULL; s_flexioHandle[index] = NULL; - s_flexioIsr[index] = NULL; + s_flexioIsr[index] = NULL; break; } } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h index da74e1f4540f4..b54a1dc2f63a5 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_H_ @@ -34,7 +34,7 @@ typedef enum _flexio_timer_trigger_polarity { kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ } flexio_timer_trigger_polarity_t; /*! @brief Define type of timer trigger source.*/ @@ -47,26 +47,26 @@ typedef enum _flexio_timer_trigger_source /*! @brief Define type of timer/shifter pin configuration.*/ typedef enum _flexio_pin_config { - kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ - kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ - kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ } flexio_pin_config_t; /*! @brief Definition of pin polarity.*/ typedef enum _flexio_pin_polarity { kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ - kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ } flexio_pin_polarity_t; /*! @brief Define type of timer work mode.*/ typedef enum _flexio_timer_mode { - kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ - kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ - kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ } flexio_timer_mode_t; /*! @brief Define type of timer initial output or timer reset condition.*/ @@ -76,7 +76,7 @@ typedef enum _flexio_timer_output reset. */ kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer reset. */ - kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ } flexio_timer_output_t; @@ -96,23 +96,23 @@ typedef enum _flexio_timer_decrement_source /*! @brief Define type of timer reset condition.*/ typedef enum _flexio_timer_reset_condition { - kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ - kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to Timer Output. */ - kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ - kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ } flexio_timer_reset_condition_t; /*! @brief Define type of timer disable condition.*/ typedef enum _flexio_timer_disable_condition { - kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ - kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ - kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ - kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided Trigger is high. */ kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ @@ -121,22 +121,22 @@ typedef enum _flexio_timer_disable_condition /*! @brief Define type of timer enable condition.*/ typedef enum _flexio_timer_enable_condition { - kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ - kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ - kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ - kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ - kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ - kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ - kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ } flexio_timer_enable_condition_t; /*! @brief Define type of timer stop bit generate condition.*/ typedef enum _flexio_timer_stop_bit_condition { - kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ - kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ - kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer disable. */ } flexio_timer_stop_bit_condition_t; @@ -145,7 +145,7 @@ typedef enum _flexio_timer_stop_bit_condition typedef enum _flexio_timer_start_bit_condition { kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ - kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ } flexio_timer_start_bit_condition_t; /*! @brief Define type of timer polarity for shifter control. */ @@ -158,10 +158,10 @@ typedef enum _flexio_shifter_timer_polarity /*! @brief Define type of shifter working mode.*/ typedef enum _flexio_shifter_mode { - kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ - kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ - kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ - kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ #if FSL_FEATURE_FLEXIO_HAS_STATE_MODE kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing @@ -176,7 +176,7 @@ typedef enum _flexio_shifter_mode /*! @brief Define type of shifter input source.*/ typedef enum _flexio_shifter_input_source { - kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ } flexio_shifter_input_source_t; @@ -184,8 +184,8 @@ typedef enum _flexio_shifter_input_source typedef enum _flexio_shifter_stop_bit { kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ - kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ - kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ } flexio_shifter_stop_bit_t; /*! @brief Define type of START bit configuration.*/ @@ -195,16 +195,16 @@ typedef enum _flexio_shifter_start_bit data on enable. */ kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads data on first shift. */ - kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ } flexio_shifter_start_bit_t; /*! @brief Define FlexIO shifter buffer type*/ typedef enum _flexio_shifter_buffer_type { - kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ - kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ - kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ #if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ @@ -342,7 +342,7 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); * @note After calling this API, call the FLEXO_Init to use the FlexIO module. * * @param base FlexIO peripheral base address -*/ + */ void FLEXIO_Deinit(FLEXIO_Type *base); /*! @@ -363,7 +363,7 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); * @brief Resets the FlexIO module. * * @param base FlexIO peripheral base address -*/ + */ void FLEXIO_Reset(FLEXIO_Type *base); /*! @@ -371,7 +371,7 @@ void FLEXIO_Reset(FLEXIO_Type *base); * * @param base FlexIO peripheral base address * @param enable true to enable, false to disable. -*/ + */ static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) { if (enable) @@ -390,7 +390,7 @@ static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) * * @param base FlexIO peripheral base address * @return FlexIO pin input data -*/ + */ static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) { return base->PIN; @@ -403,7 +403,7 @@ static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) * * @param base FlexIO peripheral base address * @return current State pointer -*/ + */ static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) { return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); @@ -482,7 +482,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_ * @param mask The shifter status mask which can be calculated by (1 << shifter index) * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) { base->SHIFTSIEN |= mask; @@ -495,7 +495,7 @@ static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint3 * @param mask The shifter status mask which can be calculated by (1 << shifter index) * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) { base->SHIFTSIEN &= ~mask; @@ -508,7 +508,7 @@ static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint * @param mask The shifter error mask which can be calculated by (1 << shifter index) * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) { base->SHIFTEIEN |= mask; @@ -521,7 +521,7 @@ static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32 * @param mask The shifter error mask which can be calculated by (1 << shifter index) * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) { base->SHIFTEIEN &= ~mask; @@ -534,7 +534,7 @@ static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint3 * @param mask The timer status mask which can be calculated by (1 << timer index) * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ + */ static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) { base->TIMIEN |= mask; @@ -547,7 +547,7 @@ static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_ * @param mask The timer status mask which can be calculated by (1 << timer index) * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ + */ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) { base->TIMIEN &= ~mask; @@ -565,7 +565,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32 * * @param base FlexIO peripheral base address * @return Shifter status flags -*/ + */ static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) { return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); @@ -578,7 +578,7 @@ static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) * @param mask The shifter status mask which can be calculated by (1 << shifter index) * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) { base->SHIFTSTAT = mask; @@ -589,7 +589,7 @@ static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t ma * * @param base FlexIO peripheral base address * @return Shifter error flags -*/ + */ static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) { return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); @@ -602,7 +602,7 @@ static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) * @param mask The shifter error mask which can be calculated by (1 << shifter index) * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate * the mask by using ((1 << shifter index0) | (1 << shifter index1)) -*/ + */ static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) { base->SHIFTERR = mask; @@ -613,7 +613,7 @@ static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mas * * @param base FlexIO peripheral base address * @return Timer status flags -*/ + */ static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) { return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); @@ -626,7 +626,7 @@ static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) * @param mask The timer status mask which can be calculated by (1 << timer index) * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate * the mask by using ((1 << timer index0) | (1 << timer index1)) -*/ + */ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) { base->TIMSTAT = mask; @@ -648,7 +648,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask * @param base FlexIO peripheral base address * @param mask The shifter status mask which can be calculated by (1 << shifter index) * @param enable True to enable, false to disable. -*/ + */ static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) { if (enable) @@ -668,7 +668,7 @@ static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mas * @param type Shifter type of flexio_shifter_buffer_type_t * @param index Shifter index * @return Corresponding shifter buffer index -*/ + */ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); /*! @@ -679,7 +679,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer * @param isr FlexIO simulated peripheral interrupt handler. * @retval kStatus_Success Successfully create the handle. * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ + */ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); /*! @@ -688,7 +688,7 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); * @param base Pointer to the FlexIO simulated peripheral type. * @retval kStatus_Success Successfully create the handle. * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. -*/ + */ status_t FLEXIO_UnregisterHandleIRQ(void *base); /* @} */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c index fc060d9e9ab42..941ae453d4a19 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,12 +20,12 @@ /*! @brief FLEXIO I2C transfer state */ enum _flexio_i2c_master_transfer_states { - kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ - kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ - kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ - kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ - kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ }; /******************************************************************************* @@ -85,14 +85,14 @@ static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, uint32_t byteCount; /* Init the handle member. */ - handle->transfer.slaveAddress = xfer->slaveAddress; - handle->transfer.direction = xfer->direction; - handle->transfer.subaddress = xfer->subaddress; + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; handle->transfer.subaddressSize = xfer->subaddressSize; - handle->transfer.data = xfer->data; - handle->transfer.dataSize = xfer->dataSize; - handle->transfer.flags = xfer->flags; - handle->transferSize = xfer->dataSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; /* Initial state, i2c check address state. */ handle->state = kFLEXIO_I2C_CheckAddress; @@ -388,8 +388,8 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t flexio_shifter_config_t shifterConfig; flexio_timer_config_t timerConfig; uint32_t controlVal = 0; - uint16_t timerDiv = 0; - status_t result = kStatus_Success; + uint16_t timerDiv = 0; + status_t result = kStatus_Success; memset(&shifterConfig, 0, sizeof(shifterConfig)); memset(&timerConfig, 0, sizeof(timerConfig)); @@ -401,46 +401,46 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t /* Do hardware configuration. */ /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerSelect = base->timerIndex[1]; shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerSelect = base->timerIndex[1]; shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDAPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); /*3. Configure the timer 0 for generating bit clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; @@ -456,20 +456,20 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); /* 4. Configure the timer 1 for controlling shifters. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCLPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ timerConfig.timerCompare = 8 * 2 - 1; @@ -503,12 +503,12 @@ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; /* Clear the shifter flag. */ base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); @@ -535,9 +535,9 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) /* Initializes the configure structure to zero. */ memset(masterConfig, 0, sizeof(*masterConfig)); - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; masterConfig->enableFastAccess = false; /* Default baud rate at 100kbps. */ @@ -549,7 +549,7 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) * * param base Pointer to FLEXIO_I2C_Type structure * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. -*/ + */ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) { @@ -575,7 +575,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) * The parameter can be any combination of the following values: * arg kFLEXIO_I2C_RxFullFlag * arg kFLEXIO_I2C_ReceiveNakFlag -*/ + */ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) { @@ -642,8 +642,8 @@ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) */ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; FLEXIO_Type *flexioBase = base->flexioBase; /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ @@ -667,7 +667,7 @@ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal * retval kStatus_Success Successfully configured the count. * retval kStatus_InvalidArgument Input argument is invalid. -*/ + */ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) { if (count > 14U) @@ -675,15 +675,15 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) return kStatus_InvalidArgument; } - uint16_t timerCmp = 0; - uint32_t timerConfig = 0; + uint16_t timerCmp = 0; + uint32_t timerConfig = 0; FLEXIO_Type *flexioBase = base->flexioBase; timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; timerCmp &= 0x00FFU; timerCmp |= (count * 18 + 1U) << 8U; flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; - timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; @@ -869,11 +869,16 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag))) { } - + FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1 << base->timerIndex[0]) | (1 << base->timerIndex[1]))); result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success)); + /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. */ + while(0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1 << base->timerIndex[0]))) + { + } + return result; } @@ -901,7 +906,7 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, /* Register callback and userData. */ handle->completionCallback = callback; - handle->userData = userData; + handle->userData = userData; /* Enable interrupt in NVIC. */ EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); @@ -996,7 +1001,7 @@ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_mas */ void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) { - FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; uint32_t statusFlags; status_t result; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.h index 394d7157224d5..c55d476a80d1e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexIO I2C master driver version 2.1.6. */ -#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*! @brief FlexIO I2C master driver version 2.1.7. */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*@}*/ /*! @brief FlexIO I2C transfer status*/ @@ -31,21 +31,21 @@ enum _flexio_i2c_status { kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ - kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ }; /*! @brief Define FlexIO I2C master interrupt mask. */ enum _flexio_i2c_master_interrupt { kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ - kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ }; /*! @brief Define FlexIO I2C master status mask. */ enum _flexio_i2c_master_status_flags { - kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ - kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ }; @@ -53,7 +53,7 @@ enum _flexio_i2c_master_status_flags typedef enum _flexio_i2c_direction { kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ - kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ } flexio_i2c_direction_t; /*! @brief Define FlexIO I2C master access structure typedef. */ @@ -178,7 +178,7 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) * * @param base Pointer to FLEXIO_I2C_Type structure. * @param enable Pass true to enable module, false does not have any effect. -*/ + */ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) { if (enable) @@ -199,7 +199,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) * * @param base Pointer to FLEXIO_I2C_Type structure * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. -*/ + */ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); @@ -211,7 +211,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); * The parameter can be any combination of the following values: * @arg kFLEXIO_I2C_RxFullFlag * @arg kFLEXIO_I2C_ReceiveNakFlag -*/ + */ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); @@ -312,7 +312,7 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal * @retval kStatus_Success Successfully configured the count. * @retval kStatus_InvalidArgument Input argument is invalid. -*/ + */ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c index 41457284a4115..acf2ea32a765b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c @@ -14,8 +14,8 @@ #endif /******************************************************************************* -* Definitations -******************************************************************************/ + * Definitations + ******************************************************************************/ enum _sai_transfer_state { kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */ @@ -60,11 +60,11 @@ static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) { - uint32_t i = 0; - uint8_t j = 0; + uint32_t i = 0; + uint8_t j = 0; uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - uint32_t temp = 0; + uint32_t data = 0; + uint32_t temp = 0; for (i = 0; i < size / bytesPerWord; i++) { @@ -75,16 +75,16 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, txData++; } base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth); - data = 0; + data = 0; } } static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) { - uint32_t i = 0; - uint8_t j = 0; + uint32_t i = 0; + uint8_t j = 0; uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; + uint32_t data = 0; for (i = 0; i < size / bytesPerWord; i++) { @@ -110,13 +110,13 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, * * param base FlexIO I2S base pointer * param config FlexIO I2S configure structure. -*/ + */ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) { assert(base && config); flexio_shifter_config_t shifterConfig = {0}; - flexio_timer_config_t timerConfig = {0}; + flexio_timer_config_t timerConfig = {0}; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Ungate flexio clock. */ @@ -127,14 +127,14 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) FLEXIO_Reset(base->flexioBase); /* Set shifter for I2S Tx data */ - shifterConfig.timerSelect = base->bclkTimerIndex; - shifterConfig.pinSelect = base->txPinIndex; + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->txPinIndex; shifterConfig.timerPolarity = config->txTimerPolarity; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinPolarity = config->txPinPolarity; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinPolarity = config->txPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; if (config->masterSlave == kFLEXIO_I2S_Master) { shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; @@ -147,89 +147,89 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig); /* Set shifter for I2S Rx Data */ - shifterConfig.timerSelect = base->bclkTimerIndex; - shifterConfig.pinSelect = base->rxPinIndex; + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->rxPinIndex; shifterConfig.timerPolarity = config->rxTimerPolarity; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinPolarity = config->rxPinPolarity; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinPolarity = config->rxPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig); /* Set Timer to I2S frame sync */ if (config->masterSlave == kFLEXIO_I2S_Master) { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->fsPinIndex; - timerConfig.pinPolarity = config->fsPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; } else { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->fsPinIndex; - timerConfig.pinPolarity = config->fsPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; } FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig); /* Set Timer to I2S bit clock */ if (config->masterSlave == kFLEXIO_I2S_Master) { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinSelect = base->bclkPinIndex; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinPolarity = config->bclkPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; } else { - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinSelect = base->bclkPinIndex; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinPolarity = config->bclkPinPolarity; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; } FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig); @@ -258,12 +258,12 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->masterSlave = kFLEXIO_I2S_Master; - config->enableI2S = true; - config->txPinPolarity = kFLEXIO_PinActiveHigh; - config->rxPinPolarity = kFLEXIO_PinActiveHigh; + config->masterSlave = kFLEXIO_I2S_Master; + config->enableI2S = true; + config->txPinPolarity = kFLEXIO_PinActiveHigh; + config->rxPinPolarity = kFLEXIO_PinActiveHigh; config->bclkPinPolarity = kFLEXIO_PinActiveHigh; - config->fsPinPolarity = kFLEXIO_PinActiveLow; + config->fsPinPolarity = kFLEXIO_PinActiveLow; config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; } @@ -275,19 +275,19 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) * call the FLEXO_I2S_Init to use the FlexIO I2S module. * * param base FlexIO I2S base pointer -*/ + */ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) { base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0; base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0; base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0; base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0; - base->flexioBase->TIMCFG[base->fsTimerIndex] = 0; - base->flexioBase->TIMCMP[base->fsTimerIndex] = 0; - base->flexioBase->TIMCTL[base->fsTimerIndex] = 0; - base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0; - base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0; - base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCFG[base->fsTimerIndex] = 0; + base->flexioBase->TIMCMP[base->fsTimerIndex] = 0; + base->flexioBase->TIMCTL[base->fsTimerIndex] = 0; + base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; } /*! @@ -315,7 +315,7 @@ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) * * param base Pointer to FLEXIO_I2S_Type structure * return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. -*/ + */ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) { uint32_t status = 0; @@ -355,10 +355,10 @@ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) * param base Pointer to FLEXIO_I2S_Type structure * param format Pointer to FlexIO I2S audio data format structure. * param srcClock_Hz I2S master clock source frequency in Hz. -*/ + */ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) { - uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U); + uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U); uint32_t bclkDiv = 0; /* Shall keep bclk and fs div an integer */ @@ -370,7 +370,7 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U); /* Set bit clock timer cmp */ - bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U)); + bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U)); base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); } @@ -382,7 +382,7 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form * * param base Pointer to FLEXIO_I2S_Type structure * param format Pointer to FlexIO I2S audio data format structure. -*/ + */ void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) { /* Set Frame sync timer cmp */ @@ -404,7 +404,7 @@ void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *forma */ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) { - uint32_t i = 0; + uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; for (i = 0; i < size / bytesPerWord; i++) @@ -436,7 +436,7 @@ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t * */ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) { - uint32_t i = 0; + uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; for (i = 0; i < size / bytesPerWord; i++) @@ -537,7 +537,7 @@ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, * param handle FlexIO I2S handle pointer. * param format Pointer to audio data format structure. * param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. -*/ + */ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, @@ -591,10 +591,10 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, } /* Add into queue */ - handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].data = xfer->data; handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; /* Set the state to busy */ handle->state = kFLEXIO_I2S_Busy; @@ -639,10 +639,10 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, } /* Add into queue */ - handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].data = xfer->data; handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; /* Set state to busy */ handle->state = kFLEXIO_I2S_Busy; @@ -676,7 +676,7 @@ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *ha /* Clear the queue */ memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -699,7 +699,7 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t /* Clear the queue */ memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -767,9 +767,9 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) assert(i2sHandle); flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; - FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; - uint8_t *buffer = handle->queue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; /* Handle error */ if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex)) @@ -787,7 +787,7 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) handle->queue[handle->queueDriver].data += dataSize; } - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) { memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); @@ -816,9 +816,9 @@ void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) assert(i2sHandle); flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; - FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; - uint8_t *buffer = handle->queue[handle->queueDriver].data; - uint8_t dataSize = handle->bitWidth / 8U; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; /* Handle transfer */ if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) && @@ -831,7 +831,7 @@ void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) handle->queue[handle->queueDriver].data += dataSize; } - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) { memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h index 6d9a713cb5f17..32e792596b475 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h @@ -29,10 +29,10 @@ /*! @brief FlexIO I2S transfer status */ enum _flexio_i2s_status { - kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ - kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ - kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ - kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ + kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ + kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */ }; @@ -54,21 +54,21 @@ typedef struct _flexio_i2s_type typedef enum _flexio_i2s_master_slave { kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */ - kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ + kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ } flexio_i2s_master_slave_t; /*! @brief Define FlexIO FlexIO I2S interrupt mask. */ enum _flexio_i2s_interrupt_enable { kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ + kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ }; /*! @brief Define FlexIO FlexIO I2S status mask. */ enum _flexio_i2s_status_flags { kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ }; /*! @brief FlexIO I2S configure structure */ @@ -97,22 +97,22 @@ typedef struct _flexio_i2s_format /*! @brief Audio sample rate */ typedef enum _flexio_i2s_sample_rate { - kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ - kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ - kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ - kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ - kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ - kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ - kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ + kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ } flexio_i2s_sample_rate_t; /*! @brief Audio word width */ typedef enum _flexio_i2s_word_width { - kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */ @@ -172,7 +172,7 @@ extern "C" { * * @param base FlexIO I2S base pointer * @param config FlexIO I2S configure structure. -*/ + */ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config); /*! @@ -193,7 +193,7 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config); * call the FLEXO_I2S_Init to use the FlexIO I2S module. * * @param base FlexIO I2S base pointer -*/ + */ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); /*! @@ -201,7 +201,7 @@ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); * * @param base Pointer to FLEXIO_I2S_Type * @param enable True to enable, false dose not have any effect. -*/ + */ static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) { if (enable) @@ -222,7 +222,7 @@ static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) * * @param base Pointer to FLEXIO_I2S_Type structure * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. -*/ + */ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base); /*! @} */ @@ -323,7 +323,7 @@ static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base * @param base Pointer to FLEXIO_I2S_Type structure * @param format Pointer to FlexIO I2S audio data format structure. * @param srcClock_Hz I2S master clock source frequency in Hz. -*/ + */ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz); /*! @@ -334,7 +334,7 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form * * @param base Pointer to FLEXIO_I2S_Type structure * @param format Pointer to FlexIO I2S audio data format structure. -*/ + */ void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format); /*! @@ -418,7 +418,7 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, * @param handle FlexIO I2S handle pointer. * @param format Pointer to audio data format structure. * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. -*/ + */ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c index 253f278f9e1e9..5774768afe0d4 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c @@ -59,14 +59,14 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds); /******************************************************************************* -* Code -******************************************************************************/ + * Code + ******************************************************************************/ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData; - flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; + flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; if (flexio_i2sHandle->callback) @@ -84,9 +84,9 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData; - flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; + flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; if (flexio_i2sHandle->callback) @@ -127,13 +127,13 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, /* Set flexio_i2s base to handle */ handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; /* Set FLEXIO I2S state to idle */ handle->state = kFLEXIO_I2S_Idle; - s_edmaPrivateHandle[0].base = base; + s_edmaPrivateHandle[0].base = base; s_edmaPrivateHandle[0].handle = handle; /* Need to use scatter gather */ @@ -169,13 +169,13 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, /* Set flexio_i2s base to handle */ handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; /* Set FLEXIO I2S state to idle */ handle->state = kFLEXIO_I2S_Idle; - s_edmaPrivateHandle[1].base = base; + s_edmaPrivateHandle[1].base = base; s_edmaPrivateHandle[1].handle = handle; /* Need to use scatter gather */ @@ -197,7 +197,7 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, * param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. * retval kStatus_Success Audio format set successfully. * retval kStatus_InvalidArgument The input arguments is invalid. -*/ + */ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, @@ -216,7 +216,7 @@ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, FLEXIO_I2S_SlaveSetFormat(base, format); } - /* Get the tranfer size from format, this should be used in EDMA configuration */ + /* Get the transfer size from format, this should be used in EDMA configuration */ handle->bytesPerFrame = format->bitWidth / 8U; } @@ -240,7 +240,7 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -257,10 +257,10 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, handle->state = kFLEXIO_I2S_Busy; /* Update the queue state */ - handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].data = xfer->data; handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; /* Prepare edma configure */ EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, @@ -304,7 +304,7 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base); + uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base); /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -321,10 +321,10 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, handle->state = kFLEXIO_I2S_Busy; /* Update queue state */ - handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].data = xfer->data; handle->queue[handle->queueUser].dataSize = xfer->dataSize; - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; /* Prepare edma configure */ EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h index 47221dac85b2e..817f1970592bf 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h @@ -112,7 +112,7 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. * @retval kStatus_Success Audio format set successfully. * @retval kStatus_InvalidArgument The input arguments is invalid. -*/ + */ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c index af8d08e42e32f..f21de1fd022e6 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c @@ -179,7 +179,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma flexio_shifter_config_t shifterConfig; flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; + uint32_t ctrlReg = 0; uint16_t timerDiv = 0; uint16_t timerCmp = 0; @@ -207,34 +207,34 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma /* Do hardware configuration. */ /* 1. Configure the shifter 0 for tx. */ shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; } else { shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; } FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { @@ -248,20 +248,20 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); /*3. Configure the timer 0 for SCK. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; timerDiv = timerDiv / 2 - 1; @@ -274,20 +274,20 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); /* 4. Configure the timer 1 for CSn. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutput; - timerConfig.pinSelect = base->CSnPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; timerConfig.timerCompare = 0xFFFFU; @@ -298,19 +298,19 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma * brief Resets the FlexIO SPI timer and shifter config. * * param base Pointer to the FLEXIO_SPI_Type. -*/ + */ void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) { base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; } /*! @@ -330,9 +330,9 @@ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) /* Initializes the configure structure to zero. */ memset(masterConfig, 0, sizeof(*masterConfig)); - masterConfig->enableMaster = true; - masterConfig->enableInDoze = false; - masterConfig->enableInDebug = true; + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; masterConfig->enableFastAccess = false; /* Default baud rate 500kbps. */ masterConfig->baudRate_Bps = 500000U; @@ -407,8 +407,8 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav /* Do hardware configuration. */ /* 1. Configure the shifter 0 for tx. */ shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; @@ -416,24 +416,24 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; } else { shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; } FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); /* 2. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[0]; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->SDIPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { @@ -447,29 +447,29 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); /*3. Configure the timer 0 for shift clock. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->SCKPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; - timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; } else { timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; } timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; @@ -481,7 +481,7 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav * brief Gates the FlexIO clock. * * param base Pointer to the FLEXIO_SPI_Type. -*/ + */ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) { FLEXIO_SPI_MasterDeinit(base); @@ -504,9 +504,9 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) /* Initializes the configure structure to zero. */ memset(slaveConfig, 0, sizeof(*slaveConfig)); - slaveConfig->enableSlave = true; - slaveConfig->enableInDoze = false; - slaveConfig->enableInDebug = true; + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; slaveConfig->enableFastAccess = false; /* Default CPHA = 0. */ slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; @@ -586,12 +586,12 @@ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) * return status flag; Use the status flag to AND the following flag mask and get the status. * arg kFLEXIO_SPI_TxEmptyFlag * arg kFLEXIO_SPI_RxEmptyFlag -*/ + */ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) { uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); - uint32_t status = 0; + uint32_t status = 0; status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); @@ -607,7 +607,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) * The parameter can be any combination of the following values: * arg kFLEXIO_SPI_TxEmptyFlag * arg kFLEXIO_SPI_RxEmptyFlag -*/ + */ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) { @@ -630,8 +630,8 @@ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) */ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) { - uint16_t timerDiv = 0; - uint16_t timerCmp = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; FLEXIO_Type *flexioBase = base->flexioBase; /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ @@ -716,40 +716,40 @@ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfe uint8_t bytesPerFrame; uint32_t dataMode = 0; uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; timerCmp &= 0x00FFU; /* Configure the values in handle. */ switch (xfer->flags) { case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; + direction = kFLEXIO_SPI_LsbFirst; break; case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; + dataMode = (16 * 2 - 1U) << 8U; bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; + dataMode = (16 * 2 - 1U) << 8U; bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; + direction = kFLEXIO_SPI_LsbFirst; break; default: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; assert(true); break; } @@ -880,7 +880,7 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, uint32_t dataMode = 0; uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; - uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; timerCmp &= 0x00FFU; @@ -900,29 +900,29 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, switch (xfer->flags) { case kFLEXIO_SPI_8bitMsb: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_8bitLsb: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; + handle->direction = kFLEXIO_SPI_LsbFirst; break; case kFLEXIO_SPI_16bitMsb: - dataMode = (16 * 2 - 1U) << 8U; + dataMode = (16 * 2 - 1U) << 8U; handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_16bitLsb: - dataMode = (16 * 2 - 1U) << 8U; + dataMode = (16 * 2 - 1U) << 8U; handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; + handle->direction = kFLEXIO_SPI_LsbFirst; break; default: - dataMode = (8 * 2 - 1U) << 8U; + dataMode = (8 * 2 - 1U) << 8U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; assert(true); break; } @@ -932,9 +932,9 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, /* Configure transfer size. */ base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; handle->rxRemainingBytes = xfer->dataSize; /* Save total transfer size. */ @@ -1050,7 +1050,7 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) return; } - base = (FLEXIO_SPI_Type *)spiType; + base = (FLEXIO_SPI_Type *)spiType; status = FLEXIO_SPI_GetStatusFlags(base); /* Handle rx. */ @@ -1147,29 +1147,29 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, switch (xfer->flags) { case kFLEXIO_SPI_8bitMsb: - dataMode = 8 * 2 - 1U; + dataMode = 8 * 2 - 1U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_8bitLsb: - dataMode = 8 * 2 - 1U; + dataMode = 8 * 2 - 1U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_LsbFirst; + handle->direction = kFLEXIO_SPI_LsbFirst; break; case kFLEXIO_SPI_16bitMsb: - dataMode = 16 * 2 - 1U; + dataMode = 16 * 2 - 1U; handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_16bitLsb: - dataMode = 16 * 2 - 1U; + dataMode = 16 * 2 - 1U; handle->bytePerFrame = 2U; - handle->direction = kFLEXIO_SPI_LsbFirst; + handle->direction = kFLEXIO_SPI_LsbFirst; break; default: - dataMode = 8 * 2 - 1U; + dataMode = 8 * 2 - 1U; handle->bytePerFrame = 1U; - handle->direction = kFLEXIO_SPI_MsbFirst; + handle->direction = kFLEXIO_SPI_MsbFirst; assert(true); break; } @@ -1177,9 +1177,9 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, /* Configure transfer size. */ base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; - handle->state = kFLEXIO_SPI_Busy; - handle->txData = xfer->txData; - handle->rxData = xfer->rxData; + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; handle->txRemainingBytes = xfer->dataSize; handle->rxRemainingBytes = xfer->dataSize; @@ -1212,7 +1212,7 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) return; } - base = (FLEXIO_SPI_Type *)spiType; + base = (FLEXIO_SPI_Type *)spiType; status = FLEXIO_SPI_GetStatusFlags(base); /* Handle tx. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.h index 96cea3a940bf1..575ac0bd141ff 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,8 +35,8 @@ /*! @brief Error codes for the FlexIO SPI driver. */ enum _flexio_spi_status { - kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ - kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ }; @@ -44,9 +44,9 @@ enum _flexio_spi_status typedef enum _flexio_spi_clock_phase { kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first - * cycle of a data transfer. */ + * cycle of a data transfer. */ kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the - * first cycle of a data transfer. */ + * first cycle of a data transfer. */ } flexio_spi_clock_phase_t; /*! @brief FlexIO SPI data shifter direction options. */ @@ -59,7 +59,7 @@ typedef enum _flexio_spi_shift_direction /*! @brief FlexIO SPI data length mode options. */ typedef enum _flexio_spi_data_bitcount_mode { - kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ } flexio_spi_data_bitcount_mode_t; @@ -67,29 +67,29 @@ typedef enum _flexio_spi_data_bitcount_mode enum _flexio_spi_interrupt_enable { kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ }; /*! @brief Define FlexIO SPI status mask. */ enum _flexio_spi_status_flags { kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ }; /*! @brief Define FlexIO SPI DMA mask. */ enum _flexio_spi_dma_enable { - kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ - kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ }; /*! @brief Define FlexIO SPI transfer flags. */ enum _flexio_spi_transfer_flags { - kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ - kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ }; @@ -230,7 +230,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma * @brief Resets the FlexIO SPI timer and shifter config. * * @param base Pointer to the FLEXIO_SPI_Type. -*/ + */ void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); /*! @@ -284,7 +284,7 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav * @brief Gates the FlexIO clock. * * @param base Pointer to the FLEXIO_SPI_Type. -*/ + */ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); /*! @@ -313,7 +313,7 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); * @return status flag; Use the status flag to AND the following flag mask and get the status. * @arg kFLEXIO_SPI_TxEmptyFlag * @arg kFLEXIO_SPI_RxEmptyFlag -*/ + */ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); @@ -325,7 +325,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); * The parameter can be any combination of the following values: * @arg kFLEXIO_SPI_TxEmptyFlag * @arg kFLEXIO_SPI_RxEmptyFlag -*/ + */ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); @@ -435,7 +435,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base * * @param base Pointer to the FLEXIO_SPI_Type. * @param enable True to enable, false does not have any effect. -*/ + */ static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) { if (enable) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c index 916b8c0cfc3f5..e680b53371601 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c @@ -69,12 +69,12 @@ static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA; static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT]; /******************************************************************************* -* Code -******************************************************************************/ + * Code + ******************************************************************************/ static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) { - tcds = tcds; + tcds = tcds; flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; /* Disable Tx DMA */ @@ -99,7 +99,7 @@ static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool t static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) { - tcds = tcds; + tcds = tcds; flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; if (transferDone) @@ -126,7 +126,7 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer) { - edma_transfer_config_t xferConfig = {0}; + edma_transfer_config_t xferConfig = {0}; flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; uint8_t bytesPerFrame; @@ -135,23 +135,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, { case kFLEXIO_SPI_8bitMsb: bytesPerFrame = 1; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_8bitLsb: bytesPerFrame = 1; - direction = kFLEXIO_SPI_LsbFirst; + direction = kFLEXIO_SPI_LsbFirst; break; case kFLEXIO_SPI_16bitMsb: bytesPerFrame = 2; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; break; case kFLEXIO_SPI_16bitLsb: bytesPerFrame = 2; - direction = kFLEXIO_SPI_LsbFirst; + direction = kFLEXIO_SPI_LsbFirst; break; default: bytesPerFrame = 1U; - direction = kFLEXIO_SPI_MsbFirst; + direction = kFLEXIO_SPI_MsbFirst; assert(true); break; } @@ -160,13 +160,13 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, handle->transferSize = xfer->dataSize; /* Configure tx transfer EDMA. */ - xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); xferConfig.destOffset = 0; if (bytesPerFrame == 1U) { - xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - xferConfig.minorLoopBytes = 1; + xferConfig.minorLoopBytes = 1; } else { @@ -174,22 +174,22 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, { xferConfig.destAddr -= 1U; } - xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - xferConfig.minorLoopBytes = 2; + xferConfig.minorLoopBytes = 2; } /* Configure DMA channel. */ if (xfer->txData) { xferConfig.srcOffset = bytesPerFrame; - xferConfig.srcAddr = (uint32_t)(xfer->txData); + xferConfig.srcAddr = (uint32_t)(xfer->txData); } else { /* Disable the source increasement and source set to dummyData. */ xferConfig.srcOffset = 0; - xferConfig.srcAddr = (uint32_t)(&s_dummyData); + xferConfig.srcAddr = (uint32_t)(&s_dummyData); } xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); @@ -213,8 +213,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, xferConfig.srcAddr -= 1U; } } - xferConfig.srcOffset = 0; - xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.srcOffset = 0; + xferConfig.destAddr = (uint32_t)(xfer->rxData); xferConfig.destOffset = bytesPerFrame; EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); handle->rxInProgress = true; @@ -264,7 +264,7 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, { if (s_edmaPrivateHandle[index].base == NULL) { - s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].base = base; s_edmaPrivateHandle[index].handle = handle; break; } @@ -381,15 +381,15 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, if (handle->rxInProgress) { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel)); + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->rxHandle->base, handle->rxHandle->channel)); } else { - *count = (handle->transferSize - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel)); + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->txHandle->base, handle->txHandle->channel)); } return kStatus_Success; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.h index 4afecc7d10c59..79c6e2352368e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_SPI_EDMA_H_ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c index 101087fa06c07..41d872add9b88 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c @@ -125,10 +125,10 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us flexio_shifter_config_t shifterConfig; flexio_timer_config_t timerConfig; - uint32_t ctrlReg = 0; + uint32_t ctrlReg = 0; uint16_t timerDiv = 0; uint16_t timerCmp = 0; - status_t result = kStatus_Success; + status_t result = kStatus_Success; /* Clear the shifterConfig & timerConfig struct. */ memset(&shifterConfig, 0, sizeof(shifterConfig)); @@ -153,33 +153,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us /* Do hardware configuration. */ /* 1. Configure the shifter 0 for tx. */ - shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerSelect = base->timerIndex[0]; shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; - shifterConfig.pinSelect = base->TxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); /*2. Configure the timer 0 for tx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->TxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetNever; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; timerDiv = srcClock_Hz / userConfig->baudRate_Bps; timerDiv = timerDiv / 2 - 1; @@ -197,33 +197,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); /* 3. Configure the shifter 1 for rx. */ - shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerSelect = base->timerIndex[1]; shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; - shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - shifterConfig.pinSelect = base->RxPinIndex; - shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; - shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; - shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; - shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; - shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); /* 4. Configure the timer 1 for rx. */ - timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; - timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; - timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; - timerConfig.pinSelect = base->RxPinIndex; - timerConfig.pinPolarity = kFLEXIO_PinActiveLow; - timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; - timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; - timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; - timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; - timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; - timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; - timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; - timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; timerConfig.timerCompare = timerCmp; @@ -238,19 +238,19 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. * * param base Pointer to FLEXIO_UART_Type structure -*/ + */ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) { base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; - base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; - base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; - base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; /* Clear the shifter flag. */ base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); @@ -276,9 +276,9 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) /* Initializes the configure structure to zero. */ memset(userConfig, 0, sizeof(*userConfig)); - userConfig->enableUart = true; - userConfig->enableInDoze = false; - userConfig->enableInDebug = true; + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; userConfig->enableFastAccess = false; /* Default baud rate 115200. */ userConfig->baudRate_Bps = 115200U; @@ -331,7 +331,7 @@ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) * * param base Pointer to the FLEXIO_UART_Type structure. * return FlexIO UART status flags. -*/ + */ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) { @@ -356,7 +356,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) * arg kFLEXIO_UART_TxDataRegEmptyFlag * arg kFLEXIO_UART_RxEmptyFlag * arg kFLEXIO_UART_RxOverRunFlag -*/ + */ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) { @@ -498,7 +498,7 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, /* Setup the ringbuffer address */ if (ringBuffer) { - handle->rxRingBuffer = ringBuffer; + handle->rxRingBuffer = ringBuffer; handle->rxRingBufferSize = ringBufferSize; handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; @@ -525,7 +525,7 @@ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_hand FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); } - handle->rxRingBuffer = NULL; + handle->rxRingBuffer = NULL; handle->rxRingBufferSize = 0U; handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; @@ -567,10 +567,10 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, } else { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; handle->txDataSizeAll = xfer->dataSize; - handle->txState = kFLEXIO_UART_TxBusy; + handle->txState = kFLEXIO_UART_TxBusy; /* Enable transmiter interrupt. */ FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); @@ -596,7 +596,7 @@ void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); handle->txDataSize = 0; - handle->txState = kFLEXIO_UART_TxIdle; + handle->txState = kFLEXIO_UART_TxIdle; } /*! @@ -686,7 +686,7 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, } else { - bytesToReceive = xfer->dataSize; + bytesToReceive = xfer->dataSize; bytesCurrentReceived = 0U; /* If RX ring buffer is used. */ @@ -725,10 +725,10 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, if (bytesToReceive) { /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; + handle->rxState = kFLEXIO_UART_RxBusy; } /* Enable FLEXIO_UART RX IRQ if previously enabled. */ @@ -746,10 +746,10 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, /* Ring buffer not used. */ else { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kFLEXIO_UART_RxBusy; + handle->rxState = kFLEXIO_UART_RxBusy; /* Enable RX interrupt. */ FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); @@ -785,7 +785,7 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle } handle->rxDataSize = 0U; - handle->rxState = kFLEXIO_UART_RxIdle; + handle->rxState = kFLEXIO_UART_RxIdle; } /*! @@ -824,8 +824,8 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart */ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) { - uint8_t count = 1; - FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; /* Read the status back. */ @@ -881,7 +881,7 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) } } - /* If ring buffer is still full after callback function, the oldest data is overrided. */ + /* If ring buffer is still full after callback function, the oldest data is overridden. */ if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) { /* Increase handle->rxRingBufferTail to make room for new data. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h index b9c5622cef9d7..0634c62c6978c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h @@ -34,7 +34,7 @@ enum _flexio_uart_status kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ - kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ kStatus_FLEXIO_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ @@ -52,15 +52,15 @@ typedef enum _flexio_uart_bit_count_per_char enum _flexio_uart_interrupt_enable { kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ - kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ }; /*! @brief Define FlexIO UART status mask. */ enum _flexio_uart_status_flags { kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ - kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ - kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ }; /*! @brief Define FlexIO UART access structure typedef. */ @@ -176,7 +176,7 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. * * @param base Pointer to FLEXIO_UART_Type structure -*/ + */ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); /*! @@ -203,7 +203,7 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); * * @param base Pointer to the FLEXIO_UART_Type structure. * @return FlexIO UART status flags. -*/ + */ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); @@ -216,7 +216,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); * @arg kFLEXIO_UART_TxDataRegEmptyFlag * @arg kFLEXIO_UART_RxEmptyFlag * @arg kFLEXIO_UART_RxOverRunFlag -*/ + */ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); @@ -318,7 +318,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) * * @param base Pointer to the FLEXIO_UART_Type. * @param enable True to enable, false does not have any effect. -*/ + */ static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) { if (enable) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c index 4bec051160a1a..bb8b1ee30ffc0 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c @@ -84,7 +84,7 @@ static void FLEXIO_UART_TransferSendEDMACallback(edma_handle_t *handle, void *pa /* Avoid the warning for unused variables. */ handle = handle; - tcds = tcds; + tcds = tcds; if (transferDone) { @@ -109,7 +109,7 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, /* Avoid the warning for unused variables. */ handle = handle; - tcds = tcds; + tcds = tcds; if (transferDone) { @@ -152,7 +152,7 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, { if (s_edmaPrivateHandle[index].base == NULL) { - s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].base = base; s_edmaPrivateHandle[index].handle = handle; break; } @@ -223,7 +223,7 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, } else { - handle->txState = kFLEXIO_UART_TxBusy; + handle->txState = kFLEXIO_UART_TxBusy; handle->txDataSizeAll = xfer->dataSize; /* Prepare transfer. */ @@ -281,7 +281,7 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, } else { - handle->rxState = kFLEXIO_UART_RxBusy; + handle->rxState = kFLEXIO_UART_RxBusy; handle->rxDataSizeAll = xfer->dataSize; /* Prepare transfer. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.h index da577d0ff9c8f..5a6b36f6eb22c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_FLEXIO_UART_EDMA_H_ @@ -36,8 +36,8 @@ typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, void *userData); /*! -* @brief UART eDMA handle -*/ + * @brief UART eDMA handle + */ struct _flexio_uart_edma_handle { flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c index a2f68853589e4..ee93440d94a82 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c @@ -34,7 +34,7 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); * * @param tcmBankNum tcm banknumber * @retval register value correspond to the tcm size - */ + */ static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum); /******************************************************************************* @@ -175,8 +175,8 @@ status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) { assert(config != NULL); - uint8_t dtcmBankNum = config->dtcmBankNum; - uint8_t itcmBankNum = config->itcmBankNum; + uint8_t dtcmBankNum = config->dtcmBankNum; + uint8_t itcmBankNum = config->itcmBankNum; uint8_t ocramBankNum = config->ocramBankNum; uint32_t bankCfg = 0U, i = 0U; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h index 0963e76df66b6..f5e1859e9fbc7 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h @@ -29,7 +29,7 @@ /*! @brief flexram write read sel */ enum _flexram_wr_rd_sel { - kFLEXRAM_Read = 0U, /*!< read */ + kFLEXRAM_Read = 0U, /*!< read */ kFLEXRAM_Write = 1U, /*!< write */ }; @@ -37,20 +37,20 @@ enum _flexram_wr_rd_sel enum _flexram_interrupt_status { kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ - kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ - kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ + kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ + kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */ }; /*! @brief FLEXRAM TCM access mode -* Fast access mode expected to be finished in 1-cycle -* Wait access mode expected to be finished in 2-cycle -* Wait access mode is a feature of the flexram and it should be used when -* the cpu clock too fast to finish tcm access in 1-cycle. -* Normally, fast mode is the default mode, the efficiency of the tcm access will better. -*/ + * Fast access mode expected to be finished in 1-cycle + * Wait access mode expected to be finished in 2-cycle + * Wait access mode is a feature of the flexram and it should be used when + * the cpu clock too fast to finish tcm access in 1-cycle. + * Normally, fast mode is the default mode, the efficiency of the tcm access will better. + */ typedef enum _flexram_tcm_access_mode { kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */ @@ -61,16 +61,16 @@ typedef enum _flexram_tcm_access_mode enum _flexram_bank_type { kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ - kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ - kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ - kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ + kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ + kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ + kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ }; /*! @brief FLEXRAM tcm support size */ enum _flexram_tcm_size { - kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */ - kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */ + kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */ + kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */ kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */ kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */ kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */ @@ -80,7 +80,7 @@ enum _flexram_tcm_size typedef enum _flexram_bank_allocate_src { kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ - kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ + kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ } flexram_bank_allocate_src_t; /*! @brief FLEXRAM allocate ocram, itcm, dtcm size */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c index a1fc50fb69254..33bd4b8a28122 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c @@ -42,9 +42,9 @@ enum _flexspi_flag_constants enum _flexspi_transfer_state { - kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ + kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ - kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ + kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ }; /*! @brief Typedef for interrupt handler. */ @@ -54,26 +54,26 @@ typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, void *flexspiHandle); * Prototypes ******************************************************************************/ /*! -* @brief Get the instance number for FLEXSPI. -* -* @param base FLEXSPI base pointer. -*/ + * @brief Get the instance number for FLEXSPI. + * + * @param base FLEXSPI base pointer. + */ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); /*! -* @brief Configure flash A/B sample clock DLL. -* -* @param base FLEXSPI base pointer. -* @param config Flash configuration parameters. -*/ + * @brief Configure flash A/B sample clock DLL. + * + * @param base FLEXSPI base pointer. + * @param config Flash configuration parameters. + */ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config); /*! -* @brief Check and clear IP command execution errors. -* -* @param base FLEXSPI base pointer. -* @param status interrupt status. -*/ + * @brief Check and clear IP command execution errors. + * + * @param base FLEXSPI base pointer. + * @param status interrupt status. + */ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); /******************************************************************************* @@ -159,7 +159,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t } else { - temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */ + temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */ dllValue = temp / kFLEXSPI_DelayCellUnitMin; if (dllValue * kFLEXSPI_DelayCellUnitMin < temp) { @@ -220,7 +220,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) { uint32_t configValue = 0; - uint8_t i = 0; + uint8_t i = 0; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the flexspi clock */ @@ -306,32 +306,32 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; - config->enableSckFreeRunning = false; - config->enableCombination = false; - config->enableDoze = true; - config->enableHalfSpeedAccess = false; - config->enableSckBDiffOpt = false; - config->enableSameConfigForAll = false; - config->seqTimeoutCycle = 0xFFFFU; - config->ipGrantTimeoutCycle = 0xFFU; - config->txWatermark = 8; - config->rxWatermark = 8; + config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; + config->enableSckFreeRunning = false; + config->enableCombination = false; + config->enableDoze = true; + config->enableHalfSpeedAccess = false; + config->enableSckBDiffOpt = false; + config->enableSameConfigForAll = false; + config->seqTimeoutCycle = 0xFFFFU; + config->ipGrantTimeoutCycle = 0xFFU; + config->txWatermark = 8; + config->rxWatermark = 8; config->ahbConfig.enableAHBWriteIpTxFifo = false; config->ahbConfig.enableAHBWriteIpRxFifo = false; - config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; - config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; - config->ahbConfig.resumeWaitCycle = 0x20U; + config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; + config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; + config->ahbConfig.resumeWaitCycle = 0x20U; memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) { config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/ } config->ahbConfig.enableClearAHBBufferOpt = false; - config->ahbConfig.enableReadAddressOpt = false; - config->ahbConfig.enableAHBPrefetch = false; - config->ahbConfig.enableAHBBufferable = false; - config->ahbConfig.enableAHBCachable = false; + config->ahbConfig.enableReadAddressOpt = false; + config->ahbConfig.enableAHBPrefetch = false; + config->ahbConfig.enableAHBBufferable = false; + config->ahbConfig.enableAHBCachable = false; } /*! @@ -360,7 +360,7 @@ void FLEXSPI_Deinit(FLEXSPI_Type *base) void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) { uint32_t configValue = 0; - uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ + uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ /* Wait for bus idle before change flash configuration. */ while (!FLEXSPI_GetBusIdleStatus(base)) @@ -428,14 +428,14 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, } /*! brief Updates the LUT table. -* -* param base FLEXSPI peripheral base address. -* param index From which index start to update. It could be any index of the LUT table, which -* also allows user to update command content inside a command. Each command consists of up to -* 8 instructions and occupy 4*32-bit memory. -* param cmd Command sequence array. -* param count Number of sequences. -*/ + * + * param base FLEXSPI peripheral base address. + * param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * param cmd Command sequence array. + * param count Number of sequences. + */ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) { assert(index < 64U); @@ -450,7 +450,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, /* Unlock LUT for update. */ base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x02; + base->LUTCR = 0x02; lutBase = &base->LUT[index]; for (i = 0; i < count; i++) @@ -460,7 +460,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, /* Lock LUT. */ base->LUTKEY = FLEXSPI_LUT_KEY_VAL; - base->LUTCR = 0x01; + base->LUTCR = 0x01; } /*! @@ -479,7 +479,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; uint32_t status; status_t result = kStatus_Success; - uint32_t i = 0; + uint32_t i = 0; /* Send data buffer */ while (size) @@ -538,7 +538,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; uint32_t status; status_t result = kStatus_Success; - uint32_t i = 0; + uint32_t i = 0; /* Send data buffer */ while (size) @@ -611,20 +611,20 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected -*/ + */ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) { uint32_t configValue = 0; - status_t result = kStatus_Success; + status_t result = kStatus_Success; /* Clear sequence pointer before sending data to external devices. */ base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - /* Clear former pending status before start this tranfer. */ + /* Clear former pending status before start this transfer. */ base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | FLEXSPI_INTR_IPCMDGE_MASK; - /* Configure base addresss. */ + /* Configure base address. */ base->IPCR0 = xfer->deviceAddress; /* Reset fifos. */ @@ -691,7 +691,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, /* Set callback and userData. */ handle->completionCallback = callback; - handle->userData = userData; + handle->userData = userData; #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ /* Save the context in global variables to support the double weak mechanism. */ @@ -720,7 +720,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) { uint32_t configValue = 0; - status_t result = kStatus_Success; + status_t result = kStatus_Success; assert(handle); assert(xfer); @@ -732,19 +732,19 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl } else { - handle->data = xfer->data; - handle->dataSize = xfer->dataSize; + handle->data = xfer->data; + handle->dataSize = xfer->dataSize; handle->transferTotalSize = xfer->dataSize; - handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite; + handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite; /* Clear sequence pointer before sending data to external devices. */ base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; - /* Clear former pending status before start this tranfer. */ + /* Clear former pending status before start this transfer. */ base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | FLEXSPI_INTR_IPCMDGE_MASK; - /* Configure base addresss. */ + /* Configure base address. */ base->IPCR0 = xfer->deviceAddress; /* Reset fifos. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h index d355462a91df2..c30f934adfb33 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h @@ -38,7 +38,7 @@ /*! @brief Status structure of FLEXSPI.*/ enum _flexspi_status { - kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ + kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout error occurred during FLEXSPI transfer. */ kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution @@ -50,33 +50,33 @@ enum _flexspi_status /*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */ enum _flexspi_command { - kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ - kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ - kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ - kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ - kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ - kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ - kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ - kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ - kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ + kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ + kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ + kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ + kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ + kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ + kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ + kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS. */ - kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ - kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ - kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ - kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ - kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ - kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ - kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ - kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ + kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ + kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ + kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ + kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ + kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ + kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS. */ kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the @@ -95,8 +95,8 @@ enum _flexspi_pad /*! @brief FLEXSPI interrupt status flags.*/ typedef enum _flexspi_flags { - kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ - kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ + kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ + kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ kFLEXSPI_SckStoppedBecauseTxEmptyFlag = FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command sequence because Async TX FIFO empty. */ @@ -106,7 +106,7 @@ typedef enum _flexspi_flags #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ #endif - kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ + kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ kFLEXSPI_AhbCommandSequenceErrorFlag = FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ @@ -127,36 +127,36 @@ typedef enum _flexspi_read_sample_clock and loopback internally. */ kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. */ - kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ + kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ } flexspi_read_sample_clock_t; /*! @brief FLEXSPI interval unit for flash device select.*/ typedef enum _flexspi_cs_interval_cycle_unit { - kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ + kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ } flexspi_cs_interval_cycle_unit_t; /*! @brief FLEXSPI AHB wait interval unit for writting.*/ typedef enum _flexspi_ahb_write_wait_unit { - kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ - kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ } flexspi_ahb_write_wait_unit_t; /*! @brief Error Code when IP command Error detected.*/ typedef enum _flexspi_ip_error_code { - kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ - kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ - kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ + kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. */ kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR @@ -164,16 +164,16 @@ typedef enum _flexspi_ip_error_code kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole flash address range (A1/A2/B1/B2). */ kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ - kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ + kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ } flexspi_ip_error_code_t; /*! @brief Error Code when AHB command Error detected.*/ typedef enum _flexspi_ahb_error_code { - kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction used in the sequence. */ - kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. */ kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR @@ -194,9 +194,9 @@ typedef enum _flexspi_port /*! @brief Trigger source of current command sequence granted by arbitrator.*/ typedef enum _flexspi_arb_command_source { - kFLEXSPI_AhbReadCommand = 0x0U, - kFLEXSPI_AhbWriteCommand = 0x1U, - kFLEXSPI_IpCommand = 0x2U, + kFLEXSPI_AhbReadCommand = 0x0U, + kFLEXSPI_AhbWriteCommand = 0x1U, + kFLEXSPI_IpCommand = 0x2U, kFLEXSPI_SuspendedCommand = 0x3U, } flexspi_arb_command_source_t; @@ -673,14 +673,14 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable } /*! @brief Updates the LUT table. -* -* @param base FLEXSPI peripheral base address. -* @param index From which index start to update. It could be any index of the LUT table, which -* also allows user to update command content inside a command. Each command consists of up to -* 8 instructions and occupy 4*32-bit memory. -* @param cmd Command sequence array. -* @param count Number of sequences. -*/ + * + * @param base FLEXSPI peripheral base address. + * @param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * @param cmd Command sequence array. + * @param count Number of sequences. + */ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); /*! @@ -741,7 +741,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected -*/ + */ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); /*! @} */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c index 41b273f70b45a..0cec1a7597d66 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h index 6a85144b8503c..8427e43da2608 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c index 9569ce26bcb4f..a91e16377b1db 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c @@ -22,7 +22,7 @@ */ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) { - uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegNum = irqId / 32U; uint32_t irqRegShiftNum = irqId % 32U; assert(irqRegNum > 0U); @@ -50,7 +50,7 @@ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) */ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) { - uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegNum = irqId / 32U; uint32_t irqRegShiftNum = irqId % 32U; assert(irqRegNum > 0U); @@ -79,7 +79,7 @@ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) */ bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) { - uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegNum = irqId / 32U; uint32_t irqRegShiftNum = irqId % 32U; uint32_t ret; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.h b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.h index be9368a468b0e..09dbaa15debbb 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpc.h @@ -3,7 +3,7 @@ * Copyright 2016 NXP * All rights reserved. * - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c index 959f926c70728..bdfb89cda7335 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c @@ -26,15 +26,15 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* -* Prototypes -******************************************************************************/ + * Prototypes + ******************************************************************************/ /*! -* @brief Gets the GPIO instance according to the GPIO base -* -* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) -* @retval GPIO instance -*/ + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ static uint32_t GPIO_GetInstance(GPIO_Type *base); /******************************************************************************* diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h index 1ca8d2c16d391..be2e0bc192d10 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h @@ -29,18 +29,18 @@ /*! @brief GPIO direction definition. */ typedef enum _gpio_pin_direction { - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ } gpio_pin_direction_t; /*! @brief GPIO interrupt mode definition. */ typedef enum _gpio_interrupt_mode { - kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ - kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ - kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ - kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ - kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ } gpio_interrupt_mode_t; @@ -194,12 +194,12 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) */ /*! -* @brief Reads the current GPIO pin pad status. -* -* @param base GPIO base pointer. -* @param pin GPIO port pin number. -* @retval GPIO pin pad status value. -*/ + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) { assert(pin < 32); @@ -208,9 +208,9 @@ static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) } /*! -* @brief Reads the current GPIO pin pad status. -* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. -*/ + * @brief Reads the current GPIO pin pad status. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. + */ static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) { return GPIO_PinReadPadStatus(base, pin); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c index 57b13c42ee2fe..697be010a7bc4 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c @@ -116,12 +116,12 @@ void GPT_GetDefaultConfig(gpt_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->clockSource = kGPT_ClockSource_Periph; - config->divider = 1U; + config->clockSource = kGPT_ClockSource_Periph; + config->divider = 1U; config->enableRunInStop = true; config->enableRunInWait = true; config->enableRunInDoze = false; - config->enableRunInDbg = false; - config->enableFreeRun = false; - config->enableMode = true; + config->enableRunInDbg = false; + config->enableFreeRun = false; + config->enableMode = true; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.h b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.h index b01a4515c40d2..3666505905428 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_gpt.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,12 +31,12 @@ */ typedef enum _gpt_clock_source { - kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ - kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ + kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ + kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/ - kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ - kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ - kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ + kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ + kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ + kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ } gpt_clock_source_t; /*! @brief List of input capture channel number. */ @@ -67,10 +67,10 @@ typedef enum _gpt_output_compare_channel typedef enum _gpt_output_operation_mode { kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/ - kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ - kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ - kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ - kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ + kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ + kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ + kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ + kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ } gpt_output_operation_mode_t; /*! @brief List of GPT interrupts */ @@ -79,9 +79,9 @@ typedef enum _gpt_interrupt_enable kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/ kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/ kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/ - kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ - kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ - kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ + kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ } gpt_interrupt_enable_t; /*! @brief Status flag. */ @@ -90,9 +90,9 @@ typedef enum _gpt_status_flag kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/ kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/ kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/ - kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ - kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ - kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ + kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ + kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ + kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ } gpt_status_flag_t; /*! @brief Structure to configure the running mode. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c index 7c6470e9e9c22..a7c8b3475f7e7 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c @@ -138,8 +138,8 @@ void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) { assert(data); - uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK; - uint8_t columIndex = 0; + uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK; + uint8_t columIndex = 0; uint8_t activeColumn = (base->KPCR & KPP_KPCR_KCO_MASK) >> KPP_KPCR_KCO_SHIFT; uint8_t times; uint8_t rowData[KPP_KEYPAD_SCAN_TIMES][KPP_KEYPAD_COLUMNNUM_MAX]; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.h index d63648046bd60..e462a38f6335b 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_kpp.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_KPP_H_ @@ -32,15 +32,17 @@ * members. Members usually map to interrupt enable bits in one or more * peripheral registers. */ -typedef enum _kpp_interrupt_enable { +typedef enum _kpp_interrupt_enable +{ kKPP_keyDepressInterrupt = KPP_KPSR_KDIE_MASK, /*!< Keypad depress interrupt source */ kKPP_keyReleaseInterrupt = KPP_KPSR_KRIE_MASK /*!< Keypad release interrupt source */ } kpp_interrupt_enable_t; /*! @brief Lists of KPP synchronize chain operation. */ -typedef enum _kpp_sync_operation { +typedef enum _kpp_sync_operation +{ kKPP_ClearKeyDepressSyncChain = KPP_KPSR_KDSC_MASK, /*!< Keypad depress interrupt status. */ - kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */ + kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */ } kpp_sync_operation_t; /*! @brief Lists of KPP status. */ @@ -60,9 +62,9 @@ extern "C" { #endif /*! - * @name Initialization and De-initialization - * @{ - */ + * @name Initialization and De-initialization + * @{ + */ /*! * @brief KPP initialize. @@ -100,7 +102,7 @@ void KPP_Deinit(KPP_Type *base); static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask) { uint16_t data = base->KPSR & ~(KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); - base->KPSR = data | mask; + base->KPSR = data | mask; } /*! @@ -149,7 +151,7 @@ static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask) static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask) { uint16_t data = base->KPSR & (KPP_KPSR_KRSS_MASK | KPP_KPSR_KDSC_MASK | KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); - base->KPSR = data | mask; + base->KPSR = data | mask; } /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c index 27c80eb498863..6dde1c393c91e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c @@ -54,8 +54,8 @@ enum _lpi2c_master_fifo_cmd { kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ }; /*! @@ -185,7 +185,7 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, assert(prescaler > 0); uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); - uint32_t cycles = 0; + uint32_t cycles = 0; /* Search for the cycle count just below the desired glitch width. */ while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles)) @@ -352,19 +352,19 @@ void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) /* Initializes the configure structure to zero. */ memset(masterConfig, 0, sizeof(*masterConfig)); - masterConfig->enableMaster = true; - masterConfig->debugEnable = false; - masterConfig->enableDoze = true; - masterConfig->ignoreAck = false; - masterConfig->pinConfig = kLPI2C_2PinOpenDrain; - masterConfig->baudRate_Hz = 100000U; - masterConfig->busIdleTimeout_ns = 0; - masterConfig->pinLowTimeout_ns = 0; + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0; + masterConfig->pinLowTimeout_ns = 0; masterConfig->sdaGlitchFilterWidth_ns = 0; masterConfig->sclGlitchFilterWidth_ns = 0; - masterConfig->hostRequest.enable = false; - masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; - masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; } /*! @@ -427,7 +427,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi /* Configure glitch filters and bus idle and pin low timeouts. */ prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; - cfgr2 = base->MCFGR2; + cfgr2 = base->MCFGR2; if (masterConfig->busIdleTimeout_ns) { cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, @@ -452,7 +452,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi base->MCFGR2 = cfgr2; if (masterConfig->pinLowTimeout_ns) { - cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); } @@ -461,8 +461,8 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi } /*! -* brief Deinitializes the LPI2C master peripheral. -* + * brief Deinitializes the LPI2C master peripheral. + * * This function disables the LPI2C master peripheral and gates the clock. It also performs a software * reset to restore the peripheral to reset conditions. * @@ -501,7 +501,7 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); - base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); + base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); /* Restore master mode. */ if (wasEnabled) @@ -526,10 +526,10 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con */ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) { - uint32_t prescale = 0; - uint32_t bestPre = 0; + uint32_t prescale = 0; + uint32_t bestPre = 0; uint32_t bestClkHi = 0; - uint32_t absError = 0; + uint32_t absError = 0; uint32_t bestError = 0xffffffffu; uint32_t value; uint32_t clkHiCycle; @@ -560,7 +560,7 @@ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t if (absError < bestError) { - bestPre = prescale; + bestPre = prescale; bestClkHi = clkHiCycle; bestError = absError; @@ -871,7 +871,7 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t uint32_t subaddressRemaining = transfer->subaddressSize; while (subaddressRemaining--) { - uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff; commandBuffer[cmdCount++] = subaddressByte; } } @@ -964,7 +964,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, /* Save base and instance. */ handle->completionCallback = callback; - handle->userData = userData; + handle->userData = userData; /* Save this handle for IRQ use. */ s_lpi2cMasterHandle[instance] = handle; @@ -998,7 +998,7 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han lpi2c_master_transfer_t *xfer; size_t txCount; size_t rxCount; - size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); bool state_complete = false; /* Set default isDone return value. */ @@ -1044,8 +1044,8 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han if (xfer->dataSize) { /* Either a send or receive transfer is next. */ - handle->state = kTransferDataState; - handle->buf = (uint8_t *)xfer->data; + handle->state = kTransferDataState; + handle->buf = (uint8_t *)xfer->data; handle->remainingBytes = xfer->dataSize; if (xfer->direction == kLPI2C_Read) { @@ -1131,7 +1131,7 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han else { /* Caller doesn't want to send a stop, so we're done now. */ - *isDone = true; + *isDone = true; state_complete = true; break; } @@ -1176,12 +1176,12 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) handle->state = kTransferDataState; } - handle->buf = (uint8_t *)xfer->data; + handle->buf = (uint8_t *)xfer->data; handle->remainingBytes = xfer->dataSize; } else { - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; uint32_t cmdCount = 0; /* Initial direction depends on whether a subaddress was provided, and of course the actual */ @@ -1199,7 +1199,7 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) while (subaddressRemaining--) { uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; + cmd[cmdCount++] = subaddressByte; } } @@ -1218,9 +1218,9 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) } /* Set up state machine for transferring the commands. */ - handle->state = kSendCommandState; + handle->state = kSendCommandState; handle->remainingBytes = cmdCount; - handle->buf = (uint8_t *)&handle->commandBuffer; + handle->buf = (uint8_t *)&handle->commandBuffer; } } @@ -1310,9 +1310,9 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h /* are synchronized with each other during an ongoing transfer. */ uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); LPI2C_MasterDisableInterrupts(base, irqs); - state = handle->state; + state = handle->state; remainingBytes = handle->remainingBytes; - dataSize = handle->transfer.dataSize; + dataSize = handle->transfer.dataSize; LPI2C_MasterEnableInterrupts(base, irqs); /* Get transfer count based on current transfer state. */ @@ -1448,23 +1448,23 @@ void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) /* Initializes the configure structure to zero. */ memset(slaveConfig, 0, sizeof(*slaveConfig)); - slaveConfig->enableSlave = true; - slaveConfig->address0 = 0U; - slaveConfig->address1 = 0U; - slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; - slaveConfig->filterDozeEnable = true; - slaveConfig->filterEnable = true; - slaveConfig->enableGeneralCall = false; - slaveConfig->sclStall.enableAck = false; - slaveConfig->sclStall.enableTx = true; - slaveConfig->sclStall.enableRx = true; - slaveConfig->sclStall.enableAddress = false; - slaveConfig->ignoreAck = false; + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; slaveConfig->enableReceivedAddressRead = false; - slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ - slaveConfig->sclGlitchFilterWidth_ns = 0; - slaveConfig->dataValidDelay_ns = 0; - slaveConfig->clockHoldTime_ns = 0; + slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ + slaveConfig->sclGlitchFilterWidth_ns = 0; + slaveConfig->dataValidDelay_ns = 0; + slaveConfig->clockHoldTime_ns = 0; } /*! @@ -1523,8 +1523,8 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, } /*! -* brief Deinitializes the LPI2C slave peripheral. -* + * brief Deinitializes the LPI2C slave peripheral. + * * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software * reset to restore the peripheral to reset conditions. * @@ -1595,7 +1595,7 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) */ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) { - uint8_t *buf = (uint8_t *)txBuff; + uint8_t *buf = (uint8_t *)txBuff; size_t remaining = txSize; assert(txBuff); @@ -1613,7 +1613,7 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t * do { /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); + flags = LPI2C_SlaveGetStatusFlags(base); result = LPI2C_SlaveCheckAndClearError(base, flags); if (result) { @@ -1670,7 +1670,7 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t * */ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) { - uint8_t *buf = (uint8_t *)rxBuff; + uint8_t *buf = (uint8_t *)rxBuff; size_t remaining = rxSize; assert(rxBuff); @@ -1688,7 +1688,7 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_ do { /* Check for errors */ - flags = LPI2C_SlaveGetStatusFlags(base); + flags = LPI2C_SlaveGetStatusFlags(base); result = LPI2C_SlaveCheckAndClearError(base, flags); if (result) { @@ -1935,7 +1935,7 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag)) { - xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->event = kLPI2C_SlaveCompletionEvent; xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback)) @@ -1948,7 +1948,7 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle { xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent : kLPI2C_SlaveCompletionEvent; - xfer->receivedAddress = 0; + xfer->receivedAddress = 0; xfer->completionStatus = kStatus_Success; xfer->transferredCount = handle->transferredCount; @@ -1982,7 +1982,7 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle } if (flags & kLPI2C_SlaveAddressValidFlag) { - xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->event = kLPI2C_SlaveAddressMatchEvent; xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK; if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback)) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h index 8ed0e658acf83..a15d21e24207e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h @@ -37,16 +37,16 @@ enum _lpi2c_status { kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ - kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ - kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ - kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ kStatus_LPI2C_PinLowTimeout = MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ kStatus_LPI2C_NoTransferInProgress = MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ - kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ }; /*! @} */ @@ -75,33 +75,33 @@ enum _lpi2c_status */ enum _lpi2c_master_flags { - kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ - kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ - kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ - kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ - kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ - kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ - kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ }; /*! @brief Direction of master and slave transfers. */ typedef enum _lpi2c_direction { kLPI2C_Write = 0U, /*!< Master transmit. */ - kLPI2C_Read = 1U /*!< Master receive. */ + kLPI2C_Read = 1U /*!< Master receive. */ } lpi2c_direction_t; /*! @brief LPI2C pin configuration. */ typedef enum _lpi2c_master_pin_config { - kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ - kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ - kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ kLPI2C_2PinOpenDrainWithSeparateSlave = 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ kLPI2C_2PinOutputOnlyWithSeparateSlave = @@ -114,15 +114,15 @@ typedef enum _lpi2c_master_pin_config /*! @brief LPI2C master host request selection. */ typedef enum _lpi2c_host_request_source { - kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ } lpi2c_host_request_source_t; /*! @brief LPI2C master host request pin polarity configuration. */ typedef enum _lpi2c_host_request_polarity { - kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ - kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ } lpi2c_host_request_polarity_t; /*! @@ -157,7 +157,7 @@ typedef struct _lpi2c_master_config /*! @brief LPI2C master data match configuration modes. */ typedef enum _lpi2c_data_match_config_mode { - kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = @@ -206,10 +206,10 @@ typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, */ enum _lpi2c_master_transfer_flags { - kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ - kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ - kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ }; /*! @@ -219,10 +219,9 @@ enum _lpi2c_master_transfer_flags */ struct _lpi2c_master_transfer { - uint32_t - flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for available - options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ @@ -268,26 +267,26 @@ struct _lpi2c_master_handle */ enum _lpi2c_slave_flags { - kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ - kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ - kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ - kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ - kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ - kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ - kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ - kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ - kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ - kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ - kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ - kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ - kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ }; /*! @brief LPI2C slave address match options. */ typedef enum _lpi2c_slave_address_match { - kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ - kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ } lpi2c_slave_address_match_t; @@ -344,13 +343,13 @@ typedef struct _lpi2c_slave_config typedef enum _lpi2c_slave_transfer_event { kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ - kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit (slave-transmitter role). */ kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received data (slave-receiver role). */ - kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ - kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ /*! Bit mask of all available events. */ kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | @@ -459,8 +458,8 @@ void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); /*! -* @brief Deinitializes the LPI2C master peripheral. -* + * @brief Deinitializes the LPI2C master peripheral. + * * This function disables the LPI2C master peripheral and gates the clock. It also performs a software * reset to restore the peripheral to reset conditions. * @@ -958,8 +957,8 @@ void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); /*! -* @brief Deinitializes the LPI2C slave peripheral. -* + * @brief Deinitializes the LPI2C slave peripheral. + * * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software * reset to restore the peripheral to reset conditions. * diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c index da100d66f2bac..e8de4a1c8976c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c @@ -57,8 +57,8 @@ enum _lpi2c_master_fifo_cmd { kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ - kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ - kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ }; /*! @brief States for the state machine used by transactional APIs. */ @@ -120,11 +120,11 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ /* in order to make the transfer API code simpler. */ - handle->base = base; + handle->base = base; handle->completionCallback = callback; - handle->userData = userData; - handle->rx = rxDmaHandle; - handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; /* Set DMA channel completion callbacks. */ EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); @@ -142,8 +142,8 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) { lpi2c_master_transfer_t *xfer = &handle->transfer; - uint16_t *cmd = (uint16_t *)&handle->commandBuffer; - uint32_t cmdCount = 0; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; /* Handle no start option. */ if (xfer->flags & kLPI2C_TransferNoStartFlag) @@ -173,7 +173,7 @@ static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) while (subaddressRemaining--) { uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; - cmd[cmdCount++] = subaddressByte; + cmd[cmdCount++] = subaddressByte; } } @@ -267,7 +267,7 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, /* Get a 32-byte aligned TCD pointer. */ edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); - bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize); edma_transfer_config_t transferConfig; @@ -276,14 +276,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, /* Set up data transmit. */ if (hasSendData) { - transferConfig.srcAddr = (uint32_t)transfer->data; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcAddr = (uint32_t)transfer->data; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = sizeof(uint8_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; + transferConfig.srcOffset = sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ handle->nbytes = transferConfig.minorLoopBytes; @@ -306,14 +306,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, else if (hasReceiveData) { /* Set up data receive. */ - transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); - transferConfig.destAddr = (uint32_t)transfer->data; - transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)transfer->data; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfig.srcOffset = 0; - transferConfig.destOffset = sizeof(uint8_t); - transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ - transferConfig.majorLoopCounts = transfer->dataSize; + transferConfig.srcOffset = 0; + transferConfig.destOffset = sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ handle->nbytes = transferConfig.minorLoopBytes; @@ -342,14 +342,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, /* Set up commands transfer. */ if (commandCount) { - transferConfig.srcAddr = (uint32_t)handle->commandBuffer; - transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); - transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfig.srcOffset = sizeof(uint16_t); - transferConfig.destOffset = 0; - transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ - transferConfig.majorLoopCounts = commandCount; + transferConfig.srcOffset = sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.h index 04711f2bd42dc..30d528e5558cf 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_LPI2C_EDMA_H_ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c index fcf1847301171..dbfbe38c98005 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c @@ -9,8 +9,8 @@ #include "fsl_lpspi.h" /******************************************************************************* -* Definitions -******************************************************************************/ + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID @@ -35,81 +35,81 @@ typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *hand typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle); /******************************************************************************* -* Prototypes -******************************************************************************/ + * Prototypes + ******************************************************************************/ /*! -* @brief Get instance number for LPSPI module. -* -* @param base LPSPI peripheral base address. -* @return Return the value of LPSPI instance. -*/ + * @brief Get instance number for LPSPI module. + * + * @param base LPSPI peripheral base address. + * @return Return the value of LPSPI instance. + */ uint32_t LPSPI_GetInstance(LPSPI_Type *base); /*! -* @brief Configures the LPSPI peripheral chip select polarity. -* -* This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and -* configures the Pcs signal to operate with the desired characteristic. -* -* @param base LPSPI peripheral address. -* @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to -* apply the active high or active low characteristic. -* @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of -* type lpspi_pcs_polarity_config_t. -*/ + * @brief Configures the LPSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base LPSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type lpspi_pcs_polarity_config_t. + */ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, lpspi_which_pcs_t pcs, lpspi_pcs_polarity_config_t activeLowOrHigh); /*! -* @brief Combine the write data for 1 byte to 4 bytes. -* This is not a public API. -*/ + * @brief Combine the write data for 1 byte to 4 bytes. + * This is not a public API. + */ static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap); /*! -* @brief Separate the read data for 1 byte to 4 bytes. -* This is not a public API. -*/ + * @brief Separate the read data for 1 byte to 4 bytes. + * This is not a public API. + */ static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); /*! -* @brief Master fill up the TX FIFO with data. -* This is not a public API. -*/ + * @brief Master fill up the TX FIFO with data. + * This is not a public API. + */ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); /*! -* @brief Master finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); /*! -* @brief Slave fill up the TX FIFO with data. -* This is not a public API. -*/ + * @brief Slave fill up the TX FIFO with data. + * This is not a public API. + */ static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); /*! -* @brief Slave finish up a transfer. -* It would call back if there is callback function and set the state to idle. -* This is not a public API. -*/ + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); /*! -* @brief LPSPI common interrupt handler. -* -* @param handle pointer to s_lpspiHandle which stores the transfer state. -*/ + * @brief LPSPI common interrupt handler. + * + * @param handle pointer to s_lpspiHandle which stores the transfer state. + */ static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param); /******************************************************************************* -* Variables -******************************************************************************/ + * Variables + ******************************************************************************/ /* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; @@ -140,8 +140,8 @@ static lpspi_slave_isr_t s_lpspiSlaveIsr; /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; /********************************************************************************************************************** -* Code -*********************************************************************************************************************/ + * Code + *********************************************************************************************************************/ uint32_t LPSPI_GetInstance(LPSPI_Type *base) { uint8_t instance = 0; @@ -172,7 +172,7 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base) */ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) { - uint32_t instance = LPSPI_GetInstance(base); + uint32_t instance = LPSPI_GetInstance(base); g_lpspiDummyData[instance] = dummyData; } @@ -252,20 +252,20 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) /* Initializes the configure structure to zero. */ memset(masterConfig, 0, sizeof(*masterConfig)); - masterConfig->baudRate = 500000; + masterConfig->baudRate = 500000; masterConfig->bitsPerFrame = 8; - masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; - masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; - masterConfig->direction = kLPSPI_MsbFirst; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; - masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->whichPcs = kLPSPI_Pcs0; masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; - masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; masterConfig->dataOutConfig = kLpspiDataOutRetained; } @@ -329,15 +329,15 @@ void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) /* Initializes the configure structure to zero. */ memset(slaveConfig, 0, sizeof(*slaveConfig)); - slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ - slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ - slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ - slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ - slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ - slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; slaveConfig->dataOutConfig = kLpspiDataOutRetained; } @@ -346,7 +346,7 @@ void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) * sets all registers to reset state. As a result, the LPSPI module can't work after calling * this API. * param base LPSPI peripheral address. -*/ + */ void LPSPI_Reset(LPSPI_Type *base) { /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ @@ -424,8 +424,8 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, assert(tcrPrescaleValue); /* For master mode configuration only, if slave mode detected, return 0. - * Also, the LPSPI module needs to be disabled first, if enabled, return 0 - */ + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) { return 0; @@ -438,16 +438,16 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t desiredBaudrate = baudRate_Bps; /* find combination of prescaler and scaler resulting in baudrate closest to the - * requested value - */ + * requested value + */ min_diff = 0xFFFFFFFFU; /* Set to maximum divisor value bit settings so that if baud rate passed in is less - * than the minimum possible baud rate, then the SPI will be configured to the lowest - * possible baud rate - */ + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ bestPrescaler = 7; - bestScaler = 255; + bestScaler = 255; bestBaudrate = 0; /* required to avoid compilation warning */ @@ -459,28 +459,28 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); /* calculate the baud rate difference based on the conditional statement - * that states that the calculated baud rate must not exceed the desired baud rate - */ + * that states that the calculated baud rate must not exceed the desired baud rate + */ if (desiredBaudrate >= realBaudrate) { diff = desiredBaudrate - realBaudrate; if (min_diff > diff) { /* a better match found */ - min_diff = diff; + min_diff = diff; bestPrescaler = prescaler; - bestScaler = scaler; - bestBaudrate = realBaudrate; + bestScaler = scaler; + bestBaudrate = realBaudrate; } } } } /* Write the best baud rate scalar to the CCR. - * Note, no need to check for error since we've already checked to make sure the module is - * disabled and in master mode. Also, there is a limit on the maximum divider so we will not - * exceed this. - */ + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); /* return the best prescaler value for user to use later */ @@ -589,8 +589,8 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, bestScaler = 0xFFU; /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as - * the delay divisors are slightly different based on which delay we are configuring. - */ + * the delay divisors are slightly different based on which delay we are configuring. + */ if (whichDelay == kLPSPI_BetweenTransfer) { /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of @@ -626,9 +626,9 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, } /* If the initial, default delay is already greater than the desired delay, then - * set the delay to their initial value (0) and return the delay. In other words, - * there is no way to decrease the delay value further. - */ + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ if (initialDelayNanoSec >= delayTimeInNanoSec) { LPSPI_MasterSetDelayScaler(base, 0, whichDelay); @@ -647,17 +647,17 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, realDelay /= clockDividedPrescaler; /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the desired delay - */ + * that states that the calculated delay must not be less then the desired delay + */ if (realDelay >= delayTimeInNanoSec) { diff = realDelay - delayTimeInNanoSec; if (min_diff > diff) { /* a better match found */ - min_diff = diff; + min_diff = diff; bestScaler = scaler; - bestDelay = realDelay; + bestDelay = realDelay; } } } @@ -702,13 +702,13 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, } /*! -* brief Check the argument for transfer . -* -* param transfer the transfer struct to be used. -* param bitPerFrame The bit size of one frame. -* param bytePerFrame The byte size of one frame. -* return Return true for right and false for wrong. -*/ + * brief Check the argument for transfer . + * + * param transfer the transfer struct to be used. + * param bitPerFrame The bit size of one frame. + * param bytePerFrame The byte size of one frame. + * return Return true for right and false for wrong. + */ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) { assert(transfer); @@ -779,10 +779,10 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf { assert(transfer); - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -795,8 +795,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf return kStatus_LPSPI_Busy; } - uint8_t *txData = transfer->txData; - uint8_t *rxData = transfer->rxData; + uint8_t *txData = transfer->txData; + uint8_t *rxData = transfer->rxData; uint32_t txRemainingByteCount = transfer->dataSize; uint32_t rxRemainingByteCount = transfer->dataSize; @@ -813,8 +813,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - bool isRxMask = false; - bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + bool isRxMask = false; + bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); LPSPI_FlushFifo(base, true, true); LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); @@ -850,12 +850,12 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf if (bytesPerFrame <= 4) { bytesEachWrite = bytesPerFrame; - bytesEachRead = bytesPerFrame; + bytesEachRead = bytesPerFrame; } else { bytesEachWrite = 4; - bytesEachRead = 4; + bytesEachRead = 4; } /*Write the TX data until txRemainingByteCount is equal to 0 */ @@ -962,10 +962,10 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t assert(handle); assert(transfer); - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; - uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -986,16 +986,16 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; handle->txRemainingByteCount = transfer->dataSize; handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; handle->writeTcrInIsr = false; handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; handle->txBuffIfNull = ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); @@ -1004,17 +1004,17 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t handle->fifoSize = LPSPI_GetRxFifoSize(base); handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); /*Set the RX and TX watermarks to reduce the ISR times.*/ if (handle->fifoSize > 1) { - txWatermark = 1; + txWatermark = 1; handle->rxWatermark = handle->fifoSize - 2; } else { - txWatermark = 0; + txWatermark = 0; handle->rxWatermark = 0; } @@ -1050,7 +1050,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t * controlled by software.*/ if (handle->rxData == NULL) { - isRxMask = true; + isRxMask = true; handle->rxRemainingByteCount = 0; } @@ -1063,12 +1063,12 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t if (bytesPerFrame <= 4) { handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; } else { handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; + handle->bytesEachRead = 4; } /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , @@ -1113,9 +1113,9 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand uint32_t wordToSend = 0; /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth - * and that the number of TX FIFO entries does not exceed the FIFO depth. - * But no need to make the protection if there is no rxData. - */ + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) && (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) || (handle->rxData == NULL))) @@ -1152,7 +1152,7 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand /* Only write to the TCR if the FIFO has room */ if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); handle->writeTcrInIsr = false; } /* Else, set a global flag to tell the ISR to do write to the TCR */ @@ -1240,7 +1240,7 @@ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) LPSPI_Reset(base); - handle->state = kLPSPI_Idle; + handle->state = kLPSPI_Idle; handle->txRemainingByteCount = 0; handle->rxRemainingByteCount = 0; } @@ -1264,9 +1264,9 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand if (handle->rxRemainingByteCount) { /* First, disable the interrupts to avoid potentially triggering another interrupt - * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll - * re-enable the interrupts based on the LPSPI state after reading out the FIFO. - */ + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable); while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount)) @@ -1290,8 +1290,8 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand } /* Re-enable the interrupts only if rxCount indicates there is more data to receive, - * else we may get a spurious interrupt. - * */ + * else we may get a spurious interrupt. + * */ if (handle->rxRemainingByteCount) { /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ @@ -1320,7 +1320,7 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand { if ((handle->isPcsContinuous) && (handle->writeTcrInIsr)) { - base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); handle->writeTcrInIsr = false; } } @@ -1404,9 +1404,9 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * assert(handle); assert(transfer); - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; + uint32_t temp = 0U; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -1425,14 +1425,14 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; handle->txRemainingByteCount = transfer->dataSize; handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; /*The TX and RX FIFO sizes are always the same*/ handle->fifoSize = LPSPI_GetRxFifoSize(base); @@ -1443,12 +1443,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * uint8_t txWatermark; if (handle->fifoSize > 1) { - txWatermark = 1; + txWatermark = 1; handle->rxWatermark = handle->fifoSize - 2; } else { - txWatermark = 0; + txWatermark = 0; handle->rxWatermark = 0; } LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); @@ -1479,7 +1479,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/ if (handle->rxData == NULL) { - isRxMask = true; + isRxMask = true; handle->rxRemainingByteCount = 0; } @@ -1488,13 +1488,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * */ if (handle->txData == NULL) { - isTxMask = true; + isTxMask = true; handle->txRemainingByteCount = 0; } - base->TCR = (base->TCR & - ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK | - LPSPI_TCR_PCS_MASK)) | + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs); @@ -1502,12 +1501,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * if (bytesPerFrame <= 4) { handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; } else { handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; + handle->bytesEachRead = 4; } /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , @@ -1674,7 +1673,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) LPSPI_Reset(base); - handle->state = kLPSPI_Idle; + handle->state = kLPSPI_Idle; handle->txRemainingByteCount = 0; handle->rxRemainingByteCount = 0; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h index c31d3de285d5a..40236798d153d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h @@ -36,25 +36,25 @@ extern volatile uint8_t g_lpspiDummyData[]; /*! @brief Status for the LPSPI driver.*/ enum _lpspi_status { - kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ - kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ - kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ - kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ }; /*! @brief LPSPI status flags in SPIx_SR register.*/ enum _lpspi_flags { - kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ - kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ - kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ - kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ - kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ - kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ - kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ - kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ - kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ }; @@ -62,14 +62,14 @@ enum _lpspi_flags /*! @brief LPSPI interrupt source.*/ enum _lpspi_interrupt_enable { - kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ - kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ - kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ - kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ - kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ - kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ - kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ kLPSPI_AllInterruptEnable = (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ @@ -86,7 +86,7 @@ enum _lpspi_dma_enable typedef enum _lpspi_master_slave_mode { kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ - kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ } lpspi_master_slave_mode_t; /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ @@ -102,24 +102,24 @@ typedef enum _lpspi_which_pcs_config typedef enum _lpspi_pcs_polarity_config { kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ - kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ } lpspi_pcs_polarity_config_t; /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ enum _lpspi_pcs_polarity { - kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ - kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ - kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ - kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ - kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ }; /*! @brief LPSPI clock polarity configuration.*/ typedef enum _lpspi_clock_polarity { kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ - kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ } lpspi_clock_polarity_t; /*! @brief LPSPI clock phase configuration.*/ @@ -141,20 +141,20 @@ typedef enum _lpspi_shift_direction /*! @brief LPSPI Host Request select configuration. */ typedef enum _lpspi_host_request_select { - kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ - kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ } lpspi_host_request_select_t; /*! @brief LPSPI Match configuration options. */ typedef enum _lpspi_match_config { - kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ - kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ - kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ - kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ } lpspi_match_config_t; /*! @brief LPSPI pin (SDO and SDI) configuration. */ @@ -177,8 +177,8 @@ typedef enum _lpspi_data_out_config typedef enum _lpspi_transfer_width { kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ - kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ - kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ } lpspi_transfer_width_t; /*! @brief LPSPI delay type selection.*/ @@ -204,17 +204,17 @@ enum _lpspi_transfer_config_flag_for_master kLPSPI_MasterByteSwap = 1U << 22 /*!< Is master swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ }; #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ @@ -230,17 +230,17 @@ enum _lpspi_transfer_config_flag_for_slave kLPSPI_SlaveByteSwap = 1U << 22 /*!< Is slave swap the byte. - * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set - * lpspi_shift_direction_t to MSB). - * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used - * or not, the waveform is 1 2 3 4 5 6 7 8. - * 2. If you set bitPerFrame = 16 : - * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - * 3. If you set bitPerFrame = 32 : - * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. - * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. - */ + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ }; /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ @@ -264,9 +264,8 @@ typedef struct _lpspi_master_config It sets the boundary value if out of range.*/ uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.*/ - uint32_t - betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum - delay. It sets the boundary value if out of range.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the + minimum delay. It sets the boundary value if out of range.*/ lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ @@ -297,13 +296,13 @@ typedef struct _lpspi_slave_config } lpspi_slave_config_t; /*! -* @brief Forward declaration of the _lpspi_master_handle typedefs. -*/ + * @brief Forward declaration of the _lpspi_master_handle typedefs. + */ typedef struct _lpspi_master_handle lpspi_master_handle_t; /*! -* @brief Forward declaration of the _lpspi_slave_handle typedefs. -*/ + * @brief Forward declaration of the _lpspi_slave_handle typedefs. + */ typedef struct _lpspi_slave_handle lpspi_slave_handle_t; /*! @@ -339,10 +338,9 @@ typedef struct _lpspi_transfer uint8_t *rxData; /*!< Receive buffer. */ volatile size_t dataSize; /*!< Transfer bytes. */ - uint32_t - configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the - transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer - is used for slave.*/ + uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if + the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the + transfer is used for slave.*/ } lpspi_transfer_t; /*! @brief LPSPI master transfer handle structure used for transactional API. */ @@ -479,7 +477,7 @@ void LPSPI_Deinit(LPSPI_Type *base); * sets all registers to reset state. As a result, the LPSPI module can't work after calling * this API. * @param base LPSPI peripheral address. -*/ + */ void LPSPI_Reset(LPSPI_Type *base); /*! @@ -502,7 +500,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) /*! *@} -*/ + */ /*! * @name Status @@ -579,7 +577,7 @@ static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags /*! *@} -*/ + */ /*! * @name Interrupts @@ -621,7 +619,7 @@ static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) /*! *@} -*/ + */ /*! * @name DMA Control @@ -692,7 +690,7 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) /*! *@} -*/ + */ /*! * @name Bus Operations @@ -700,13 +698,13 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) */ /*! -* @brief Check the argument for transfer . -* -* @param transfer the transfer struct to be used. -* @param bitPerFrame The bit size of one frame. -* @param bytePerFrame The byte size of one frame. -* @return Return true for right and false for wrong. -*/ + * @brief Check the argument for transfer . + * + * @param transfer the transfer struct to be used. + * @param bitPerFrame The bit size of one frame. + * @param bytePerFrame The byte size of one frame. + * @return Return true for right and false for wrong. + */ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); /*! @@ -934,7 +932,7 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); /*! *@} -*/ + */ /*! * @name Transactional @@ -1099,13 +1097,13 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle /*! *@} -*/ + */ #if defined(__cplusplus) } #endif /*_cplusplus*/ /*! *@} - */ + */ #endif /*_FSL_LPSPI_H_*/ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c index effca2527cecf..a26599bd2155e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c @@ -9,8 +9,8 @@ #include "fsl_lpspi_edma.h" /*********************************************************************************************************************** -* Definitions -***********************************************************************************************************************/ + * Definitions + ***********************************************************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID @@ -18,8 +18,8 @@ #endif /*! -* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. -*/ + * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + */ typedef struct _lpspi_master_edma_private_handle { LPSPI_Type *base; /*!< LPSPI peripheral base address. */ @@ -27,8 +27,8 @@ typedef struct _lpspi_master_edma_private_handle } lpspi_master_edma_private_handle_t; /*! -* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. -*/ + * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + */ typedef struct _lpspi_slave_edma_private_handle { LPSPI_Type *base; /*!< LPSPI peripheral base address. */ @@ -36,30 +36,30 @@ typedef struct _lpspi_slave_edma_private_handle } lpspi_slave_edma_private_handle_t; /*********************************************************************************************************************** -* Prototypes -***********************************************************************************************************************/ + * Prototypes + ***********************************************************************************************************************/ /*! -* @brief Get instance number for LPSPI module. -* -* @param base LPSPI peripheral base address. -* @return Return the value of LPSPI instance. -*/ + * @brief Get instance number for LPSPI module. + * + * @param base LPSPI peripheral base address. + * @return Return the value of LPSPI instance. + */ static uint32_t LPSPI_GetInstance(LPSPI_Type *base); /*! -* @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. -* This is not a public API. -*/ + * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. + * This is not a public API. + */ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, void *g_lpspiEdmaPrivateHandle, bool transferDone, uint32_t tcds); /*! -* @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. -* This is not a public API. -*/ + * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. + * This is not a public API. + */ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, void *g_lpspiEdmaPrivateHandle, bool transferDone, @@ -68,8 +68,8 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); /*********************************************************************************************************************** -* Variables -***********************************************************************************************************************/ + * Variables + ***********************************************************************************************************************/ /*! @brief Pointers to lpspi bases for each instance. */ static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; @@ -78,8 +78,8 @@ static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_S static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; /*********************************************************************************************************************** -* Code -***********************************************************************************************************************/ + * Code + ***********************************************************************************************************************/ static uint32_t LPSPI_GetInstance(LPSPI_Type *base) { @@ -189,7 +189,7 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, uint32_t instance = LPSPI_GetInstance(base); - s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].base = base; s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; handle->callback = callback; @@ -221,9 +221,9 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * assert(handle); assert(transfer); - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; + uint32_t temp = 0U; if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) { @@ -245,8 +245,8 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * handle->state = kLPSPI_Busy; uint32_t instance = LPSPI_GetInstance(base); - uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); - uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; @@ -266,17 +266,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * edma_transfer_config_t transferConfigRx; edma_transfer_config_t transferConfigTx; - edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; handle->txRemainingByteCount = transfer->dataSize; handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; handle->txBuffIfNull = ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); @@ -285,7 +285,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * handle->fifoSize = LPSPI_GetRxFifoSize(base); handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); - handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); @@ -308,6 +308,8 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * } } + LPSPI_Enable(base, true); + /*Flush FIFO , clear status , disable all the inerrupts.*/ LPSPI_FlushFifo(base, true, true); LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); @@ -320,27 +322,27 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); - isThereExtraTxBytes = false; + isThereExtraTxBytes = false; handle->isThereExtraRxBytes = false; /*Calculate the bytes for write/read the TX/RX register each time*/ if (bytesPerFrame <= 4) { handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; handle->bytesLastRead = bytesPerFrame; } else { handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; + handle->bytesEachRead = 4; handle->bytesLastRead = 4; if ((transfer->dataSize % 4) != 0) { - bytesLastWrite = transfer->dataSize % 4; + bytesLastWrite = transfer->dataSize % 4; handle->bytesLastRead = bytesLastWrite; isThereExtraTxBytes = true; @@ -362,12 +364,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * if (handle->rxData) { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); transferConfigRx.destOffset = 1; } else { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); transferConfigRx.destOffset = 0; } transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; @@ -377,7 +379,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { case (1U): transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; + transferConfigRx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -386,7 +388,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * case (2U): transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; + transferConfigRx.minorLoopBytes = 2; if (handle->isByteSwap) { dif = 2; @@ -395,17 +397,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * case (4U): transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; + transferConfigRx.minorLoopBytes = 4; break; default: transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; + transferConfigRx.minorLoopBytes = 1; assert(false); break; } - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; transferConfigRx.srcOffset = 0; transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; @@ -425,12 +427,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { if (handle->txData) { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); transferConfigTx.srcOffset = 1; } else { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); transferConfigTx.srcOffset = 0; } @@ -443,7 +445,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { case (1U): transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -452,7 +454,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * case (2U): transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; + transferConfigTx.minorLoopBytes = 2; if (handle->isByteSwap) { dif = 2; @@ -461,12 +463,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * default: transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; assert(false); break; } - transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.destAddr = (uint32_t)txAddr + dif; transferConfigTx.majorLoopCounts = 1; EDMA_TcdReset(softwareTCD_extraBytes); @@ -485,16 +487,16 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); - transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); transferConfigTx.srcOffset = 0; - transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destAddr = (uint32_t) & (base->TCR); transferConfigTx.destOffset = 0; - transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; - transferConfigTx.majorLoopCounts = 1; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; EDMA_TcdReset(softwareTCD_pcsContinuous); EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); @@ -502,12 +504,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * if (handle->txData) { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcAddr = (uint32_t)(handle->txData); transferConfigTx.srcOffset = 1; } else { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); transferConfigTx.srcOffset = 0; } @@ -520,7 +522,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * { case (1U): transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -529,7 +531,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * case (2U): transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; + transferConfigTx.minorLoopBytes = 2; if (handle->isByteSwap) { @@ -539,12 +541,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * case (4U): transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; + transferConfigTx.minorLoopBytes = 4; break; default: transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; assert(false); break; } @@ -573,7 +575,6 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t * EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); return kStatus_Success; } @@ -712,7 +713,7 @@ void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, uint32_t instance = LPSPI_GetInstance(base); - s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; handle->callback = callback; @@ -744,9 +745,9 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha assert(handle); assert(transfer); - uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; - uint32_t temp = 0U; + uint32_t temp = 0U; uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; @@ -792,14 +793,14 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha bool isThereExtraTxBytes = false; - handle->txData = transfer->txData; - handle->rxData = transfer->rxData; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; handle->txRemainingByteCount = transfer->dataSize; handle->rxRemainingByteCount = transfer->dataSize; - handle->totalByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); - handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; handle->txBuffIfNull = ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); @@ -830,6 +831,8 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha } } + LPSPI_Enable(base, true); + /*Flush FIFO , clear status , disable all the inerrupts.*/ LPSPI_FlushFifo(base, true, true); LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); @@ -841,27 +844,27 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); - isThereExtraTxBytes = false; + isThereExtraTxBytes = false; handle->isThereExtraRxBytes = false; /*Calculate the bytes for write/read the TX/RX register each time*/ if (bytesPerFrame <= 4) { handle->bytesEachWrite = bytesPerFrame; - handle->bytesEachRead = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; handle->bytesLastRead = bytesPerFrame; } else { handle->bytesEachWrite = 4; - handle->bytesEachRead = 4; + handle->bytesEachRead = 4; handle->bytesLastRead = 4; if ((transfer->dataSize % 4) != 0) { - bytesLastWrite = transfer->dataSize % 4; + bytesLastWrite = transfer->dataSize % 4; handle->bytesLastRead = bytesLastWrite; isThereExtraTxBytes = true; @@ -884,12 +887,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha if (handle->rxData) { - transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); transferConfigRx.destOffset = 1; } else { - transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); transferConfigRx.destOffset = 0; } transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; @@ -899,7 +902,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha { case (1U): transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; + transferConfigRx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -908,7 +911,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha case (2U): transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; - transferConfigRx.minorLoopBytes = 2; + transferConfigRx.minorLoopBytes = 2; if (handle->isByteSwap) { dif = 2; @@ -917,17 +920,17 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha case (4U): transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; - transferConfigRx.minorLoopBytes = 4; + transferConfigRx.minorLoopBytes = 4; break; default: transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; - transferConfigRx.minorLoopBytes = 1; + transferConfigRx.minorLoopBytes = 1; assert(false); break; } - transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; transferConfigRx.srcOffset = 0; transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; @@ -948,12 +951,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha { if (handle->txData) { - transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); transferConfigTx.srcOffset = 1; } else { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); transferConfigTx.srcOffset = 0; } @@ -966,7 +969,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha { case (1U): transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -975,7 +978,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha case (2U): transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; + transferConfigTx.minorLoopBytes = 2; if (handle->isByteSwap) { dif = 2; @@ -984,12 +987,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha default: transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; assert(false); break; } - transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.destAddr = (uint32_t)txAddr + dif; transferConfigTx.majorLoopCounts = 1; EDMA_TcdReset(softwareTCD_extraBytes); @@ -999,12 +1002,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha if (handle->txData) { - transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcAddr = (uint32_t)(handle->txData); transferConfigTx.srcOffset = 1; } else { - transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); transferConfigTx.srcOffset = 0; } @@ -1017,7 +1020,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha { case (1U): transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; if (handle->isByteSwap) { dif = 3; @@ -1026,7 +1029,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha case (2U): transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; - transferConfigTx.minorLoopBytes = 2; + transferConfigTx.minorLoopBytes = 2; if (handle->isByteSwap) { @@ -1036,12 +1039,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha case (4U): transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; - transferConfigTx.minorLoopBytes = 4; + transferConfigTx.minorLoopBytes = 4; break; default: transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; - transferConfigTx.minorLoopBytes = 1; + transferConfigTx.minorLoopBytes = 1; assert(false); break; } @@ -1065,7 +1068,6 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); - LPSPI_Enable(base, true); return kStatus_Success; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.h index 8ef2cde1ed795..a2f9ef55e0aef 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.h @@ -26,13 +26,13 @@ /*@}*/ /*! -* @brief Forward declaration of the _lpspi_master_edma_handle typedefs. -*/ + * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. + */ typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; /*! -* @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. -*/ + * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. + */ typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c index 76c71ea4c0793..3a8a43703600e 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -132,17 +132,20 @@ uint32_t LPUART_GetInstance(LPUART_Type *base) */ size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; - if (handle->rxRingBufferTail > handle->rxRingBufferHead) + if (tmpRxRingBufferTail > tmpRxRingBufferHead) { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); } else { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); } return size; @@ -150,7 +153,7 @@ size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t * static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); bool full; @@ -167,7 +170,7 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) { - assert(data); + assert(NULL != data); size_t i; @@ -181,7 +184,7 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) { - assert(data); + assert(NULL != data); size_t i; #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT @@ -204,7 +207,7 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng data[i] = base->DATA; } #else - data[i] = base->DATA; + data[i] = (uint8_t)(base->DATA); #endif } } @@ -235,11 +238,11 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng */ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) { - assert(config); - assert(config->baudRate_Bps); + assert(NULL != config); + assert(0U < config->baudRate_Bps); #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); - assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); #endif uint32_t temp; @@ -253,16 +256,16 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t * iterate through the rest of the supported values of OSR */ baudDiff = config->baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) + osr = 0; + sbr = 0; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) { /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp)); + sbrTemp = (uint16_t)((srcClock_Hz / (config->baudRate_Bps * osrTemp))); /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) + if (sbrTemp == 0U) { - sbrTemp = 1; + sbrTemp = 1U; } /* Calculate the baud rate based on the temporary OSR and SBR values */ calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); @@ -270,23 +273,23 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t tempDiff = calculatedBaud - config->baudRate_Bps; /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U))))) { - tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U))); sbrTemp++; } if (tempDiff <= baudDiff) { baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ } } /* Check to see if actual baud rate is within 3% of desired baud rate * based on the best calculate OSR value */ - if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) { /* Unacceptable baud rate difference of more than 3%*/ return kStatus_LPUART_BaudrateNotSupport; @@ -316,14 +319,14 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) + if ((osr > 3U) && (osr < 8U)) { temp |= LPUART_BAUD_BOTHEDGE_MASK; } /* program the osr value (bit value is one less than actual value) */ temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); + temp |= LPUART_BAUD_OSR(osr - 1U); /* write the sbr value to the BAUD registers */ temp &= ~LPUART_BAUD_SBR_MASK; @@ -332,9 +335,8 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t /* Set bit count and parity mode. */ base->BAUD &= ~LPUART_BAUD_M10_MASK; - temp = base->CTRL & - ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK); + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType); @@ -364,7 +366,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT /* set stop bit per char */ - temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); #endif @@ -378,7 +380,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t 5 bytes are received. the last byte will be saved in FIFO but not trigger RX interrupt because the water mark is 2. */ - base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark); + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); /* Enable tx/rx FIFO */ base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); @@ -402,12 +404,12 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT /* Set the CTS configuration/TX CTS source. */ base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); - if (config->enableRxRTS) + if (true == config->enableRxRTS) { /* Enable the receiver RTS(request-to-send) function. */ base->MODIR |= LPUART_MODIR_RXRTSE_MASK; } - if (config->enableTxCTS) + if (true == config->enableTxCTS) { /* Enable the CTS(clear-to-send) function. */ base->MODIR |= LPUART_MODIR_TXCTSE_MASK; @@ -415,7 +417,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t #endif /* Set data bits order. */ - if (config->isMsb) + if (true == config->isMsb) { temp |= LPUART_STAT_MSBF_MASK; } @@ -428,12 +430,12 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t /* Enable TX/RX base on configure structure. */ temp = base->CTRL; - if (config->enableTx) + if (true == config->enableTx) { temp |= LPUART_CTRL_TE_MASK; } - if (config->enableRx) + if (true == config->enableRx) { temp |= LPUART_CTRL_RE_MASK; } @@ -455,12 +457,12 @@ void LPUART_Deinit(LPUART_Type *base) #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO /* Wait tx FIFO send out*/ - while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) { } #endif /* Wait last char shift out */ - while (0 == (base->STAT & LPUART_STAT_TC_MASK)) + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) { } @@ -515,15 +517,15 @@ void LPUART_Deinit(LPUART_Type *base) */ void LPUART_GetDefaultConfig(lpuart_config_t *config) { - assert(config); + assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); - config->baudRate_Bps = 115200U; - config->parityMode = kLPUART_ParityDisabled; + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; config->dataBitsCount = kLPUART_EightDataBits; - config->isMsb = false; + config->isMsb = false; #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT config->stopBitCount = kLPUART_OneStopBit; #endif @@ -537,10 +539,10 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config) config->txCtsConfig = kLPUART_CtsSampleAtStart; config->txCtsSource = kLPUART_CtsSourcePin; #endif - config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleType = kLPUART_IdleTypeStartBit; config->rxIdleConfig = kLPUART_IdleCharacter1; - config->enableTx = false; - config->enableRx = false; + config->enableTx = false; + config->enableRx = false; } /*! @@ -560,7 +562,7 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config) */ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { - assert(baudRate_Bps); + assert(0U < baudRate_Bps); uint32_t temp, oldCtrl; uint16_t sbr, sbrTemp; @@ -573,40 +575,40 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s * iterate through the rest of the supported values of OSR */ baudDiff = baudRate_Bps; - osr = 0; - sbr = 0; - for (osrTemp = 4; osrTemp <= 32; osrTemp++) + osr = 0; + sbr = 0; + for (osrTemp = 4u; osrTemp <= 32u; osrTemp++) { /* calculate the temporary sbr value */ - sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp)); + sbrTemp = (uint16_t)(srcClock_Hz / (baudRate_Bps * osrTemp)); /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ - if (sbrTemp == 0) + if (sbrTemp == 0u) { - sbrTemp = 1; + sbrTemp = 1u; } /* Calculate the baud rate based on the temporary OSR and SBR values */ - calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + calculatedBaud = (uint16_t)((srcClock_Hz / (osrTemp * sbrTemp))); tempDiff = calculatedBaud - baudRate_Bps; /* Select the better value between srb and (sbr + 1) */ - if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))))) + if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u))))) { - tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1))); + tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u))); sbrTemp++; } if (tempDiff <= baudDiff) { baudDiff = tempDiff; - osr = osrTemp; /* update and store the best OSR value calculated */ - sbr = sbrTemp; /* update store the best SBR value calculated */ + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ } } /* Check to see if actual baud rate is within 3% of desired baud rate * based on the best calculate OSR value */ - if (baudDiff < ((baudRate_Bps / 100) * 3)) + if (baudDiff < (uint32_t)((baudRate_Bps / 100u) * 3u)) { /* Store CTRL before disable Tx and Rx */ oldCtrl = base->CTRL; @@ -618,14 +620,14 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. * If so, then "BOTHEDGE" sampling must be turned on */ - if ((osr > 3) && (osr < 8)) + if ((osr > 3u) && (osr < 8u)) { temp |= LPUART_BAUD_BOTHEDGE_MASK; } /* program the osr value (bit value is one less than actual value) */ temp &= ~LPUART_BAUD_OSR_MASK; - temp |= LPUART_BAUD_OSR(osr - 1); + temp |= LPUART_BAUD_OSR(osr - 1u); /* write the sbr value to the BAUD registers */ temp &= ~LPUART_BAUD_SBR_MASK; @@ -658,10 +660,10 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s */ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) { - base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); + base->BAUD |= ((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | - ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + ((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); #endif mask &= 0xFFFFFF00U; base->CTRL |= mask; @@ -682,10 +684,10 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) */ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) { - base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); + base->BAUD &= ~((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & - ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + ~((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); #endif mask &= 0xFFFFFF00U; base->CTRL &= ~mask; @@ -714,11 +716,11 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) { uint32_t temp; - temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8U; #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8; + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8U; #endif - temp |= (base->CTRL & 0xFF0C000); + temp |= (uint32_t)(base->CTRL & 0xFF0C000u); return temp; } @@ -747,7 +749,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base) #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO temp |= (base->FIFO & (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> - 16; + 16U; #endif return temp; } @@ -778,7 +780,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO temp = (uint32_t)base->FIFO; temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); - temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); base->FIFO = temp; #endif temp = (uint32_t)base->STAT; @@ -796,7 +798,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) #endif base->STAT = temp; /* If some flags still pending. */ - if (mask & LPUART_GetStatusFlags(base)) + if (0U != (mask & LPUART_GetStatusFlags(base))) { /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, @@ -828,21 +830,26 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) */ void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) { - assert(data); + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; /* This API can only ensure that the data is written into the data buffer but can't ensure all data in the data buffer are sent into the transmit shift buffer. */ - while (length--) + while (0U != transferSize) { - while (!(base->STAT & LPUART_STAT_TDRE_MASK)) + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) { } - base->DATA = *(data++); + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; } } /*! -* brief Reads the receiver data register using a blocking method. + * brief Reads the receiver data register using a blocking method. * * This function polls the receiver register, waits for the receiver register full or receiver FIFO * has data, and reads data from the TX register. @@ -858,60 +865,69 @@ void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) */ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) { - assert(data); + assert(NULL != data); uint32_t statusFlag; + uint8_t *dataAddress = data; + #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT uint32_t ctrl = base->CTRL; bool isSevenDataBits = ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); #endif - while (length--) + while (0U != (length--)) { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) #else - while (!(base->STAT & LPUART_STAT_RDRF_MASK)) + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) #endif { statusFlag = LPUART_GetStatusFlags(base); - if (statusFlag & kLPUART_RxOverrunFlag) + if ((uint32_t)kLPUART_RxOverrunFlag == (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) { - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - return kStatus_LPUART_RxHardwareOverrun; + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); } - if (statusFlag & kLPUART_NoiseErrorFlag) + if ((uint32_t)kLPUART_NoiseErrorFlag == (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) { - LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag); - return kStatus_LPUART_NoiseError; + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); } - if (statusFlag & kLPUART_FramingErrorFlag) + if ((uint32_t)kLPUART_FramingErrorFlag == (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) { - LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag); - return kStatus_LPUART_FramingError; + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); } - if (statusFlag & kLPUART_ParityErrorFlag) + if ((uint32_t)kLPUART_ParityErrorFlag == (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) { - LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag); - return kStatus_LPUART_ParityError; + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); } } #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT if (isSevenDataBits) { - *(data++) = (base->DATA & 0x7F); + *(dataAddress) = (uint8_t)(base->DATA & 0x7F); + dataAddress++; } else { - *(data++) = base->DATA; + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; } #else - *(data++) = base->DATA; + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; #endif } @@ -941,9 +957,10 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_transfer_callback_t callback, void *userData) { - assert(handle); + assert(NULL != handle); uint32_t instance; + #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT uint32_t ctrl = base->CTRL; bool isSevenDataBits = @@ -951,11 +968,11 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, #endif /* Zero the handle. */ - memset(handle, 0, sizeof(lpuart_handle_t)); + (void)memset(handle, 0, sizeof(lpuart_handle_t)); /* Set the TX/RX state. */ - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; /* Set the callback and user data. */ handle->callback = callback; @@ -976,10 +993,10 @@ void LPUART_TransferCreateHandle(LPUART_Type *base, /* Enable interrupt in NVIC. */ #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ - EnableIRQ(s_lpuartRxIRQ[instance]); - EnableIRQ(s_lpuartTxIRQ[instance]); + (void)EnableIRQ(s_lpuartRxIRQ[instance]); + (void)EnableIRQ(s_lpuartTxIRQ[instance]); #else - EnableIRQ(s_lpuartIRQ[instance]); + (void)EnableIRQ(s_lpuartIRQ[instance]); #endif } @@ -1005,17 +1022,18 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base, uint8_t *ringBuffer, size_t ringBufferSize) { - assert(handle); - assert(ringBuffer); + assert(NULL != handle); + assert(NULL != ringBuffer); /* Setup the ring buffer address */ - handle->rxRingBuffer = ringBuffer; + handle->rxRingBuffer = ringBuffer; handle->rxRingBufferSize = ringBufferSize; handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; /* Enable the interrupt to accept the data when user need the ring buffer. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + LPUART_EnableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); } /*! @@ -1028,14 +1046,15 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base, */ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); - if (handle->rxState == kLPUART_RxIdle) + if (handle->rxState == (uint8_t)kLPUART_RxIdle) { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); } - handle->rxRingBuffer = NULL; + handle->rxRingBuffer = NULL; handle->rxRingBufferSize = 0U; handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; @@ -1062,27 +1081,27 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) */ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) { - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); status_t status; /* Return error if current TX busy. */ - if (kLPUART_TxBusy == handle->txState) + if ((uint8_t)kLPUART_TxBusy == handle->txState) { status = kStatus_LPUART_TxBusy; } else { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; handle->txDataSizeAll = xfer->dataSize; - handle->txState = kLPUART_TxBusy; + handle->txState = (uint8_t)kLPUART_TxBusy; /* Enable transmitter interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable); + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); status = kStatus_Success; } @@ -1101,12 +1120,13 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand */ void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); - LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable); + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable | (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); handle->txDataSize = 0; - handle->txState = kLPUART_TxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; } /*! @@ -1124,10 +1144,10 @@ void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) */ status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) { - assert(handle); - assert(count); + assert(NULL != handle); + assert(NULL != count); - if (kLPUART_TxIdle == handle->txState) + if ((uint8_t)kLPUART_TxIdle == handle->txState) { return kStatus_NoTransferInProgress; } @@ -1168,10 +1188,10 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_transfer_t *xfer, size_t *receivedBytes) { - assert(handle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); uint32_t i; status_t status; @@ -1192,25 +1212,25 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, save the xfer->data remained empty space to lpuart handle, receive data to this empty space and trigger callback when finished. */ - if (kLPUART_RxBusy == handle->rxState) + if ((uint8_t)kLPUART_RxBusy == handle->rxState) { status = kStatus_LPUART_RxBusy; } else { - bytesToReceive = xfer->dataSize; + bytesToReceive = xfer->dataSize; bytesCurrentReceived = 0; /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) + if (NULL != handle->rxRingBuffer) { /* Disable LPUART RX IRQ, protect ring buffer. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); /* How many bytes in RX ring buffer currently. */ bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); - if (bytesToCopy) + if (0U != bytesToCopy) { bytesToCopy = MIN(bytesToReceive, bytesToCopy); @@ -1219,10 +1239,11 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, /* Copy data from ring buffer to user memory. */ for (i = 0U; i < bytesToCopy; i++) { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + xfer->data[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + bytesCurrentReceived++; /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) { handle->rxRingBufferTail = 0U; } @@ -1234,21 +1255,21 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, } /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) + if (0U != bytesToReceive) { /* No data in ring buffer, save the request to LPUART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; + handle->rxState = (uint8_t)kLPUART_RxBusy; } /* Enable LPUART RX IRQ if previously enabled. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable); + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); /* Call user callback since all data are received. */ - if (0 == bytesToReceive) + if (0U == bytesToReceive) { - if (handle->callback) + if (NULL != handle->callback) { handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); } @@ -1257,18 +1278,19 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, /* Ring buffer not used. */ else { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kLPUART_RxBusy; + handle->rxState = (uint8_t)kLPUART_RxBusy; /* Enable RX interrupt. */ - LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); } /* Return the how many bytes have read. */ - if (receivedBytes) + if (NULL != receivedBytes) { *receivedBytes = bytesCurrentReceived; } @@ -1290,18 +1312,19 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, */ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) + if (NULL == handle->rxRingBuffer) { /* Disable RX interrupt. */ - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable | - kLPUART_IdleLineInterruptEnable); + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); } handle->rxDataSize = 0U; - handle->rxState = kLPUART_RxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; } /*! @@ -1318,10 +1341,10 @@ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) */ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) { - assert(handle); - assert(count); + assert(NULL != handle); + assert(NULL != count); - if (kLPUART_RxIdle == handle->rxState) + if ((uint8_t)kLPUART_RxIdle == handle->rxState) { return kStatus_NoTransferInProgress; } @@ -1341,35 +1364,36 @@ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *hand */ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) { - assert(handle); + assert(NULL != handle); uint8_t count; uint8_t tempCount; - uint32_t status = LPUART_GetStatusFlags(base); + uint32_t status = LPUART_GetStatusFlags(base); uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); /* If RX overrun. */ - if (kLPUART_RxOverrunFlag & status) + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) { /* Clear overrun flag, otherwise the RX does not work. */ base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); /* Trigger callback. */ - if (handle->callback) + if (NULL != (handle->callback)) { handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); } } /* If IDLE flag is set and the IDLE interrupt is enabled. */ - if ((kLPUART_IdleLineFlag & status) && (kLPUART_IdleLineInterruptEnable & enabledInterrupts)) + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); - while ((count) && (handle->rxDataSize)) + while ((0U != handle->rxDataSize) && (0U != count)) { - tempCount = MIN(handle->rxDataSize, count); + tempCount = (uint8_t)MIN(handle->rxDataSize, count); /* Using non block API to read the data from the registers. */ LPUART_ReadNonBlocking(base, handle->rxData, tempCount); @@ -1378,12 +1402,13 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) count -= tempCount; /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) + if (0U == (handle->rxDataSize)) { - handle->rxState = kLPUART_RxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); - if (handle->callback) + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + if (NULL != handle->callback) { handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); } @@ -1394,18 +1419,19 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) base->STAT |= LPUART_STAT_IDLE_MASK; /* If rxDataSize is 0, disable idle line interrupt.*/ - if (!(handle->rxDataSize)) + if (0U != (handle->rxDataSize)) { - LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable); + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_IdleLineInterruptEnable); } /* If callback is not NULL and rxDataSize is not 0. */ - if ((handle->callback) && (handle->rxDataSize)) + if ((0U != handle->rxDataSize) && (NULL != handle->callback)) { handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); } } /* Receive data register full */ - if ((kLPUART_RxDataRegFullFlag & status) && (kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts)) + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) { /* Get the size that can be stored into buffer for this interrupt. */ #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO @@ -1415,10 +1441,10 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) #endif /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ - while ((count) && (handle->rxDataSize)) + while ((0U != handle->rxDataSize) && (0U != count)) { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->rxDataSize, count); + tempCount = (uint8_t)MIN(handle->rxDataSize, count); #else tempCount = 1; #endif @@ -1430,11 +1456,11 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) count -= tempCount; /* If all the data required for upper layer is ready, trigger callback. */ - if (!handle->rxDataSize) + if (0U == handle->rxDataSize) { - handle->rxState = kLPUART_RxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; - if (handle->callback) + if (NULL != handle->callback) { handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); } @@ -1442,24 +1468,24 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } /* If use RX ring buffer, receive data to ring buffer. */ - if (handle->rxRingBuffer) + if (NULL != handle->rxRingBuffer) { - while (count--) + while (0U != count--) { /* If RX ring buffer is full, trigger callback to notify over run. */ if (LPUART_TransferIsRxRingBufferFull(base, handle)) { - if (handle->callback) + if (NULL != handle->callback) { handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); } } - /* If ring buffer is still full after callback function, the oldest data is overrided. */ + /* If ring buffer is still full after callback function, the oldest data is overridden. */ if (LPUART_TransferIsRxRingBufferFull(base, handle)) { /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) { handle->rxRingBufferTail = 0U; } @@ -1480,11 +1506,13 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; } #else - handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; + uint16_t tpmRxRingBufferHead = handle->rxRingBufferHead; + uint32_t tpmData = base->DATA; + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; #endif /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) { handle->rxRingBufferHead = 0U; } @@ -1495,9 +1523,10 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } } /* If no receive requst pending, stop RX interrupt. */ - else if (!handle->rxDataSize) + else if (0U == handle->rxDataSize) { - LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable); + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); } else { @@ -1505,20 +1534,21 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) } /* Send data register empty and the interrupt is enabled. */ - if ((kLPUART_TxDataRegEmptyFlag & status) && (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)) + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) { /* Get the bytes that available at this moment. */ #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) - - ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); #else count = 1; #endif - while ((count) && (handle->txDataSize)) + while ((0U != handle->txDataSize) && (0U != count)) { #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - tempCount = MIN(handle->txDataSize, count); + tempCount = (uint8_t)MIN(handle->txDataSize, count); #else tempCount = 1; #endif @@ -1530,15 +1560,15 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) count -= tempCount; /* If all the data are written to data register, notify user with the callback, then TX finished. */ - if (!handle->txDataSize) + if (0U == handle->txDataSize) { - handle->txState = kLPUART_TxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; /* Disable TX register empty interrupt. */ base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); /* Trigger callback. */ - if (handle->callback) + if (NULL != handle->callback) { handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); } @@ -1563,18 +1593,23 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ void LPUART0_LPUART1_RX_DriverIRQHandler(void) { + uint32_t stat = 0U; + uint32_t ctrl = 0U; + if (CLOCK_isEnabledClock(s_lpuartClock[0])) { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL))) + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } } if (CLOCK_isEnabledClock(s_lpuartClock[1])) { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL))) + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } @@ -1587,18 +1622,23 @@ void LPUART0_LPUART1_RX_DriverIRQHandler(void) } void LPUART0_LPUART1_TX_DriverIRQHandler(void) { + uint32_t stat = 0U; + uint32_t ctrl = 0U; + if (CLOCK_isEnabledClock(s_lpuartClock[0])) { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } } if (CLOCK_isEnabledClock(s_lpuartClock[1])) { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } @@ -1612,20 +1652,27 @@ void LPUART0_LPUART1_TX_DriverIRQHandler(void) #else void LPUART0_LPUART1_DriverIRQHandler(void) { + uint32_t stat = 0U; + uint32_t ctrl = 0U; + if (CLOCK_isEnabledClock(s_lpuartClock[0])) { - if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || - ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK))) + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((0U != (LPUART_STAT_OR_MASK & stat)) || + ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || + ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } } if (CLOCK_isEnabledClock(s_lpuartClock[1])) { - if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || - ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || - ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK))) + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((0U != (LPUART_STAT_OR_MASK & stat)) || + ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || + ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h index 419951fcbf971..ddfa6f6d6b451 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,27 +21,27 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPUART driver version 2.2.6. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) +/*! @brief LPUART driver version 2.2.7. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 7)) /*@}*/ /*! @brief Error codes for the LPUART driver. */ enum _lpuart_status { - kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ - kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ - kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ - kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ - kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ - kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ - kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ kStatus_LPUART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ - kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ - kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ - kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ - kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ kStatus_LPUART_BaudrateNotSupport = MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ @@ -51,8 +51,8 @@ enum _lpuart_status typedef enum _lpuart_parity_mode { kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ } lpuart_parity_mode_t; /*! @brief LPUART data bits count. */ @@ -75,7 +75,7 @@ typedef enum _lpuart_stop_bit_count /*! @brief LPUART transmit CTS source. */ typedef enum _lpuart_transmit_cts_source { - kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ } lpuart_transmit_cts_source_t; @@ -83,7 +83,7 @@ typedef enum _lpuart_transmit_cts_source typedef enum _lpuart_transmit_cts_config { kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ - kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ } lpuart_transmit_cts_config_t; #endif @@ -91,7 +91,7 @@ typedef enum _lpuart_transmit_cts_config typedef enum _lpuart_idle_type_select { kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ - kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ } lpuart_idle_type_select_t; /*! @brief LPUART idle detected configuration. @@ -100,13 +100,13 @@ typedef enum _lpuart_idle_type_select */ typedef enum _lpuart_idle_config { - kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ - kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ } lpuart_idle_config_t; @@ -120,17 +120,17 @@ enum _lpuart_interrupt_enable #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ #endif - kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ - kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ - kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ - kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ - kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ - kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ - kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ - kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ - kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO - kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ #endif }; @@ -148,18 +148,17 @@ enum _lpuart_flags (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ - kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ - kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is - read from receive register */ - kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these - samples differ, noise flag sets */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ kLPUART_FramingErrorFlag = (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT - kLPUART_LinBreakFlag = - (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char - detected and LIN circuit enabled */ + kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled */ #endif kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ @@ -173,7 +172,7 @@ enum _lpuart_flags kLPUART_NoiseErrorInRxDataRegFlag = (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ kLPUART_ParityErrorInRxDataRegFlag = - (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */ + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITY bit, sets if noise detected in current data word */ #endif #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ @@ -615,7 +614,7 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base) return base->DATA; } #else - return base->DATA; + return (uint8_t)(base->DATA); #endif } @@ -636,7 +635,7 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base) void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); /*! -* @brief Reads the receiver data register using a blocking method. + * @brief Reads the receiver data register using a blocking method. * * This function polls the receiver register, waits for the receiver register full or receiver FIFO * has data, and reads data from the TX register. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c index 4313f147c608c..5e7561399cdd3 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -77,7 +77,7 @@ enum _lpuart_edma_tansfer_states #endif /* LPUART 8 */ /*base, lpuartPrivateHandle->handle); - if (lpuartPrivateHandle->handle->callback) + if (NULL != lpuartPrivateHandle->handle->callback) { lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); @@ -133,20 +133,20 @@ static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool tra static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) { - assert(param); + assert(NULL != param); lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; /* Avoid warning for unused parameters. */ handle = handle; - tcds = tcds; + tcds = tcds; if (transferDone) { /* Disable transfer. */ LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); - if (lpuartPrivateHandle->handle->callback) + if (NULL != lpuartPrivateHandle->handle->callback) { lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); @@ -170,17 +170,17 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle) { - assert(handle); + assert(NULL != handle); uint32_t instance = LPUART_GetInstance(base); - s_edmaPrivateHandle[instance].base = base; - s_edmaPrivateHandle[instance].handle = handle; + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); - handle->rxState = kLPUART_RxIdle; - handle->txState = kLPUART_TxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; handle->rxEdmaHandle = rxEdmaHandle; handle->txEdmaHandle = txEdmaHandle; @@ -197,22 +197,22 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, 5 bytes are received. the last byte will be saved in FIFO but not trigger EDMA transfer because the water mark is 2. */ - if (rxEdmaHandle) + if (NULL != rxEdmaHandle) { base->WATER &= (~LPUART_WATER_RXWATER_MASK); } #endif /* Configure TX. */ - if (txEdmaHandle) + if (NULL != txEdmaHandle) { - EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); } /* Configure RX. */ - if (rxEdmaHandle) + if (NULL != rxEdmaHandle) { - EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); } } @@ -231,34 +231,39 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, */ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) { - assert(handle); - assert(handle->txEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); edma_transfer_config_t xferConfig; status_t status; /* If previous TX not finished. */ - if (kLPUART_TxBusy == handle->txState) + if ((uint8_t)kLPUART_TxBusy == handle->txState) { status = kStatus_LPUART_TxBusy; } else { - handle->txState = kLPUART_TxBusy; + handle->txState = (uint8_t)kLPUART_TxBusy; handle->txDataSizeAll = xfer->dataSize; /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base), - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); + handle->nbytes = (uint8_t)sizeof(uint8_t); /* Submit transfer. */ - EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } EDMA_StartTransfer(handle->txEdmaHandle); /* Enable LPUART TX EDMA. */ @@ -285,34 +290,38 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart */ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) { - assert(handle); - assert(handle->rxEdmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); edma_transfer_config_t xferConfig; status_t status; /* If previous RX not finished. */ - if (kLPUART_RxBusy == handle->rxState) + if ((uint8_t)kLPUART_RxBusy == handle->rxState) { status = kStatus_LPUART_RxBusy; } else { - handle->rxState = kLPUART_RxBusy; + handle->rxState = (uint8_t)kLPUART_RxBusy; handle->rxDataSizeAll = xfer->dataSize; /* Prepare transfer. */ - EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, - sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ - handle->nbytes = sizeof(uint8_t); + handle->nbytes = (uint8_t)sizeof(uint8_t); /* Submit transfer. */ - EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } EDMA_StartTransfer(handle->rxEdmaHandle); /* Enable LPUART RX EDMA. */ @@ -334,8 +343,8 @@ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpu */ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) { - assert(handle); - assert(handle->txEdmaHandle); + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); /* Disable LPUART TX EDMA. */ LPUART_EnableTxDMA(base, false); @@ -343,7 +352,7 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl /* Stop transfer. */ EDMA_AbortTransfer(handle->txEdmaHandle); - handle->txState = kLPUART_TxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; } /*! @@ -356,8 +365,8 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl */ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) { - assert(handle); - assert(handle->rxEdmaHandle); + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); /* Disable LPUART RX EDMA. */ LPUART_EnableRxDMA(base, false); @@ -365,7 +374,7 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha /* Stop transfer. */ EDMA_AbortTransfer(handle->rxEdmaHandle); - handle->rxState = kLPUART_RxIdle; + handle->rxState = (uint8_t)kLPUART_RxIdle; } /*! @@ -382,18 +391,18 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha */ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) { - assert(handle); - assert(handle->rxEdmaHandle); - assert(count); + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); - if (kLPUART_RxIdle == handle->rxState) + if ((uint8_t)kLPUART_RxIdle == handle->rxState) { return kStatus_NoTransferInProgress; } *count = handle->rxDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); return kStatus_Success; } @@ -413,18 +422,18 @@ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handl */ status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) { - assert(handle); - assert(handle->txEdmaHandle); - assert(count); + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); - if (kLPUART_TxIdle == handle->txState) + if ((uint8_t)kLPUART_TxIdle == handle->txState) { return kStatus_NoTransferInProgress; } *count = handle->txDataSizeAll - - (uint32_t)handle->nbytes * - EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); return kStatus_Success; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h index 70e456fbd839a..53ac71036bf84 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPUART EDMA driver version 2.2.6. */ -#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) +/*! @brief LPUART EDMA driver version 2.2.7. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 7)) /*@}*/ /* Forward declaration of the handle typedef. */ @@ -36,8 +36,8 @@ typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, void *userData); /*! -* @brief LPUART eDMA handle -*/ + * @brief LPUART eDMA handle + */ struct _lpuart_edma_handle { lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c index 5de591885261c..2d15e76865e71 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.c @@ -67,7 +67,7 @@ static uint32_t PIT_GetInstance(PIT_Type *base) */ void PIT_Init(PIT_Type *base, const pit_config_t *config) { - assert(config); + assert(NULL != config); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Ungate the PIT clock*/ @@ -81,14 +81,14 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config) #if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT) /* Clear the timer enable bit for all channels to make sure the channel's timer is disabled. */ - for (uint8_t i = 0U; i < FSL_FEATURE_PIT_TIMER_COUNT; i++) + for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++) { base->CHANNEL[i].TCTRL &= ~PIT_TCTRL_TEN_MASK; } #endif /* FSL_FEATURE_PIT_TIMER_COUNT */ /* Config timer operation when in debug mode */ - if (config->enableRunInDebug) + if (true == config->enableRunInDebug) { base->MCR &= ~PIT_MCR_FRZ_MASK; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.h b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.h index 667ce8df269fc..1de4984358f17 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pit.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pit.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief PIT Driver Version 2.0.1 */ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief PIT Driver Version 2.0.2 */ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @@ -104,7 +104,7 @@ void PIT_Deinit(PIT_Type *base); */ static inline void PIT_GetDefaultConfig(pit_config_t *config) { - assert(config); + assert(NULL != config); /* Timers are stopped in Debug mode */ config->enableRunInDebug = false; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h index e885646825516..6d9639d22eb42 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PMU_H_ @@ -65,10 +65,10 @@ typedef enum _pmu_3p0_vbus_voltage_source */ typedef enum _pmu_core_reg_voltage_ramp_rate { - kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */ + kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */ kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */ kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */ - kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */ + kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */ } pmu_core_reg_voltage_ramp_rate_t; #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL @@ -77,11 +77,11 @@ typedef enum _pmu_core_reg_voltage_ramp_rate */ enum _pmu_power_gate { - kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */ - kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */ - kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */ - kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */ - kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */ + kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */ + kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */ + kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */ + kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */ + kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */ }; #endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ @@ -91,7 +91,7 @@ enum _pmu_power_gate typedef enum _pmu_power_bandgap { kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */ - kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */ + kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */ } pmu_power_bandgap_t; /******************************************************************************* @@ -108,10 +108,10 @@ extern "C" { */ /*! - * @brief Get PMU status flags. + * @brief Get PMU status flags. * * @param base PMU peripheral base address. - * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok + * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok * and brownout output of 1P1,3P0 and 2P5 is detected. */ uint32_t PMU_GetStatusFlags(PMU_Type *base); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c index fb6ad2237f005..ebb9d283ddda6 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c @@ -393,14 +393,14 @@ status_t PWM_SetupPwm(PWM_Type *base, */ if (chnlParams->pwmChannel == kPWM_PwmA) { - polarityShift = PWM_OCTRL_POLA_SHIFT; - outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); } else { - polarityShift = PWM_OCTRL_POLB_SHIFT; - outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); } @@ -452,7 +452,7 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base, switch (currPwmMode) { case kPWM_SignedCenterAligned: - modulo = base->SM[subModule].VAL1; + modulo = base->SM[subModule].VAL1; pulseCnt = modulo * 2; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; @@ -487,7 +487,7 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base, } break; case kPWM_SignedEdgeAligned: - modulo = base->SM[subModule].VAL1; + modulo = base->SM[subModule].VAL1; pulseCnt = modulo * 2; /* Calculate pulse width */ pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; @@ -803,7 +803,7 @@ void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t ma uint16_t reg; base->SM[subModule].STS = (mask & 0xFFFFU); - reg = base->FSTS; + reg = base->FSTS; /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared * by writing a login one */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.h b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.h index 36e2d3155b3b5..29e78a2be1a8c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_pwm.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_PWM_H_ @@ -15,7 +15,6 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ @@ -183,18 +182,18 @@ typedef enum _pwm_interrupt_enable kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ - kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ - kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ - kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ - kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ - kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ - kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ - kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ - kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ - kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ - kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ - kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ } pwm_interrupt_enable_t; /*! @brief List of PWM status flags */ @@ -206,19 +205,19 @@ typedef enum _pwm_status_flags kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ - kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ - kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ - kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ - kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ - kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ - kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ - kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ - kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ - kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ - kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ - kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ - kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ } pwm_status_flags_t; /*! @brief PWM operation mode */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c index 5d4c556aee110..88294a994faed 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c @@ -182,8 +182,8 @@ status_t QTMR_SetupPwm(TMR_Type *base, /* Counter values to generate a PWM signal */ periodCount = (srcClock_Hz / pwmFreqHz); - highCount = (periodCount * dutyCyclePercent) / 100; - lowCount = periodCount - highCount; + highCount = (periodCount * dutyCyclePercent) / 100; + lowCount = periodCount - highCount; /* Setup the compare registers for PWM output */ base->CHANNEL[channel].COMP1 = lowCount; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.h b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.h index 87329499e3ab1..26d1204ebb2b1 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.h @@ -1,7 +1,7 @@ /* * Copyright 2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_QTMR_H_ @@ -14,7 +14,6 @@ * @{ */ - /******************************************************************************* * Definitions ******************************************************************************/ @@ -109,21 +108,21 @@ typedef enum _qtmr_debug_action /*! @brief List of Quad Timer interrupts */ typedef enum _qtmr_interrupt_enable { - kQTMR_CompareInterruptEnable = (1U << 0), /*!< Compare interrupt.*/ + kQTMR_CompareInterruptEnable = (1U << 0), /*!< Compare interrupt.*/ kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/ kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/ kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/ - kQTMR_EdgeInterruptEnable = (1U << 4) /*!< Input edge interrupt.*/ + kQTMR_EdgeInterruptEnable = (1U << 4) /*!< Input edge interrupt.*/ } qtmr_interrupt_enable_t; /*! @brief List of Quad Timer flags */ typedef enum _qtmr_status_flags { - kQTMR_CompareFlag = (1U << 0), /*!< Compare flag */ + kQTMR_CompareFlag = (1U << 0), /*!< Compare flag */ kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */ kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */ kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */ - kQTMR_EdgeFlag = (1U << 4) /*!< Input edge flag */ + kQTMR_EdgeFlag = (1U << 4) /*!< Input edge flag */ } qtmr_status_flags_t; /*! @brief List of channel selection */ @@ -138,7 +137,7 @@ typedef enum _qtmr_channel_selection /*! @brief List of Quad Timer DMA enable */ typedef enum _qtmr_dma_enable { - kQTMR_InputEdgeFlagDmaEnable = (1U << 0), /*!< Input Edge Flag DMA Enable.*/ + kQTMR_InputEdgeFlagDmaEnable = (1U << 0), /*!< Input Edge Flag DMA Enable.*/ kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/ kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/ } qtmr_dma_enable_t; @@ -233,8 +232,12 @@ void QTMR_GetDefaultConfig(qtmr_config_t *config); * * @return Returns an error if there was error setting up the signal. */ -status_t QTMR_SetupPwm( - TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz); +status_t QTMR_SetupPwm(TMR_Type *base, + qtmr_channel_selection_t channel, + uint32_t pwmFreqHz, + uint8_t dutyCyclePercent, + bool outputPolarity, + uint32_t srcClock_Hz); /*! * @brief Allows the user to count the source clock cycles until a capture event arrives. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c index da3587a55a7b3..9a32bd8064eab 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c @@ -69,18 +69,18 @@ void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableRtwdog = true; - config->clockSource = kRTWDOG_ClockSource1; - config->prescaler = kRTWDOG_ClockPrescalerDivide1; - config->workMode.enableWait = true; - config->workMode.enableStop = false; + config->enableRtwdog = true; + config->clockSource = kRTWDOG_ClockSource1; + config->prescaler = kRTWDOG_ClockPrescalerDivide1; + config->workMode.enableWait = true; + config->workMode.enableStop = false; config->workMode.enableDebug = false; - config->testMode = kRTWDOG_TestModeDisabled; - config->enableUpdate = true; - config->enableInterrupt = false; - config->enableWindowMode = false; - config->windowValue = 0U; - config->timeoutValue = 0xFFFFU; + config->testMode = kRTWDOG_TestModeDisabled; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; } /*! @@ -106,7 +106,7 @@ void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) { assert(config); - uint32_t value = 0U; + uint32_t value = 0U; uint32_t primaskValue = 0U; value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | @@ -119,9 +119,9 @@ void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ primaskValue = DisableGlobalIRQ(); RTWDOG_Unlock(base); - base->WIN = config->windowValue; + base->WIN = config->windowValue; base->TOVAL = config->timeoutValue; - base->CS = value; + base->CS = value; while ((base->CS & RTWDOG_CS_RCS_MASK) == 0) { } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h index 42c5eb7878265..0b1b4fb4973c4 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h @@ -47,7 +47,7 @@ typedef enum _rtwdog_clock_source /*! @brief Describes the selection of the clock prescaler. */ typedef enum _rtwdog_clock_prescaler { - kRTWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kRTWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ kRTWDOG_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ } rtwdog_clock_prescaler_t; @@ -63,9 +63,9 @@ typedef struct _rtwdog_work_mode typedef enum _rtwdog_test_mode { kRTWDOG_TestModeDisabled = 0U, /*!< Test Mode disabled */ - kRTWDOG_UserModeEnabled = 1U, /*!< User Mode enabled */ - kRTWDOG_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ - kRTWDOG_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ + kRTWDOG_UserModeEnabled = 1U, /*!< User Mode enabled */ + kRTWDOG_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ + kRTWDOG_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ } rtwdog_test_mode_t; /*! @brief Describes RTWDOG configuration structure. */ @@ -100,7 +100,7 @@ enum _rtwdog_interrupt_enable_t */ enum _rtwdog_status_flags_t { - kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK, /*!< Running flag, set when RTWDOG is enabled */ + kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK, /*!< Running flag, set when RTWDOG is enabled */ kRTWDOG_InterruptFlag = RTWDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ }; @@ -262,6 +262,43 @@ static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base) return (base->CS & (RTWDOG_CS_EN_MASK | RTWDOG_CS_FLG_MASK)); } +/*! + * @brief Enables/disables the window mode. + * + * @param base RTWDOG peripheral base address. + * @param enable Enables(true) or disables(false) the feature. + */ +static inline void RTWDOG_EnableWindowMode(RTWDOG_Type *base, bool enable) +{ + if (enable) + { + base->CS |= RTWDOG_CS_WIN_MASK; + } + else + { + base->CS &= ~RTWDOG_CS_WIN_MASK; + } +} + +/*! + * @brief Converts raw count value to millisecond. + * + * Note that if the clock frequency is too high the timeout period can be less than 1 ms. + * In this case this api will return 0 value. + * + * @param base RTWDOG peripheral base address. + * @param count Raw count value. + # @param clockFreqInHz The frequency of the clock source RTWDOG uses. + */ +static inline uint32_t RTWDOG_CountToMesec(RTWDOG_Type *base, uint32_t count, uint32_t clockFreqInHz) +{ + if ((base->CS & RTWDOG_CS_PRES_MASK) >> RTWDOG_CS_PRES_SHIFT) + { + clockFreqInHz /= 256; + } + return count * 1000U / clockFreqInHz; +} + /*! * @brief Clears the RTWDOG flag. * @@ -346,7 +383,7 @@ static inline void RTWDOG_Unlock(RTWDOG_Type *base) static inline void RTWDOG_Refresh(RTWDOG_Type *base) { uint32_t primaskValue = 0U; - primaskValue = DisableGlobalIRQ(); + primaskValue = DisableGlobalIRQ(); if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) { base->CNT = RTWDOG_REFRESH_KEY; diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c index 19cd7e4989347..3e7522bb8c422 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.c @@ -20,7 +20,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ @@ -91,6 +91,19 @@ static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations + * @param bitWidth audio data bitWidth. + * @param mode audio data channel + * @param saiChannelMask channel mask value to enable + */ +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); /******************************************************************************* * Variables ******************************************************************************/ @@ -118,12 +131,12 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t { uint32_t freq = mclkSrcClock_Hz; uint16_t fract, divide; - uint32_t remaind = 0; + uint32_t remaind = 0; uint32_t current_remainder = 0xFFFFFFFFU; - uint16_t current_fract = 0; - uint16_t current_divide = 0; - uint32_t mul_freq = 0; - uint32_t max_fract = 256; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; /*In order to prevent overflow */ freq /= 100; @@ -140,13 +153,13 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t for (fract = 1; fract < max_fract; fract++) { mul_freq = freq * fract; - remaind = mul_freq % mclk_Hz; - divide = mul_freq / mclk_Hz; + remaind = mul_freq % mclk_Hz; + divide = mul_freq / mclk_Hz; /* Find the exactly frequency */ if (remaind == 0) { - current_fract = fract; + current_fract = fract; current_divide = mul_freq / mclk_Hz; break; } @@ -161,8 +174,8 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t /* Update the closest div and fract */ if (remaind < current_remainder) { - current_fract = fract; - current_divide = divide; + current_fract = fract; + current_divide = divide; current_remainder = remaind; } } @@ -206,8 +219,8 @@ static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t i = 0; uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; - uint32_t temp = 0; + uint32_t data = 0; + uint32_t temp = 0; for (i = 0; i < size / bytesPerWord; i++) { @@ -222,7 +235,7 @@ static void SAI_WriteNonBlocking(I2S_Type *base, buffer++; } base->TDR[j] = data; - data = 0; + data = 0; } } } @@ -239,7 +252,7 @@ static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t i = 0; uint8_t j = 0, m = 0; uint8_t bytesPerWord = bitWidth / 8U; - uint32_t data = 0; + uint32_t data = 0; for (i = 0; i < size / bytesPerWord; i++) { @@ -258,9 +271,64 @@ static void SAI_ReadNonBlocking(I2S_Type *base, } } +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + memset(config, 0U, sizeof(sai_transceiver_t)); + + config->channelMask = saiChannelMask; + /* sync mode default configurations */ + config->syncMode = kSAI_ModeAsync; + + /* master mode default */ + config->masterSlave = kSAI_Master; + + /* bit default configurations */ + config->bitClock.bclkSrcSwap = false; + config->bitClock.bclkInputDelay = false; + config->bitClock.bclkPolarity = kSAI_SampleOnRisingEdge; + config->bitClock.bclkSource = kSAI_BclkSourceMclkDiv; + + /* frame sync default configurations */ + config->frameSync.frameSyncWidth = bitWidth; + config->frameSync.frameSyncEarly = true; +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + config->frameSync.frameSyncGenerateOnDemand = false; +#endif + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow; + + /* serial data default configurations */ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + config->serialData.dataMode = kSAI_DataPinStateOutputZero; +#endif + config->serialData.dataOrder = kSAI_DataMSB; + config->serialData.dataWord0Length = bitWidth; + config->serialData.dataWordLength = bitWidth; + config->serialData.dataWordNLength = bitWidth; + config->serialData.dataFirstBitShifted = bitWidth; + config->serialData.dataWordNum = 2U; + config->serialData.dataMaskedWord = mode; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* fifo configurations */ + config->fifo.fifoWatermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + config->fifo.fifoContinueOneError = true; +#endif +} + /*! * brief Initializes the SAI Tx peripheral. * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. * The configuration structure can be custom filled or set with default values by * SAI_TxGetDefaultConfig(). @@ -271,7 +339,7 @@ static void SAI_ReadNonBlocking(I2S_Type *base, * * param base SAI base pointer * param config SAI configuration structure. -*/ + */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) { uint32_t val = 0; @@ -284,12 +352,12 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); + val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); #endif /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); + val = (base->MCR & ~I2S_MCR_MOE_MASK); base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ @@ -339,7 +407,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) base->TCR4 |= I2S_TCR4_FSD_MASK; /* Bit clock source setting */ - val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); } else @@ -365,6 +433,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) val &= ~I2S_RCR2_SYNC_MASK; base->RCR2 = (val | I2S_RCR2_SYNC(0U)); break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) case kSAI_ModeSyncWithOtherTx: val = base->TCR2; val &= ~I2S_TCR2_SYNC_MASK; @@ -375,6 +444,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) val &= ~I2S_TCR2_SYNC_MASK; base->TCR2 = (val | I2S_TCR2_SYNC(3U)); break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ default: break; } @@ -387,6 +457,8 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) /*! * brief Initializes the SAI Rx peripheral. * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. * The configuration structure can be custom filled or set with default values by * SAI_RxGetDefaultConfig(). @@ -410,12 +482,12 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) /* Master clock source setting */ - val = (base->MCR & ~I2S_MCR_MICS_MASK); + val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); #endif /* Configure Master clock output enable */ - val = (base->MCR & ~I2S_MCR_MOE_MASK); + val = (base->MCR & ~I2S_MCR_MOE_MASK); base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ @@ -465,7 +537,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) base->RCR4 |= I2S_RCR4_FSD_MASK; /* Bit clock source setting */ - val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); } else @@ -491,6 +563,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) val &= ~I2S_TCR2_SYNC_MASK; base->TCR2 = (val | I2S_TCR2_SYNC(0U)); break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) case kSAI_ModeSyncWithOtherTx: val = base->RCR2; val &= ~I2S_RCR2_SYNC_MASK; @@ -501,6 +574,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) val &= ~I2S_RCR2_SYNC_MASK; base->RCR2 = (val | I2S_RCR2_SYNC(3U)); break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ default: break; } @@ -510,6 +584,21 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) #endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ } +/*! + * brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Init(I2S_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + /*! * brief De-initializes the SAI peripheral. * @@ -517,7 +606,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) * or SAI_RxInit is called to enable the clock. * * param base SAI base pointer -*/ + */ void SAI_Deinit(I2S_Type *base) { SAI_TxEnable(base, false); @@ -530,6 +619,9 @@ void SAI_Deinit(I2S_Type *base) /*! * brief Sets the SAI Tx configuration structure to default values. * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * * This API initializes the configuration structure for use in SAI_TxConfig(). * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified * before calling SAI_TxConfig(). @@ -546,7 +638,7 @@ void SAI_TxGetDefaultConfig(sai_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->bclkSource = kSAI_BclkSourceMclkDiv; + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; @@ -561,6 +653,9 @@ void SAI_TxGetDefaultConfig(sai_config_t *config) /*! * brief Sets the SAI Rx configuration structure to default values. * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * * This API initializes the configuration structure for use in SAI_RxConfig(). * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified * before calling SAI_RxConfig(). @@ -577,7 +672,7 @@ void SAI_RxGetDefaultConfig(sai_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->bclkSource = kSAI_BclkSourceMclkDiv; + config->bclkSource = kSAI_BclkSourceMclkDiv; config->masterSlave = kSAI_Master; #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) config->mclkOutputEnable = true; @@ -609,7 +704,7 @@ void SAI_TxReset(I2S_Type *base) base->TCR3 = 0; base->TCR4 = 0; base->TCR5 = 0; - base->TMR = 0; + base->TMR = 0; } /*! @@ -632,7 +727,7 @@ void SAI_RxReset(I2S_Type *base) base->RCR3 = 0; base->RCR4 = 0; base->RCR5 = 0; - base->RMR = 0; + base->RMR = 0; } /*! @@ -698,7 +793,7 @@ void SAI_RxEnable(I2S_Type *base, bool enable) * brief Do software reset or FIFO reset . * * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software * reset will not clear any configuration registers like TCR1~TCR5. * This function will also clear all the error flags such as FIFO error, sync error etc. * @@ -717,7 +812,7 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) * brief Do software reset or FIFO reset . * * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software * reset will not clear any configuration registers like RCR1~RCR5. * This function will also clear all the error flags such as FIFO error, sync error etc. * @@ -859,11 +954,11 @@ void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) } /*! -* brief Set Rx FIFO packing feature. -* -* param base SAI base pointer. -* param pack FIFO pack type. It is element of sai_fifo_packing_t. -*/ + * brief Set Rx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) { uint32_t val = base->RCR4; @@ -874,9 +969,760 @@ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) } #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t tcr2 = base->TCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + tcr2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + tcr2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1U); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t rcr2 = base->RCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + rcr2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + rcr2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1U); + } + + base->RCR2 = rcr2; +} + +/*! + * brief Transmitter Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t tcr2 = base->TCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK); + tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) | + I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource); + } + else + { + tcr2 &= ~(I2S_TCR2_BCD_MASK); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t rcr2 = base->RCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK); + rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) | + I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource); + } + else + { + rcr2 &= ~(I2S_RCR2_BCD_MASK); + } + + base->RCR2 = rcr2; +} + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * brief Master clock configurations. + * + * param base SAI base pointer. + * param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config) +{ + assert(config != NULL); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + uint32_t val = 0; + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (config->mclkOutputEnable) + { + SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +} +#endif + +/*! + * brief SAI transmitter fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + + uint32_t tcr4 = base->TCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + tcr4 &= ~I2S_TCR4_FCOMB_MASK; + tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + tcr4 &= ~I2S_TCR4_FCONT_MASK; + tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + tcr4 &= ~I2S_TCR4_FPACK_MASK; + tcr4 |= I2S_TCR4_FPACK(config->fifoPacking); +#endif + + base->TCR4 = tcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI receiver fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + uint32_t rcr4 = base->RCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + rcr4 &= ~I2S_RCR4_FCOMB_MASK; + rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + rcr4 &= ~I2S_RCR4_FCONT_MASK; + rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + rcr4 &= ~I2S_RCR4_FPACK_MASK; + rcr4 |= I2S_RCR4_FPACK(config->fifoPacking); +#endif + + base->RCR4 = rcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI transmitter Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + uint32_t tcr4 = base->TCR4; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) + { + assert(config != NULL); + assert((config->frameSyncWidth - 1U) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT)); + + tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + tcr4 &= ~I2S_TCR4_ONDEM_MASK; + tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + tcr4 |= I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) | I2S_TCR4_FSD(1U) | + I2S_TCR4_SYWD(config->frameSyncWidth - 1U); + } + else + { + tcr4 &= ~I2S_TCR4_FSD_MASK; + } + + base->TCR4 = tcr4; +} + +/*! + * brief SAI receiver Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + uint32_t rcr4 = base->RCR4; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) + { + assert(config != NULL); + assert((config->frameSyncWidth - 1U) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT)); + + rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + rcr4 &= ~I2S_RCR4_ONDEM_MASK; + rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + rcr4 |= I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) | I2S_RCR4_FSD(1U) | + I2S_RCR4_SYWD(config->frameSyncWidth - 1U); + } + else + { + rcr4 &= ~I2S_RCR4_FSD_MASK; + } + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter Serial data configurations. + * + * param base SAI base pointer. + * param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t tcr4 = base->TCR4; + + base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1U) | I2S_TCR5_W0W(config->dataWord0Length - 1U) | + I2S_TCR5_FBT(config->dataFirstBitShifted - 1U); + base->TMR = config->dataMaskedWord; + + tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK); + tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1U) | I2S_TCR4_MF(config->dataOrder); + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + tcr4 &= ~I2S_TCR4_CHMOD_MASK; + tcr4 |= I2S_TCR4_CHMOD(config->dataMode); +#endif + + base->TCR4 = tcr4; +} + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t rcr4 = base->RCR4; + + base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1U) | I2S_RCR5_W0W(config->dataWord0Length - 1U) | + I2S_RCR5_FBT(config->dataFirstBitShifted - 1U); + base->RMR = config->dataMaskedWord; + + rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK); + rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1u) | I2S_RCR4_MF(config->dataOrder); + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + rcr4 &= ~I2S_RCR4_CHMOD_MASK; + rcr4 |= I2S_RCR4_CHMOD(config->dataMode); +#endif + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + + uint32_t val = 0U, i = 0U; + uint32_t channelNums = 0U; + /* reset transmitter */ + SAI_TxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & config->channelMask) + { + /* get start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + config->startChannel = i; + } + channelNums++; + config->endChannel = i; + } + } + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(config->channelMask); + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + + /* bit clock configurations */ + SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_TxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); + /* fifo configurations */ + SAI_TxSetFifoConfig(base, &config->fifo); +} + +/*! + * brief SAI transmitter transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* transmitter configurations */ + SAI_TxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief SAI receiver configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + + uint32_t val = 0U, i = 0U; + uint32_t channelNums = 0U; + + /* reset receiver */ + SAI_RxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & config->channelMask) + { + /* get start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + config->startChannel = i; + } + channelNums++; + config->endChannel = i; + } + } + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(config->channelMask); + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + + /* bit clock configurations */ + SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_RxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); + /* fifo configurations */ + SAI_RxSetFifoConfig(base, &config->fifo); +} + +/*! + * brief SAI receiver transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* receiver configurations */ + SAI_RxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief Get classic I2S mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); +} + +/*! + * brief Get left justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get right justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get DSP mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + default: + assert(false); + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get TDM mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + assert(dataWordNum <= 32U); + + SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + case kSAI_FrameSyncLenPerWordWidth: + break; + default: + assert(false); + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; + config->serialData.dataWordNum = dataWordNum; +} + /*! * brief Configures the SAI Tx audio format. * + * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig + * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. * @@ -885,21 +1731,21 @@ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) * param mclkSourceClockHz SAI master clock source frequency in Hz. * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master * clock, this value should equal the masterClockHz. -*/ + */ void SAI_TxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz) { - uint32_t bclk = 0; - uint32_t val = 0; - uint32_t i = 0U; + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t i = 0U; uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); + val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); val |= I2S_TCR4_SYWD(format->bitWidth - 1U); base->TCR4 = val; } @@ -976,7 +1822,7 @@ void SAI_TxSetFormat(I2S_Type *base, } /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) { if (((uint32_t)1 << i) & format->channelMask) { @@ -990,7 +1836,7 @@ void SAI_TxSetFormat(I2S_Type *base, } } format->channelNums = channelNums; - assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) /* make sure combine mode disabled while multipe channel is used */ @@ -1013,6 +1859,8 @@ void SAI_TxSetFormat(I2S_Type *base, /*! * brief Configures the SAI Rx audio format. * + * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig + * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. * @@ -1021,21 +1869,21 @@ void SAI_TxSetFormat(I2S_Type *base, * param mclkSourceClockHz SAI master clock source frequency in Hz. * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master * clock, this value should equal the masterClockHz. -*/ + */ void SAI_RxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz) { - uint32_t bclk = 0; - uint32_t val = 0; - uint32_t i = 0U; + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t i = 0U; uint32_t divider = 0U, channelNums = 0U; if (format->isFrameSyncCompact) { bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); - val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); + val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); val |= I2S_RCR4_SYWD(format->bitWidth - 1U); base->RCR4 = val; } @@ -1111,7 +1959,7 @@ void SAI_RxSetFormat(I2S_Type *base, } /* if channel nums is not set, calculate it here according to channelMask*/ - for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNT; i++) + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) { if (((uint32_t)1 << i) & format->channelMask) { @@ -1125,7 +1973,7 @@ void SAI_RxSetFormat(I2S_Type *base, } } format->channelNums = channelNums; - assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) /* make sure combine mode disabled while multipe channel is used */ @@ -1159,7 +2007,7 @@ void SAI_RxSetFormat(I2S_Type *base, */ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { - uint32_t i = 0; + uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); @@ -1206,7 +2054,7 @@ void SAI_WriteMultiChannelBlocking( bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); #endif - for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) { if ((1U << i) & (channelMask)) { @@ -1215,7 +2063,7 @@ void SAI_WriteMultiChannelBlocking( } } - assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); bytesPerWord *= channelNums; while (j < size) @@ -1257,7 +2105,7 @@ void SAI_ReadMultiChannelBlocking( #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); #endif - for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNT); i++) + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) { if ((1U << i) & (channelMask)) { @@ -1266,7 +2114,7 @@ void SAI_ReadMultiChannelBlocking( } } - assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNT); + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); bytesPerWord *= channelNums; while (j < size) @@ -1295,7 +2143,7 @@ void SAI_ReadMultiChannelBlocking( */ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) { - uint32_t i = 0; + uint32_t i = 0; uint8_t bytesPerWord = bitWidth / 8U; #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); @@ -1336,7 +2184,7 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; - handle->base = base; + handle->base = base; /* Set the isr pointer */ s_saiTxIsr = SAI_TransferTxHandleIRQ; @@ -1367,7 +2215,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; - handle->base = base; + handle->base = base; /* Set the isr pointer */ s_saiRxIsr = SAI_TransferRxHandleIRQ; @@ -1379,6 +2227,8 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf /*! * brief Configures the SAI Tx audio format. * + * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetTransferConfig + * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. * @@ -1389,7 +2239,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master * clock, this value should equal the masterClockHz in format. * return Status of this function. Return value is the status_t. -*/ + */ status_t SAI_TransferTxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -1402,7 +2252,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) || (mclkSourceClockHz < format->sampleRate_Hz) #endif - ) + ) { return kStatus_InvalidArgument; } @@ -1419,7 +2269,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, /* used for multi channel */ handle->channelMask = format->channelMask; handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; + handle->endChannel = format->endChannel; return kStatus_Success; } @@ -1427,6 +2277,8 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, /*! * brief Configures the SAI Rx audio format. * + * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetTransferConfig + * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. * @@ -1437,7 +2289,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master * clock, this value should equal the masterClockHz in format. * return Status of this function. Return value is one of status_t. -*/ + */ status_t SAI_TransferRxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -1450,7 +2302,7 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) || (mclkSourceClockHz < format->sampleRate_Hz) #endif - ) + ) { return kStatus_InvalidArgument; } @@ -1467,7 +2319,7 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base, /* used for multi channel */ handle->channelMask = format->channelMask; handle->channelNums = format->channelNums; - handle->endChannel = format->endChannel; + handle->endChannel = format->endChannel; return kStatus_Success; } @@ -1498,10 +2350,10 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t } /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; /* Set the state to busy */ handle->state = kSAI_Busy; @@ -1546,10 +2398,10 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa } /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; /* Set state to busy */ handle->state = kSAI_Busy; @@ -1649,7 +2501,7 @@ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) /* Clear the queue */ memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -1679,7 +2531,7 @@ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) /* Clear the queue */ memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -1701,7 +2553,7 @@ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) /* Clear all the internal information */ memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; } @@ -1724,7 +2576,7 @@ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) /* Clear all the internal information */ memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; } @@ -1738,7 +2590,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ @@ -1787,7 +2639,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) } #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if (handle->saiQueue[handle->queueDriver].dataSize == 0U) { memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); @@ -1815,7 +2667,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) { assert(handle); - uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; /* Handle Error */ @@ -1863,7 +2715,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) } #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if (handle->saiQueue[handle->queueDriver].dataSize == 0U) { memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); @@ -2146,7 +2998,8 @@ void I2S4_Rx_DriverIRQHandler(void) } #endif -#if defined(FSL_FEATURE_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && defined(I2S6) +#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \ + defined(I2S6) void I2S56_DriverIRQHandler(void) { /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h index c6d33c746e05f..dc86ce5e55713 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai.h @@ -12,7 +12,7 @@ #include "fsl_common.h" /*! - * @addtogroup sai + * @addtogroup sai_driver * @{ */ @@ -22,19 +22,19 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0 */ /*@}*/ /*! @brief SAI return status*/ enum _sai_status_t { - kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ - kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ - kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ - kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ - kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ - kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ }; /*< sai channel mask value, actual channel numbers is depend soc specific */ @@ -63,8 +63,10 @@ typedef enum _sai_protocol /*! @brief Master or slave mode */ typedef enum _sai_master_slave { - kSAI_Master = 0x0U, /*!< Master mode */ - kSAI_Slave = 0x1U /*!< Slave mode */ + kSAI_Master = 0x0U, /*!< Master mode include bclk and frame sync */ + kSAI_Slave = 0x1U, /*!< Slave mode include bclk and frame sync */ + kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */ + kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */ } sai_master_slave_t; /*! @brief Mono or stereo audio format */ @@ -85,17 +87,21 @@ typedef enum _sai_data_order /*! @brief SAI clock polarity, active high or low */ typedef enum _sai_clock_polarity { - kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */ - kSAI_PolarityActiveLow /*!< Clock active low */ + kSAI_PolarityActiveHigh = 0x0U, /*!< Drive outputs on rising edge */ + kSAI_PolarityActiveLow, /*!< Drive outputs on falling edge */ + kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */ + kSAI_SampleOnRisingEdge /*!< Sample inputs on rising edge */ } sai_clock_polarity_t; /*! @brief Synchronous or asynchronous mode */ typedef enum _sai_sync_mode { - kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ - kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ } sai_sync_mode_t; #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) @@ -118,7 +124,7 @@ typedef enum _sai_bclk_source kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ /* Kinetis device bit clock source definition */ - kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ } sai_bclk_source_t; @@ -128,9 +134,9 @@ enum _sai_interrupt_enable_t { kSAI_WordStartInterruptEnable = I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ - kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ - kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ @@ -160,9 +166,9 @@ enum _sai_flags /*! @brief The reset type */ typedef enum _sai_reset_type { - kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ - kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ - kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ } sai_reset_type_t; #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING @@ -173,8 +179,8 @@ typedef enum _sai_reset_type typedef enum _sai_fifo_packing { kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ - kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ - kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ @@ -193,53 +199,93 @@ typedef struct _sai_config sai_master_slave_t masterSlave; /*!< Master or slave */ } sai_config_t; +#ifndef SAI_XFER_QUEUE_SIZE /*!@brief SAI transfer queue size, user can refine it according to use case. */ #define SAI_XFER_QUEUE_SIZE (4) +#endif /*! @brief Audio sample rate */ typedef enum _sai_sample_rate { - kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ - kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ - kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ - kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ - kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ - kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ - kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ - kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ - kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ - kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ - kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ - kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ } sai_sample_rate_t; /*! @brief Audio word width */ typedef enum _sai_word_width { - kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ } sai_word_width_t; +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE +/*! @brief sai data pin state definition */ +typedef enum _sai_data_pin_state +{ + kSAI_DataPinStateTriState = + 0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */ + kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots + are masked or channel disabled */ +} sai_data_pin_state_t; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE +/*! @brief sai fifo combine mode definition */ +typedef enum _sai_fifo_combine +{ + kSAI_FifoCombineDisabled = 0U, /*!< sai fifo combine mode disabled */ + kSAI_FifoCombineModeEnabledOnRead, /*!< sai fifo combine mode enabled on FIFO reads */ + kSAI_FifoCombineModeEnabledOnWrite, /*!< sai fifo combine mode enabled on FIFO write */ + kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */ +} sai_fifo_combine_t; +#endif + +/*! @brief sai transceiver type */ +typedef enum _sai_transceiver_type +{ + kSAI_Transmitter = 0U, /*!< sai transmitter */ + kSAI_Receiver = 1U, /*!< sai receiver */ +} sai_transceiver_type_t; + +/*! @brief sai frame sync len */ +typedef enum _sai_frame_sync_len +{ + kSAI_FrameSyncLenOneBitClk = 0U, /*!< 1 bit clock frame sync len for DSP mode */ + kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */ +} sai_frame_sync_len_t; + /*! @brief sai transfer format */ typedef struct _sai_transfer_format { uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ sai_mono_stereo_t stereo; /*!< Mono or stereo */ - uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) uint8_t watermark; /*!< Watermark value */ #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle - * other parameter carefully, such as - * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask - * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. - * for the single channel usage, user can provide channel or channel mask only, such as, - * channel = 0 or channelMask = kSAI_Channel0Mask. - */ + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ uint8_t channel; /*!< Transfer start channel */ uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ uint8_t endChannel; /*!< end channel number */ @@ -250,6 +296,106 @@ typedef struct _sai_transfer_format sync length is 64 times of bit clock. */ } sai_transfer_format_t; +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! @brief master clock configurations */ +typedef struct _sai_master_clock +{ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< master clock output enable */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif +#endif + +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + uint32_t mclkHz; /*!< target mclk frequency */ + uint32_t mclkSourceClkHz; /*!< mclk source frequency*/ +#endif +} sai_master_clock_t; +#endif + +/*! @brief sai fifo configurations */ +typedef struct _sai_fifo +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + bool fifoContinueOneError; /*!< fifo continues when error occur */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */ +#endif +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t fifoWatermark; /*!< fifo watermark */ +#endif +} sai_fifo_t; + +/*! @brief sai bit clock configurations */ +typedef struct _sai_bit_clock +{ + bool bclkSrcSwap; /*!< bit clock source swap */ + bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay, + this has effect of decreasing the data input setup time, but increasing the data output valid + time .*/ + sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */ + sai_bclk_source_t bclkSource; /*!< bit Clock source */ +} sai_bit_clock_t; + +/*! @brief sai frame sync configurations */ +typedef struct _sai_frame_sync +{ + uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */ + bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame + FALSE is frame sync assert with the first bit of the frame */ + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */ +#endif + + sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */ + +} sai_frame_sync_t; + +/*! @brief sai serial data configurations */ +typedef struct _sai_serial_data +{ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */ +#endif + + sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */ + uint8_t dataWord0Length; /*!< configure the number of bits in the first word in each frame */ + uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */ + uint8_t dataWordLength; /*!< used to record the data length for dma transfer */ + uint8_t + dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */ + uint8_t dataWordNum; /*!< configure the number of words in each frame */ + uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */ +} sai_serial_data_t; + +/*! @brief sai transceiver configurations */ +typedef struct _sai_transceiver +{ + sai_serial_data_t serialData; /*!< serial data configurations */ + sai_frame_sync_t frameSync; /*!< ws configurations */ + sai_bit_clock_t bitClock; /*!< bit clock configurations */ + sai_fifo_t fifo; /*!< fifo configurations */ + + sai_master_slave_t masterSlave; /*!< transceiver is master or slave */ + + sai_sync_mode_t syncMode; /*!< transceiver sync mode */ + + uint8_t startChannel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + +} sai_transceiver_t; + /*! @brief SAI transfer structure */ typedef struct _sai_transfer { @@ -273,12 +419,12 @@ struct _sai_handle uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle - * other parameter carefully, such as - * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask - * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. - * for the single channel usage, user can provide channel or channel mask only, such as, - * channel = 0 or channelMask = kSAI_Channel0Mask. - */ + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ uint8_t channel; /*!< Transfer start channel */ uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ uint8_t endChannel; /*!< end channel number */ @@ -308,6 +454,7 @@ extern "C" { /*! * @brief Initializes the SAI Tx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init * * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. * The configuration structure can be custom filled or set with default values by @@ -319,11 +466,12 @@ extern "C" { * * @param base SAI base pointer * @param config SAI configuration structure. -*/ + */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); /*! * @brief Initializes the SAI Rx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init * * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. * The configuration structure can be custom filled or set with default values by @@ -340,6 +488,8 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); /*! * @brief Sets the SAI Tx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig * * This API initializes the configuration structure for use in SAI_TxConfig(). * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified @@ -356,6 +506,8 @@ void SAI_TxGetDefaultConfig(sai_config_t *config); /*! * @brief Sets the SAI Rx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig * * This API initializes the configuration structure for use in SAI_RxConfig(). * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified @@ -370,14 +522,23 @@ void SAI_TxGetDefaultConfig(sai_config_t *config); */ void SAI_RxGetDefaultConfig(sai_config_t *config); +/*! + * @brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Init(I2S_Type *base); + /*! * @brief De-initializes the SAI peripheral. * * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit * or SAI_RxInit is called to enable the clock. * - * @param base SAI base pointer -*/ + * @param base SAI base pointer. + */ void SAI_Deinit(I2S_Type *base); /*! @@ -401,7 +562,7 @@ void SAI_RxReset(I2S_Type *base); /*! * @brief Enables/disables the SAI Tx. * - * @param base SAI base pointer + * @param base SAI base pointer. * @param enable True means enable SAI Tx, false means disable. */ void SAI_TxEnable(I2S_Type *base, bool enable); @@ -409,11 +570,278 @@ void SAI_TxEnable(I2S_Type *base, bool enable); /*! * @brief Enables/disables the SAI Rx. * - * @param base SAI base pointer + * @param base SAI base pointer. * @param enable True means enable SAI Rx, false means disable. */ void SAI_RxEnable(I2S_Type *base, bool enable); +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR4 |= I2S_RCR4_FSD_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } +} + +/*! + * @brief Set Tx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR4 |= I2S_TCR4_FSD_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } +} + +/*! + * @brief Transmitter bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz, bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth, audio data bitWidth. + * @param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz, bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth, audio data bitWidth. + * @param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Transmitter Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +/*! + * @brief Receiver Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * @brief Master clock configurations. + * + * @param base SAI base pointer. + * @param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config); +#endif + +/*! + * @brief SAI transmitter fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI receiver fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI transmitter Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI receiver Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI transmitter Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI transmitter configurations. + * + * @param base SAI base pointer. + * @param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief SAI receiver configurations. + * + * @param base SAI base pointer. + * @param config receiver configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get left justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get right justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get TDM mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data word width. + * @param dataWordNum word number in one frame. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask); + +/*! + * @brief Get DSP mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); /*! @} */ /*! @@ -475,7 +903,7 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) * @brief Do software reset or FIFO reset . * * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software * reset will not clear any configuration registers like TCR1~TCR5. * This function will also clear all the error flags such as FIFO error, sync error etc. * @@ -488,7 +916,7 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); * @brief Do software reset or FIFO reset . * * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. - * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software * reset will not clear any configuration registers like RCR1~RCR5. * This function will also clear all the error flags such as FIFO error, sync error etc. * @@ -573,24 +1001,24 @@ void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); /*! -* @brief Set Rx FIFO packing feature. -* -* @param base SAI base pointer. -* @param pack FIFO pack type. It is element of sai_fifo_packing_t. -*/ + * @brief Set Rx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ #if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR /*! -* @brief Set Tx FIFO error continue. -* -* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature -* not enabled, SAI will hang and users need to clear FEF flag in TCSR register. -* -* @param base SAI base pointer. -* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. -*/ + * @brief Set Tx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in TCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) { if (isEnabled) @@ -604,14 +1032,14 @@ static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) } /*! -* @brief Set Rx FIFO error continue. -* -* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature -* not enabled, SAI will hang and users need to clear FEF flag in RCSR register. -* -* @param base SAI base pointer. -* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. -*/ + * @brief Set Rx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in RCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) { if (isEnabled) @@ -624,6 +1052,7 @@ static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) } } #endif + /*! @} */ /*! @@ -785,6 +1214,7 @@ static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t cha /*! * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. @@ -794,7 +1224,7 @@ static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t cha * @param mclkSourceClockHz SAI master clock source frequency in Hz. * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master * clock, this value should equal the masterClockHz. -*/ + */ void SAI_TxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -802,6 +1232,7 @@ void SAI_TxSetFormat(I2S_Type *base, /*! * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. @@ -811,7 +1242,7 @@ void SAI_TxSetFormat(I2S_Type *base, * @param mclkSourceClockHz SAI master clock source frequency in Hz. * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master * clock, this value should equal the masterClockHz. -*/ + */ void SAI_RxSetFormat(I2S_Type *base, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, @@ -930,8 +1361,33 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf */ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); +/*! + * @brief SAI transmitter transfer configurations. + * + * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief SAI receiver transfer configurations. + * + * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config receiver configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + /*! * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetTransferConfig * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. @@ -943,7 +1399,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master * clock, this value should equal the masterClockHz in format. * @return Status of this function. Return value is the status_t. -*/ + */ status_t SAI_TransferTxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, @@ -952,6 +1408,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, /*! * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetTransferConfig * * The audio format can be changed at run-time. This function configures the sample rate and audio data * format to be transferred. @@ -963,7 +1420,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base, * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master * clock, this value should equal the masterClockHz in format. * @return Status of this function. Return value is one of status_t. -*/ + */ status_t SAI_TransferRxSetFormat(I2S_Type *base, sai_handle_t *handle, sai_transfer_format_t *format, diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c index 116d088d9f20d..6fb16e06f20a3 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c @@ -68,8 +68,8 @@ static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds); /******************************************************************************* -* Code -******************************************************************************/ + * Code + ******************************************************************************/ static uint32_t SAI_GetInstance(I2S_Type *base) { uint32_t instance; @@ -91,9 +91,9 @@ static uint32_t SAI_GetInstance(I2S_Type *base) static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; - sai_edma_handle_t *saiHandle = privHandle->handle; + sai_edma_handle_t *saiHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; if (saiHandle->callback) @@ -113,9 +113,9 @@ static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; - sai_edma_handle_t *saiHandle = privHandle->handle; + sai_edma_handle_t *saiHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; if (saiHandle->callback) @@ -157,13 +157,13 @@ void SAI_TransferTxCreateHandleEDMA( /* Set sai base to handle */ handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; /* Set SAI state to idle */ handle->state = kSAI_Idle; - s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].base = base; s_edmaPrivateHandle[instance][0].handle = handle; /* Need to use scatter gather */ @@ -198,13 +198,13 @@ void SAI_TransferRxCreateHandleEDMA( /* Set sai base to handle */ handle->dmaHandle = dmaHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; /* Set SAI state to idle */ handle->state = kSAI_Idle; - s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].base = base; s_edmaPrivateHandle[instance][1].handle = handle; /* Need to use scatter gather */ @@ -228,7 +228,7 @@ void SAI_TransferRxCreateHandleEDMA( * clock, this value should equals to masterClockHz in format. * retval kStatus_Success Audio format set successfully. * retval kStatus_InvalidArgument The input argument is invalid. -*/ + */ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -240,7 +240,7 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, /* Configure the audio format to SAI registers */ SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - /* Get the tranfer size from format, this should be used in EDMA configuration */ + /* Get the transfer size from format, this should be used in EDMA configuration */ if (format->bitWidth == 24U) { handle->bytesPerFrame = 4U; @@ -253,7 +253,7 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, /* Update the data channel SAI used */ handle->channel = format->channel; - /* Clear the channel enable bits unitl do a send/receive */ + /* Clear the channel enable bits until do a send/receive */ base->TCR3 &= ~I2S_TCR3_TCE_MASK; #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; @@ -262,6 +262,42 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * @brief Configures the SAI Tx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert(handle && saiConfig); + + /* Configure the audio format to SAI registers */ + SAI_TxSetConfig(base, saiConfig); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + + /* Clear the channel enable bits until do a send/receive */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - saiConfig->fifo.fifoWatermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + /*! * brief Configures the SAI Rx audio format. * @@ -276,7 +312,7 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, * clock, this value should equal to masterClockHz in format. * retval kStatus_Success Audio format set successfully. * retval kStatus_InvalidArgument The input argument is invalid. -*/ + */ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -288,7 +324,7 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, /* Configure the audio format to SAI registers */ SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); - /* Get the tranfer size from format, this should be used in EDMA configuration */ + /* Get the transfer size from format, this should be used in EDMA configuration */ if (format->bitWidth == 24U) { handle->bytesPerFrame = 4U; @@ -301,7 +337,7 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, /* Update the data channel SAI used */ handle->channel = format->channel; - /* Clear the channel enable bits unitl do a send/receive */ + /* Clear the channel enable bits until do a send/receive */ base->RCR3 &= ~I2S_RCR3_RCE_MASK; #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) handle->count = format->watermark; @@ -310,6 +346,43 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, #endif /* FSL_FEATURE_SAI_FIFO_COUNT */ } +/*! + * @brief Configures the SAI Rx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert(handle && saiConfig); + + /* Configure the audio format to SAI registers */ + SAI_RxSetConfig(base, saiConfig); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + + /* Clear the channel enable bits until do a send/receive */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = saiConfig->fifo.fifoWatermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + /*! * brief Performs a non-blocking SAI transfer using DMA. * @@ -328,7 +401,7 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -345,10 +418,10 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra handle->state = kSAI_Busy; /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; /* Prepare edma configure */ EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, @@ -392,7 +465,7 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); /* Check if input parameter invalid */ if ((xfer->data == NULL) || (xfer->dataSize == 0U)) @@ -409,10 +482,10 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_ handle->state = kSAI_Busy; /* Update queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->saiQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; /* Prepare edma configure */ EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, @@ -532,7 +605,7 @@ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) memset(handle->tcd, 0U, sizeof(handle->tcd)); memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; } @@ -556,7 +629,7 @@ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) memset(handle->tcd, 0U, sizeof(handle->tcd)); memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h index b3d913948b556..71305fd448540 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h @@ -8,8 +8,8 @@ #ifndef _FSL_SAI_EDMA_H_ #define _FSL_SAI_EDMA_H_ -#include "fsl_sai.h" #include "fsl_edma.h" +#include "fsl_sai.h" /*! * @addtogroup sai_edma @@ -22,7 +22,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5 */ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0 */ /*@}*/ typedef struct _sai_edma_handle sai_edma_handle_t; @@ -106,7 +106,7 @@ void SAI_TransferRxCreateHandleEDMA( * clock, this value should equals to masterClockHz in format. * @retval kStatus_Success Audio format set successfully. * @retval kStatus_InvalidArgument The input argument is invalid. -*/ + */ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, @@ -127,13 +127,33 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base, * clock, this value should equal to masterClockHz in format. * @retval kStatus_Success Audio format set successfully. * @retval kStatus_InvalidArgument The input argument is invalid. -*/ + */ void SAI_TransferRxSetFormatEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_format_t *format, uint32_t mclkSourceClockHz, uint32_t bclkSourceClockHz); +/*! + * @brief Configures the SAI Tx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + +/*! + * @brief Configures the SAI Rx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + /*! * @brief Performs a non-blocking SAI transfer using DMA. * diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c index 77796e75ce9f4..7ff0be0d0d029 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c @@ -184,13 +184,13 @@ static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datet secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; datetime->minute = secondsRemaining / 60U; datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; + daysInYear = DAYS_IN_A_YEAR; datetime->year = YEAR_RANGE_START; while (days > daysInYear) { @@ -332,21 +332,21 @@ void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->rtcCalEnable = false; - config->rtcCalValue = 0U; + config->rtcCalEnable = false; + config->rtcCalValue = 0U; config->periodicInterruptFreq = 0U; } static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) { uint32_t seconds = 0; - uint32_t tmp = 0; + uint32_t tmp = 0; /* Do consecutive reads until value is correct */ do { seconds = tmp; - tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); + tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); } while (tmp != seconds); return seconds; @@ -366,7 +366,7 @@ status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t * assert(datetime); uint32_t seconds = 0U; - uint32_t tmp = base->HPCR; + uint32_t tmp = base->HPCR; /* disable RTC */ SNVS_HP_RTC_StopTimer(base); @@ -424,8 +424,8 @@ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *ala assert(alarmTime); uint32_t alarmSeconds = 0U; - uint32_t currSeconds = 0U; - uint32_t tmp = base->HPCR; + uint32_t currSeconds = 0U; + uint32_t tmp = base->HPCR; /* Return error if the alarm time provided is not valid */ if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) @@ -434,7 +434,7 @@ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *ala } alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); - currSeconds = SNVS_HP_RTC_GetSeconds(base); + currSeconds = SNVS_HP_RTC_GetSeconds(base); /* Return error if the alarm time has passed */ if (alarmSeconds < currSeconds) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h index 2f1cf36d47662..04d16a46d0a81 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h @@ -28,34 +28,34 @@ /*! @brief List of SNVS interrupts */ typedef enum _snvs_hp_interrupts { - kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ - kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ + kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ + kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ } snvs_hp_interrupts_t; /*! @brief List of SNVS flags */ typedef enum _snvs_hp_status_flags { - kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ - kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ - kSNVS_ZMK_ZeroFlag = (int)SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */ - kSNVS_OTPMK_ZeroFlag = SNVS_HPSR_OTPMK_ZERO_MASK, /*!< The OTPMK is zero */ + kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ + kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ + kSNVS_ZMK_ZeroFlag = (int)SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */ + kSNVS_OTPMK_ZeroFlag = SNVS_HPSR_OTPMK_ZERO_MASK, /*!< The OTPMK is zero */ } snvs_hp_status_flags_t; /*! @brief List of SNVS security violation flags */ typedef enum _snvs_hp_sv_status_flags { - kSNVS_LP_ViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< Low Power section Security Violation */ - kSNVS_ZMK_EccFailFlag = SNVS_HPSVSR_ZMK_ECC_FAIL_MASK, /*!< Zeroizable Master Key Error Correcting Code Check - Failure */ - kSNVS_LP_SoftwareViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< LP Software Security Violation */ - kSNVS_FatalSoftwareViolationFlag = SNVS_HPSVSR_SW_FSV_MASK, /*!< Software Fatal Security Violation */ - kSNVS_SoftwareViolationFlag = SNVS_HPSVSR_SW_SV_MASK, /*!< Software Security Violation */ - kSNVS_Violation0Flag = SNVS_HPSVSR_SV0_MASK, /*!< Security Violation 0 */ - kSNVS_Violation1Flag = SNVS_HPSVSR_SV1_MASK, /*!< Security Violation 1 */ - kSNVS_Violation2Flag = SNVS_HPSVSR_SV2_MASK, /*!< Security Violation 2 */ - kSNVS_Violation3Flag = SNVS_HPSVSR_SV3_MASK, /*!< Security Violation 3 */ - kSNVS_Violation4Flag = SNVS_HPSVSR_SV4_MASK, /*!< Security Violation 4 */ - kSNVS_Violation5Flag = SNVS_HPSVSR_SV5_MASK, /*!< Security Violation 5 */ + kSNVS_LP_ViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< Low Power section Security Violation */ + kSNVS_ZMK_EccFailFlag = SNVS_HPSVSR_ZMK_ECC_FAIL_MASK, /*!< Zeroizable Master Key Error Correcting Code Check + Failure */ + kSNVS_LP_SoftwareViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< LP Software Security Violation */ + kSNVS_FatalSoftwareViolationFlag = SNVS_HPSVSR_SW_FSV_MASK, /*!< Software Fatal Security Violation */ + kSNVS_SoftwareViolationFlag = SNVS_HPSVSR_SW_SV_MASK, /*!< Software Security Violation */ + kSNVS_Violation0Flag = SNVS_HPSVSR_SV0_MASK, /*!< Security Violation 0 */ + kSNVS_Violation1Flag = SNVS_HPSVSR_SV1_MASK, /*!< Security Violation 1 */ + kSNVS_Violation2Flag = SNVS_HPSVSR_SV2_MASK, /*!< Security Violation 2 */ + kSNVS_Violation3Flag = SNVS_HPSVSR_SV3_MASK, /*!< Security Violation 3 */ + kSNVS_Violation4Flag = SNVS_HPSVSR_SV4_MASK, /*!< Security Violation 4 */ + kSNVS_Violation5Flag = SNVS_HPSVSR_SV5_MASK, /*!< Security Violation 5 */ } snvs_hp_sv_status_flags_t; /*! @@ -98,14 +98,14 @@ typedef struct _snvs_hp_rtc_config typedef enum _snvs_hp_ssm_state { - kSNVS_SSMInit = 0x00, /*!< Init */ - kSNVS_SSMHardFail = 0x01, /*!< Hard Fail */ - kSNVS_SSMSoftFail = 0x03, /*!< Soft Fail */ + kSNVS_SSMInit = 0x00, /*!< Init */ + kSNVS_SSMHardFail = 0x01, /*!< Hard Fail */ + kSNVS_SSMSoftFail = 0x03, /*!< Soft Fail */ kSNVS_SSMInitInter = 0x08, /*!< Init Intermediate (transition state between Init and Check) */ - kSNVS_SSMCheck = 0x09, /*!< Check */ + kSNVS_SSMCheck = 0x09, /*!< Check */ kSNVS_SSMNonSecure = 0x0B, /*!< Non-Secure */ - kSNVS_SSMTrusted = 0x0D, /*!< Trusted */ - kSNVS_SSMSecure = 0x0F, /*!< Secure */ + kSNVS_SSMTrusted = 0x0D, /*!< Trusted */ + kSNVS_SSMSecure = 0x0F, /*!< Secure */ } snvs_hp_ssm_state_t; /******************************************************************************* diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c index 2fb8b71c88d81..c1e324c26123d 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c @@ -176,13 +176,13 @@ static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_date secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; datetime->minute = secondsRemaining / 60U; datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; /* Calculate year */ - daysInYear = DAYS_IN_A_YEAR; + daysInYear = DAYS_IN_A_YEAR; datetime->year = YEAR_RANGE_START; while (days > daysInYear) { @@ -249,7 +249,7 @@ void SNVS_LP_Init(SNVS_Type *base) /* Power glitch detector: set the PGD value and clear the previous status. */ base->LPPGDR = SNVS_DEFAULT_PGD_VALUE; - base->LPSR = SNVS_LPSR_PGD_MASK; + base->LPSR = SNVS_LPSR_PGD_MASK; } /*! @@ -333,19 +333,19 @@ void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config) memset(config, 0, sizeof(*config)); config->srtcCalEnable = false; - config->srtcCalValue = 0U; + config->srtcCalValue = 0U; } static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base) { uint32_t seconds = 0; - uint32_t tmp = 0; + uint32_t tmp = 0; /* Do consecutive reads until value is correct */ do { seconds = tmp; - tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U); + tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U); } while (tmp != seconds); return seconds; @@ -365,7 +365,7 @@ status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t assert(datetime); uint32_t seconds = 0U; - uint32_t tmp = base->LPCR; + uint32_t tmp = base->LPCR; /* disable RTC */ SNVS_LP_SRTC_StopTimer(base); @@ -427,8 +427,8 @@ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *a assert(alarmTime); uint32_t alarmSeconds = 0U; - uint32_t currSeconds = 0U; - uint32_t tmp = base->LPCR; + uint32_t currSeconds = 0U; + uint32_t tmp = base->LPCR; /* Return error if the alarm time provided is not valid */ if (!(SNVS_LP_CheckDatetimeFormat(alarmTime))) @@ -437,7 +437,7 @@ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *a } alarmSeconds = SNVS_LP_ConvertDatetimeToSeconds(alarmTime); - currSeconds = SNVS_LP_SRTC_GetSeconds(base); + currSeconds = SNVS_LP_SRTC_GetSeconds(base); /* Return error if the alarm time has passed */ if (alarmSeconds <= currSeconds) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h index bbf2ede992045..db01b35d9a413 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2017, NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,14 +44,14 @@ typedef enum _snvs_lp_external_tamper { kSNVS_ExternalTamper1 = 1U, #if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) - kSNVS_ExternalTamper2 = 2U, - kSNVS_ExternalTamper3 = 3U, - kSNVS_ExternalTamper4 = 4U, - kSNVS_ExternalTamper5 = 5U, - kSNVS_ExternalTamper6 = 6U, - kSNVS_ExternalTamper7 = 7U, - kSNVS_ExternalTamper8 = 8U, - kSNVS_ExternalTamper9 = 9U, + kSNVS_ExternalTamper2 = 2U, + kSNVS_ExternalTamper3 = 3U, + kSNVS_ExternalTamper4 = 4U, + kSNVS_ExternalTamper5 = 5U, + kSNVS_ExternalTamper6 = 6U, + kSNVS_ExternalTamper7 = 7U, + kSNVS_ExternalTamper8 = 8U, + kSNVS_ExternalTamper9 = 9U, kSNVS_ExternalTamper10 = 10U #endif } snvs_lp_external_tamper_t; @@ -67,13 +67,13 @@ typedef enum _snvs_lp_external_tamper typedef enum _snvs_lp_external_tamper_status { kSNVS_TamperNotDetected = 0U, - kSNVS_TamperDetected = 1U + kSNVS_TamperDetected = 1U } snvs_lp_external_tamper_status_t; /*! @brief SNVS_LP external tamper polarity */ typedef enum _snvs_lp_external_tamper_polarity { - kSNVS_ExternalTamperActiveLow = 0U, + kSNVS_ExternalTamperActiveLow = 0U, kSNVS_ExternalTamperActiveHigh = 1U } snvs_lp_external_tamper_polarity_t; @@ -120,8 +120,8 @@ typedef enum _snvs_lp_zmk_program_mode typedef enum _snvs_lp_master_key_mode { kSNVS_OTPMK = 0, /*!< One Time Programmable Master Key. */ - kSNVS_ZMK = 2, /*!< Zeroizable Master Key. */ - kSNVS_CMK = 3, /*!< Combined Master Key, it is XOR of OPTMK and ZMK. */ + kSNVS_ZMK = 2, /*!< Zeroizable Master Key. */ + kSNVS_CMK = 3, /*!< Combined Master Key, it is XOR of OPTMK and ZMK. */ } snvs_lp_master_key_mode_t; /******************************************************************************* @@ -527,13 +527,12 @@ static inline void SNVS_LP_EnableZeroizableMasterKeyECC(SNVS_Type *base, bool en static inline void SNVS_LP_SetMasterKeyMode(SNVS_Type *base, snvs_lp_master_key_mode_t mode) { uint32_t lpmkcr = base->LPMKCR; - lpmkcr = (lpmkcr & (~SNVS_LPMKCR_MASTER_KEY_SEL_MASK)) | SNVS_LPMKCR_MASTER_KEY_SEL(mode); - base->LPMKCR = lpmkcr; + lpmkcr = (lpmkcr & (~SNVS_LPMKCR_MASTER_KEY_SEL_MASK)) | SNVS_LPMKCR_MASTER_KEY_SEL(mode); + base->LPMKCR = lpmkcr; } /*! @}*/ - #if defined(__cplusplus) } #endif diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c index 6b73432e74b4a..0909d6b73a282 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c @@ -20,7 +20,7 @@ enum _spdif_transfer_state { kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ kSPDIF_Idle, /*!< Transfer is done. */ - kSPDIF_Error /*!< Transfer error occured. */ + kSPDIF_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for spdif tx interrupt handler. */ @@ -54,7 +54,7 @@ static spdif_isr_t s_spdifTxIsr; /*! @brief Pointer to IRQ handler for each instance. */ static spdif_isr_t s_spdifRxIsr; /*! @brief Used for spdif gain */ -static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U}; +static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U}; static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4}; static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16}; @@ -92,7 +92,7 @@ uint32_t SPDIF_GetInstance(SPDIF_Type *base) * * param base SPDIF base pointer * param config SPDIF configuration structure. -*/ + */ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) { uint32_t val = 0; @@ -131,7 +131,7 @@ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. * * param base SPDIF base pointer -*/ + */ void SPDIF_Deinit(SPDIF_Type *base) { SPDIF_TxEnable(base, false); @@ -160,16 +160,16 @@ void SPDIF_GetDefaultConfig(spdif_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->isTxAutoSync = true; - config->isRxAutoSync = true; - config->DPLLClkSource = 1; - config->txClkSource = 1; - config->rxFullSelect = kSPDIF_RxFull8Samples; - config->txFullSelect = kSPDIF_TxEmpty8Samples; - config->uChannelSrc = kSPDIF_UChannelFromTx; - config->txSource = kSPDIF_txNormal; + config->isTxAutoSync = true; + config->isRxAutoSync = true; + config->DPLLClkSource = 1; + config->txClkSource = 1; + config->rxFullSelect = kSPDIF_RxFull8Samples; + config->txFullSelect = kSPDIF_TxEmpty8Samples; + config->uChannelSrc = kSPDIF_UChannelFromTx; + config->txSource = kSPDIF_txNormal; config->validityConfig = kSPDIF_validityFlagAlwaysClear; - config->gain = kSPDIF_GAIN_8; + config->gain = kSPDIF_GAIN_8; } /*! @@ -207,12 +207,12 @@ void SPDIF_TxEnable(SPDIF_Type *base, bool enable) * param base SPDIF base pointer. * param sampleRate_Hz SPDIF sample rate frequency in Hz. * param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. -*/ + */ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz) { - uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); - uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64); - uint32_t val = 0; + uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); + uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64); + uint32_t val = 0; uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT); /* Compute the nearest divider */ @@ -257,7 +257,7 @@ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t so */ uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) { - uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; + uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; uint32_t measure = 0, sampleRate = 0; uint64_t temp = 0; @@ -268,7 +268,7 @@ uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) /* Get the measure value */ measure = base->SRFM; - temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz; + temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz; temp /= (uint64_t)(1024 * 1024 * 128 * gain); sampleRate = (uint32_t)temp; @@ -458,10 +458,10 @@ status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, } /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; /* Set the state to busy */ handle->state = kSPDIF_Busy; @@ -501,12 +501,12 @@ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *hand } /* Add into queue */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; - handle->spdifQueue[handle->queueUser].udata = xfer->udata; - handle->spdifQueue[handle->queueUser].qdata = xfer->qdata; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + handle->spdifQueue[handle->queueUser].udata = xfer->udata; + handle->spdifQueue[handle->queueUser].qdata = xfer->qdata; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; /* Set state to busy */ handle->state = kSPDIF_Busy; @@ -596,7 +596,7 @@ void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) /* Clear the queue */ memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -621,7 +621,7 @@ void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) /* Clear the queue */ memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); handle->queueDriver = 0; - handle->queueUser = 0; + handle->queueUser = 0; } /*! @@ -634,7 +634,7 @@ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); - uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data; + uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data; uint8_t dataSize = 0; uint32_t i = 0, j = 0, data = 0; @@ -667,7 +667,7 @@ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) { memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); @@ -696,7 +696,7 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) { assert(handle); - uint8_t *buffer = NULL; + uint8_t *buffer = NULL; uint8_t dataSize = 0; uint32_t i = 0, j = 0, data = 0; @@ -745,8 +745,8 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) && (base->SIE & kSPDIF_QChannelReceiveRegisterFull)) { - buffer = handle->spdifQueue[handle->queueDriver].qdata; - data = SPDIF_ReadQChannel(base); + buffer = handle->spdifQueue[handle->queueDriver].qdata; + data = SPDIF_ReadQChannel(base); buffer[0] = data & 0xFFU; buffer[1] = (data >> 8U) & 0xFFU; buffer[2] = (data >> 16U) & 0xFFU; @@ -756,8 +756,8 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) && (base->SIE & kSPDIF_UChannelReceiveRegisterFull)) { - buffer = handle->spdifQueue[handle->queueDriver].udata; - data = SPDIF_ReadUChannel(base); + buffer = handle->spdifQueue[handle->queueDriver].udata; + data = SPDIF_ReadUChannel(base); buffer[0] = data & 0xFFU; buffer[1] = (data >> 8U) & 0xFFU; buffer[2] = (data >> 16U) & 0xFFU; @@ -767,7 +767,7 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull)) { dataSize = handle->watermark; - buffer = handle->spdifQueue[handle->queueDriver].data; + buffer = handle->spdifQueue[handle->queueDriver].data; while (i < dataSize) { /* Read left channel data */ @@ -791,7 +791,7 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) { memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.h b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.h index 65369a0607477..242cc33aca442 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif.h @@ -28,23 +28,23 @@ /*! @brief SPDIF return status*/ enum _spdif_status_t { - kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */ - kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */ - kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */ - kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */ - kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */ - kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */ + kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */ + kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */ + kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */ + kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */ + kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */ + kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */ kStatus_SPDIF_RxParityBitError = MAKE_STATUS(kStatusGroup_SPDIF, 6), /*!< SPDIF Rx parity bit error. */ - kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */ - kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */ - kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */ + kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */ + kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */ + kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */ kStatus_SPDIF_UQChannelFrameError = MAKE_STATUS(kStatusGroup_SPDIF, 10), /*!< SPDIF U/Q channel frame error. */ - kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */ + kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */ kStatus_SPDIF_RxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 12), /*!< SPDIF Rx left and right FIFO resync. */ - kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */ - kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */ - kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */ - kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16) /*!< SPDIF queue full */ + kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */ + kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */ + kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */ + kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16) /*!< SPDIF queue full */ }; /*! @brief SPDIF Rx FIFO full falg select, it decides when assert the rx full flag */ @@ -68,7 +68,7 @@ typedef enum _spdif_txempty_select /*! @brief SPDIF U channel source */ typedef enum _spdif_uchannel_source { - kSPDIF_NoUChannel = 0x0U, /*!< No embedded U channel */ + kSPDIF_NoUChannel = 0x0U, /*!< No embedded U channel */ kSPDIF_UChannelFromRx = 0x1U, /*!< U channel from receiver, it is CD mode */ kSPDIF_UChannelFromTx = 0x3U, /*!< U channel from on chip tx */ } spdif_uchannel_source_t; @@ -89,7 +89,7 @@ typedef enum _spdif_gain_select typedef enum _spdif_tx_source { kSPDIF_txFromReceiver = 0x1U, /*!< Tx data directly through SPDIF receiver */ - kSPDIF_txNormal = 0x5U, /*!< Normal operation, data from processor */ + kSPDIF_txNormal = 0x5U, /*!< Normal operation, data from processor */ } spdif_tx_source_t; /*! @brief SPDIF tx data source */ @@ -102,24 +102,24 @@ typedef enum _spdif_validity_config /*! @brief The SPDIF interrupt enable flag */ enum _spdif_interrupt_enable_t { - kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK, /*!< SPDIF DPLL locked */ - kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK, /*!< Tx FIFO underrun or overrun */ - kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK, /*!< Tx FIFO left and right channel resync */ - kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK, /*!< SPDIF Rx control channel value changed */ - kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK, /*!< SPDIF validity flag no good */ - kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK, /*!< SPDIF receiver found illegal symbol */ - kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK, /*!< SPDIF receiver found parity bit error */ - kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK, /*!< SPDIF U channel revceive register full */ - kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */ - kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK, /*!< SPDIF Q channel receive reigster full */ - kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */ - kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK, /*!< SPDIF U/Q channel sync found */ - kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK, /*!< SPDIF U/Q channel frame error */ - kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK, /*!< SPDIF Rx FIFO underrun/overrun */ - kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */ - kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK, /*!< SPDIF receiver loss of lock */ - kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK, /*!< SPDIF Tx FIFO empty */ - kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK /*!< SPDIF Rx FIFO full */ + kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK, /*!< SPDIF DPLL locked */ + kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK, /*!< Tx FIFO underrun or overrun */ + kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK, /*!< Tx FIFO left and right channel resync */ + kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK, /*!< SPDIF Rx control channel value changed */ + kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK, /*!< SPDIF validity flag no good */ + kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK, /*!< SPDIF receiver found illegal symbol */ + kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK, /*!< SPDIF receiver found parity bit error */ + kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK, /*!< SPDIF U channel revceive register full */ + kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */ + kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK, /*!< SPDIF Q channel receive reigster full */ + kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */ + kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK, /*!< SPDIF U/Q channel sync found */ + kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK, /*!< SPDIF U/Q channel frame error */ + kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK, /*!< SPDIF Rx FIFO underrun/overrun */ + kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */ + kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK, /*!< SPDIF receiver loss of lock */ + kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK, /*!< SPDIF Tx FIFO empty */ + kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK /*!< SPDIF Rx FIFO full */ }; /*! @brief The DMA request sources */ @@ -200,7 +200,7 @@ extern "C" { * * @param base SPDIF base pointer * @param config SPDIF configuration structure. -*/ + */ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config); /*! @@ -225,7 +225,7 @@ void SPDIF_GetDefaultConfig(spdif_config_t *config); * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. * * @param base SPDIF base pointer -*/ + */ void SPDIF_Deinit(SPDIF_Type *base); /*! @@ -448,7 +448,7 @@ static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base) * @param base SPDIF base pointer. * @param sampleRate_Hz SPDIF sample rate frequency in Hz. * @param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. -*/ + */ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz); /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c index 363c46ff3c884..8504a25ec9b33 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c @@ -77,14 +77,14 @@ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool don static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds); /******************************************************************************* -* Code -******************************************************************************/ + * Code + ******************************************************************************/ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData; - spdif_edma_handle_t *spdifHandle = privHandle->handle; + spdif_edma_handle_t *spdifHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; if (spdifHandle->callback) @@ -102,9 +102,9 @@ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool don static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) { spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData; - spdif_edma_handle_t *spdifHandle = privHandle->handle; + spdif_edma_handle_t *spdifHandle = privHandle->handle; - /* If finished a blcok, call the callback function */ + /* If finished a block, call the callback function */ memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; if (spdifHandle->callback) @@ -163,10 +163,10 @@ static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_ if (currentTcd != previousTcd) { /* Enable scatter/gather feature in the previous TCD block. */ - csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; handle->tcdPool[previousTcd].CSR = csr; /* - Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + Check if the TCD block in the registers is the previous one (points to current TCD block). It is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to link the TCD register in case link the current TCD with the dead chain when TCD loading occurs before link the previous TCD block. @@ -258,17 +258,17 @@ void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, memset(handle, 0, sizeof(*handle)); /* Set spdif base to handle */ - handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaLeftHandle = dmaLeftHandle; handle->dmaRightHandle = dmaRightHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; handle->count = s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; /* Set SPDIF state to idle */ handle->state = kSPDIF_Idle; - s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].base = base; s_edmaPrivateHandle[instance][0].handle = handle; /* Need to use scatter gather */ @@ -308,16 +308,16 @@ void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, memset(handle, 0, sizeof(*handle)); /* Set spdif base to handle */ - handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaLeftHandle = dmaLeftHandle; handle->dmaRightHandle = dmaRightHandle; - handle->callback = callback; - handle->userData = userData; + handle->callback = callback; + handle->userData = userData; handle->count = s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; /* Set SPDIF state to idle */ handle->state = kSPDIF_Idle; - s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].base = base; s_edmaPrivateHandle[instance][1].handle = handle; /* Need to use scatter gather */ @@ -346,7 +346,7 @@ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, s assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base); + uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base); /* Check if input parameter invalid */ if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) @@ -363,11 +363,11 @@ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, s handle->state = kSPDIF_Busy; /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ handle->nbytes = handle->count * 8U; @@ -414,7 +414,7 @@ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle assert(handle && xfer); edma_transfer_config_t config = {0}; - uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base); + uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base); /* Check if input parameter invalid */ if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) @@ -431,11 +431,11 @@ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle handle->state = kSPDIF_Busy; /* Update the queue state */ - handle->transferSize[handle->queueUser] = xfer->dataSize; - handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; - handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; - handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ handle->nbytes = handle->count * 8U; @@ -485,7 +485,7 @@ void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) /* Set internal state */ memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; /* Set the handle state */ @@ -512,7 +512,7 @@ void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handl /* Set internal state */ memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); memset(handle->transferSize, 0U, sizeof(handle->transferSize)); - handle->queueUser = 0U; + handle->queueUser = 0U; handle->queueDriver = 0U; /* Set the handle state */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_src.h b/ext/hal/nxp/mcux/drivers/imx/fsl_src.h index cec5039b506bf..74aa005ce7055 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_src.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_src.h @@ -2,7 +2,7 @@ * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief SRC driver version 2.0.0. */ -#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief SRC driver version 2.0.1. */ +#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*@}*/ /*! @@ -36,14 +36,14 @@ enum _src_reset_status_flags driven out on PTE0 pin. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */ #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) - kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot - was initiated by software. */ -#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ - kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the - result of software reset from on-chip - Temperature Sensor. Temperature Sensor - Interrupt need be served before this - bit can be cleaned.*/ + kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot + was initiated by software. */ +#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ + kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the + result of software reset from on-chip + Temperature Sensor. Temperature Sensor + Interrupt need be served before this + bit can be cleaned.*/ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates whether the reset was the result of the @@ -55,6 +55,9 @@ enum _src_reset_status_flags Interrupt and Reset Control Register in the ARM core. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) + kSRC_JTAGSystemResetFlag = SRC_SRSR_JTAG_SW_RST_MASK, /*!< Indicates whether the reset was the result of software reset form JTAG */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST */ kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of setting SJC_GPCCR bit 31. */ kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG @@ -86,10 +89,11 @@ enum _src_reset_status_flags power-on detection logic. */ #endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) - kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software - setting of SYSRESETREQ bit in Application Interrupt and - Reset Control Register of the ARM core. */ -#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ + kSRC_LockupSysResetFlag = + SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software + setting of SYSRESETREQ bit in Application Interrupt and + Reset Control Register of the ARM core. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence). */ @@ -144,9 +148,9 @@ typedef enum _src_wdog3_reset_option typedef enum _src_warm_reset_bypass_count { kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */ - kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */ - kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */ - kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */ } src_warm_reset_bypass_count_t; #if defined(__cplusplus) diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c index 2f2b08dde32f9..c797534737f93 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c @@ -65,11 +65,11 @@ void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config) /* ready to read calibration data */ calibrationData = OCOTP->ANA1; - s_hotTemp = (uint32_t)(calibrationData & TEMPMON_HOTTEMPMASK) >> TEMPMON_HOTTEMPSHIFT; - s_hotCount = (uint32_t)(calibrationData & TEMPMON_HOTCOUNTMASK) >> TEMPMON_HOTCOUNTSHIFT; - roomCount = (uint32_t)(calibrationData & TEMPMON_ROOMCOUNTMASK) >> TEMPMON_ROOMCOUNTSHIFT; + s_hotTemp = (uint32_t)(calibrationData & TEMPMON_HOTTEMPMASK) >> TEMPMON_HOTTEMPSHIFT; + s_hotCount = (uint32_t)(calibrationData & TEMPMON_HOTCOUNTMASK) >> TEMPMON_HOTCOUNTSHIFT; + roomCount = (uint32_t)(calibrationData & TEMPMON_ROOMCOUNTMASK) >> TEMPMON_ROOMCOUNTSHIFT; - s_hotT_ROOM = s_hotTemp - TEMPMON_ROOMTEMP; + s_hotT_ROOM = s_hotTemp - TEMPMON_ROOMTEMP; s_roomC_hotC = roomCount - s_hotCount; /* Set alarm temperature */ diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.h b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.h index 729beb9df0f60..8e9d723815706 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.h @@ -38,9 +38,9 @@ typedef struct _tempmon_config /*! @brief TEMPMON alarm mode. */ typedef enum _tempmon_alarm_mode { - kTEMPMON_HighAlarmMode = 0U, /*!< The high alarm temperature interrupt mode.*/ + kTEMPMON_HighAlarmMode = 0U, /*!< The high alarm temperature interrupt mode.*/ kTEMPMON_PanicAlarmMode = 1U, /*!< The panic alarm temperature interrupt mode.*/ - kTEMPMON_LowAlarmMode = 2U, /*!< The low alarm temperature interrupt mode.*/ + kTEMPMON_LowAlarmMode = 2U, /*!< The low alarm temperature interrupt mode.*/ } tempmon_alarm_mode; /******************************************************************************* diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c index 5590a883c55e9..4a160b919b4d8 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.c @@ -22,8 +22,8 @@ #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES)) #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 -#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ - defined(KL82Z7_SERIES)) +#elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ + defined(KL82Z7_SERIES)) #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 #elif defined(K81F25615_SERIES) #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 @@ -60,8 +60,8 @@ /*! @brief TRNG work mode */ typedef enum _trng_work_mode { - kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ - kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ + kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ + kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ } trng_work_mode_t; /*! @brief TRNG statistical check type*/ @@ -1266,34 +1266,34 @@ status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) if (userConfig != NULL) { - userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK; - userConfig->clockMode = kTRNG_ClockModeRingOscillator; - userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; - userConfig->sampleMode = kTRNG_SampleModeRaw; - userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; - userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; + userConfig->lock = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK; + userConfig->clockMode = kTRNG_ClockModeRingOscillator; + userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; + userConfig->sampleMode = kTRNG_SampleModeRaw; + userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; + userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; /* Statistical Check Parameters.*/ - userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; + userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; - userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; - userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; - userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; - userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; - userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; - userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; - userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; - userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; - userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; - userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; - userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; - userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; - userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; - userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; - userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; - userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; + userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; + userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; + userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; + userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; + userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; + userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; + userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; + userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; + userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; + userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; + userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; + userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; + userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; + userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; + userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; + userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; @@ -1313,7 +1313,7 @@ status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) * This function sets the retry counter which defines the number of times a * statistical check may fails during the TRNG Entropy Generation before * generating an error. -*/ + */ static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) { status_t status; @@ -1344,123 +1344,132 @@ static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, uint32_t range; status_t status = kStatus_Success; - if (limit && (limit->maximum > limit->minimum)) + if ((NULL != limit) && (limit->maximum > limit->minimum)) { range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ - switch (statistical_check) + if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero + detected during entropy generation. */ + { + if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) + { + TRNG_WR_SCML_MONO_MAX(base, limit->maximum); + TRNG_WR_SCML_MONO_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of + length 1 detected during entropy generation. */ + { + if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) + { + TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); + TRNG_WR_SCR1L_RUN1_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of + length 2 detected during entropy generation. */ + { + if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) + { + TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); + TRNG_WR_SCR2L_RUN2_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of + length 3 detected during entropy generation. */ + { + if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) + { + TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); + TRNG_WR_SCR3L_RUN3_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of + length 4 detected during entropy generation. */ + { + if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) + { + TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); + TRNG_WR_SCR4L_RUN4_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of + length 5 detected during entropy generation. */ + { + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); + TRNG_WR_SCR5L_RUN5_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of + length 6 or more detected during entropy + generation */ + { + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); + TRNG_WR_SCR6PL_RUN6P_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker + Test" detected during entropy generation . */ + { + if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) + { + TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); + TRNG_WR_PKRRNG_PKR_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of + entropy sample frquency count during + entropy generation . */ { - case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during - entropy generation. */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) - { - TRNG_WR_SCML_MONO_MAX(base, limit->maximum); - TRNG_WR_SCML_MONO_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected - during entropy generation. */ - if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) - { - TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); - TRNG_WR_SCR1L_RUN1_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected - during entropy generation. */ - if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) - { - TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); - TRNG_WR_SCR2L_RUN2_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected - during entropy generation. */ - if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) - { - TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); - TRNG_WR_SCR3L_RUN3_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected - during entropy generation. */ - if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) - { - TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); - TRNG_WR_SCR4L_RUN4_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected - during entropy generation. */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); - TRNG_WR_SCR5L_RUN5_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected - during entropy generation */ - if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) - { - TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); - TRNG_WR_SCR6PL_RUN6P_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during - entropy generation . */ - if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) - { - TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); - TRNG_WR_PKRRNG_PKR_RNG(base, range); - } - else - { - status = kStatus_InvalidArgument; - } - break; - case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency - count during entropy generation . */ - if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) - { - TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); - TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); - } - else - { - status = kStatus_InvalidArgument; - } - break; - default: + if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) + { + TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); + TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); + } + else + { status = kStatus_InvalidArgument; - break; + } + } + else + { + status = kStatus_InvalidArgument; } } @@ -1477,35 +1486,75 @@ static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userC { status_t status; - if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, - &userConfig->runBit6PlusLimit)) == kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) == - kStatus_Success) && - ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, - &userConfig->frequencyCountLimit)) == kStatus_Success)) + status = trng_SetRetryCount(base, userConfig->retryCount); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit); + if (kStatus_Success != status) { - TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); - TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); - TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); - TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); - TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); - TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); - TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); + return status; } + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit); + if (kStatus_Success != status) + { + return status; + } + + status = + trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit); + if (kStatus_Success != status) + { + return status; + } + + TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); + TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); + TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); + TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); + TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); + TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); + TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); + return status; } @@ -1515,7 +1564,7 @@ static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userC * This function gets an entropy data from TRNG. * Entropy data is spread over TRNG_ENT_COUNT registers. * Read register number is defined by index parameter. -*/ + */ static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) { uint32_t data; @@ -1524,7 +1573,7 @@ static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) data = TRNG_RD_ENT(base, index); - if (index == (TRNG_ENT_COUNT - 1)) + if (index == (TRNG_ENT_COUNT - 1u)) { /* Dummy read. Defect workaround. * TRNG could not clear ENT_VAL flag automatically, application @@ -1572,13 +1621,13 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) /* Enable TRNG Access Mode. To generate an Entropy - * value that can be read via the true0-true15 registers.*/ + * value that can be read via the true0-true15 registers.*/ TRNG_WR_MCTL_TRNG_ACC(base, 1); #endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ - (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); + (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); - if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */ + if (true == userConfig->lock) /* Disable programmability of TRNG registers. */ { TRNG_WR_SEC_CFG_NO_PRGM(base, 1); } @@ -1604,7 +1653,7 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) void TRNG_Deinit(TRNG_Type *base) { /* Check input parameters.*/ - if (base) + if (NULL != base) { /* Move to program mode. Stop entropy generation.*/ TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); @@ -1615,7 +1664,7 @@ void TRNG_Deinit(TRNG_Type *base) is complete. If the TRNG clock is stopped while the TRNG ring oscillator is running, the oscillator continues running though the RNG clock. is stopped. */ - while (TRNG_RD_MCTL_TSTOP_OK(base) == 0) + while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u) { } @@ -1644,20 +1693,27 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) uint32_t random_size; uint8_t *data_p = (uint8_t *)data; uint32_t i; + uint32_t tmpValidFlag; + uint32_t tmpErrorFlag; + int index = 0; /* Check input parameters.*/ - if (base && data && dataSize) + if ((NULL != base) && (NULL != data) && (0U != dataSize)) { do { /* Wait for Valid or Error flag*/ - while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0)) + tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); + tmpErrorFlag = TRNG_RD_MCTL_ERR(base); + while (tmpValidFlag == 0u && tmpErrorFlag == 0u) { + tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); + tmpErrorFlag = TRNG_RD_MCTL_ERR(base); } /* Check HW error.*/ - if (TRNG_RD_MCTL_ERR(base)) + if (0U != TRNG_RD_MCTL_ERR(base)) { result = kStatus_Fail; /* TRNG module error occurred */ /* Clear error.*/ @@ -1666,7 +1722,7 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) } /* Read Entropy.*/ - random_32 = trng_ReadEntropy(base, index++); + random_32 = trng_ReadEntropy(base, (uint32_t)index++); random_p = (uint8_t *)&random_32; @@ -1685,13 +1741,13 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) } dataSize -= random_size; - } while (dataSize > 0); + } while (dataSize > 0u); /* Start a new entropy generation. It is done by reading of the last entropy register.*/ - if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1)) + if (((unsigned)index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1u)) { - trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1)); + (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); } } else diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h index ec58261747a0c..a2c3911428f7c 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_trng.h @@ -23,11 +23,13 @@ /*! @name Driver version */ /*@{*/ -/*! @brief TRNG driver version 2.0.3. +/*! @brief TRNG driver version 2.0.4. * - * Current version: 2.0.3 + * Current version: 2.0.4 * * Change log: + * - version 2.0.4 + * - Fix MISRA-2012 issues. * - Version 2.0.3 * - update TRNG_Init to restart entropy generation * - Version 2.0.2 @@ -36,14 +38,14 @@ * - add support for KL8x and KL28Z * - update default OSCDIV for K81 to divide by 2 */ -#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ /*! @brief TRNG sample mode. Used by trng_config_t. */ typedef enum _trng_sample_mode { kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ - kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ + kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ kTRNG_SampleModeVonNeumannRaw = 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ } trng_sample_mode_t; @@ -52,7 +54,7 @@ typedef enum _trng_sample_mode typedef enum _trng_clock_mode { kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ - kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and + kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and indeterminate results may occur. */ } trng_clock_mode_t; @@ -89,44 +91,36 @@ typedef struct _trng_user_config entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during Entropy generation. */ - uint16_t - sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of - * consecutive samples that may be discarded before an error is generated. - * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). - * Samples are discarded if two consecutive raw samples are both 0 or both 1. If - * this discarding occurs for a long period of time, it indicates that there is - * insufficient Entropy. */ + uint16_t sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of + * consecutive samples that may be discarded before an error is generated. + * This limit is used only for during von Neumann sampling (enabled by + * TRNG_HAL_SetSampleMode()). Samples are discarded if two consecutive raw samples are both + * 0 or both 1. If this discarding occurs for a long period of time, it indicates that + * there is insufficient Entropy. */ /* Statistical Check Parameters.*/ uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails - * during the TRNG Entropy Generation before generating an error. */ + * during the TRNG Entropy Generation before generating an error. */ uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, - * that is allowed during the Entropy generation. */ - trng_statistical_check_limit_t - monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected - during entropy generation. */ - trng_statistical_check_limit_t - runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4 - detected during entropy generation. */ - trng_statistical_check_limit_t - runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5 - detected during entropy generation. */ + * that is allowed during the Entropy generation. */ + trng_statistical_check_limit_t monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number + of ones/zero detected during entropy generation. */ + trng_statistical_check_limit_t runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 1 detected during entropy generation. */ + trng_statistical_check_limit_t runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 2 detected during entropy generation. */ + trng_statistical_check_limit_t runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 3 detected during entropy generation. */ + trng_statistical_check_limit_t runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 4 detected during entropy generation. */ + trng_statistical_check_limit_t runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 5 detected during entropy generation. */ trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 6 or more detected during entropy generation. */ trng_statistical_check_limit_t pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ - trng_statistical_check_limit_t - frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency - count. */ + trng_statistical_check_limit_t frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of + entropy sample frequency count. */ } trng_config_t; /******************************************************************************* diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c index 275b98377a4b2..54ee7e61943aa 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c @@ -46,7 +46,7 @@ static uint32_t WDOG_GetInstance(WDOG_Type *base) } /*! - * brief Initializes the WDOG configuration sturcture. + * brief Initializes the WDOG configuration structure. * * This function initializes the WDOG configuration structure to default values. The default * values are as follows. @@ -72,16 +72,16 @@ void WDOG_GetDefaultConfig(wdog_config_t *config) /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); - config->enableWdog = true; - config->workMode.enableWait = false; - config->workMode.enableStop = false; - config->workMode.enableDebug = false; - config->enableInterrupt = false; + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; config->softwareResetExtension = false; - config->enablePowerDown = false; - config->timeoutValue = 0xffu; - config->interruptTimeValue = 0x04u; - config->enableTimeOutAssert = false; + config->enablePowerDown = false; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; + config->enableTimeOutAssert = false; } /*! @@ -113,13 +113,13 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Set configruation */ + /* Set configuration */ CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); #endif base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); - base->WCR = value; + base->WCR = value; if (config->enableInterrupt) { EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]); diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h index d3b533f2dcd76..d8e0628a3ec07 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h @@ -66,11 +66,11 @@ enum _wdog_interrupt_enable */ enum _wdog_status_flags { - kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ - kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ - kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ - kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ }; /******************************************************************************* @@ -87,7 +87,7 @@ extern "C" { */ /*! - * @brief Initializes the WDOG configuration sturcture. + * @brief Initializes the WDOG configuration structure. * * This function initializes the WDOG configuration structure to default values. The default * values are as follows. diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c index 9b081c0d704dc..ab39eb738fe51 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c @@ -17,6 +17,9 @@ #define FSL_COMPONENT_ID "platform.drivers.xbara" #endif +/* Macros for entire XBARA_CTRL register. */ +#define XBARA_CTRLx(base, index) ((&(base->CTRL0))[index]) + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -188,74 +191,32 @@ void XBARA_SetOutputSignalConfig(XBARA_Type *base, const xbara_control_config_t *controlConfig) { uint16_t regVal; - /* Set active edge for edge detection, set interrupt or DMA function. */ - switch ((uint16_t)output) + uint8_t outputIndex = (uint8_t)output & 0xFFU; + uint8_t regIndex; + uint8_t shiftInReg; + + assert(outputIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + + regIndex = outputIndex / 2; + + if ((outputIndex & 0x01U) != 0U) { -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 - case kXBARA1_OutputDmaChMuxReq30: -#else - case kXBARA_OutputDmamux18: -#endif - /* Assign regVal to CTRL0 register's value */ - regVal = (base->CTRL0); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT)); - /* Write regVal value into CTRL0 register */ - base->CTRL0 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 - case kXBARA1_OutputDmaChMuxReq31: -#else - case kXBARA_OutputDmamux19: -#endif - /* Assign regVal to CTRL0 register's value */ - regVal = (base->CTRL0); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT)); - /* Write regVal value into CTRL0 register */ - base->CTRL0 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 - case kXBARA1_OutputDmaChMuxReq94: -#else - case kXBARA_OutputDmamux20: -#endif - /* Assign regVal to CTRL1 register's value */ - regVal = (base->CTRL1); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT)); - /* Write regVal value into CTRL1 register */ - base->CTRL1 = regVal; - break; -#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 - case kXBARA1_OutputDmaChMuxReq95: -#else - case kXBARA_OutputDmamux21: -#endif - /* Assign regVal to CTRL1 register's value */ - regVal = (base->CTRL1); - /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */ - regVal &= (uint16_t)( - ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK)); - /* Configure edge and request type */ - regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) | - ((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT)); - /* Write regVal value into CTRL1 register */ - base->CTRL1 = regVal; - break; - default: - break; + shiftInReg = 8; + } + else + { + shiftInReg = 0; } + + regVal = XBARA_CTRLx(base, regIndex); + + /* Don't clear the status flags. */ + regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + + regVal &= (uint16_t)(~((XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK | XBARA_CTRL0_EDGE0_MASK) << shiftInReg)); + regVal |= (uint16_t)( + (XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT)) + << shiftInReg); + + XBARA_CTRLx(base, regIndex) = regVal; } diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.h b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.h index f3f71d21e4759..c3db766923312 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_xbara.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,10 +35,10 @@ */ typedef enum _xbara_active_edge { - kXBARA_EdgeNone = 0U, /*!< Edge detection status bit never asserts. */ - kXBARA_EdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ - kXBARA_EdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ - kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ + kXBARA_EdgeNone = 0U, /*!< Edge detection status bit never asserts. */ + kXBARA_EdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ + kXBARA_EdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ + kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ } xbara_active_edge_t; /*! @@ -46,9 +46,9 @@ typedef enum _xbara_active_edge */ typedef enum _xbar_request { - kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ - kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ - kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ + kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ + kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ + kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ } xbara_request_t; /*! diff --git a/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.h b/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.h index ad83f51e59631..b4598806058cb 100644 --- a/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.h +++ b/ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.h @@ -2,7 +2,7 @@ * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. - * + * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 new file mode 100644 index 0000000000000..6d12ad502c1fe --- /dev/null +++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 @@ -0,0 +1,29 @@ +# Kconfig - i.MX RT1015 +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_MIMXRT1015 + +config SOC + string + default "mimxrt1015" + +config NUM_IRQS + default 142 + +config ARM_DIV + default 0 + +config AHB_DIV + default 0 + +config IPG_DIV + default 3 + +config GPIO + default y + +endif # SOC_MIMXRT1015 diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index 6e29b69dba8b2..f7ba92da58598 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -9,6 +9,22 @@ choice prompt "i.MX RT Selection" depends on SOC_SERIES_IMX_RT +config SOC_MIMXRT1015 + bool "SOC_MIMXRT1015" + select HAS_MCUX + select HAS_MCUX_CACHE + select HAS_MCUX_CCM + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPUART + select HAS_MCUX_TRNG + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_SYS_PLL + select INIT_USB1_PLL + select INIT_ENET_PLL + config SOC_MIMXRT1021 bool "SOC_MIMXRT1021" select HAS_MCUX @@ -117,6 +133,12 @@ endchoice if SOC_SERIES_IMX_RT +config SOC_PART_NUMBER_MIMXRT1015CAF4A + bool + +config SOC_PART_NUMBER_MIMXRT1015DAF5A + bool + config SOC_PART_NUMBER_MIMXRT1021CAF4A bool @@ -173,6 +195,8 @@ config SOC_PART_NUMBER_MIMXRT1064DVL6A config SOC_PART_NUMBER_IMX_RT string + default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A + default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A diff --git a/soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h b/soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h index 25a26ab47bbbc..8c328aae0999b 100644 --- a/soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h +++ b/soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h @@ -26,6 +26,8 @@ #define REGION_FLASH_SIZE REGION_4M #elif CONFIG_FLASH_SIZE == 8192 #define REGION_FLASH_SIZE REGION_8M +#elif CONFIG_FLASH_SIZE == 16384 +#define REGION_FLASH_SIZE REGION_16M #elif CONFIG_FLASH_SIZE == 65536 #define REGION_FLASH_SIZE REGION_64M #else diff --git a/soc/arm/nxp_imx/rt/soc.c b/soc/arm/nxp_imx/rt/soc.c index 126a07f76ec73..b514df68fff8a 100644 --- a/soc/arm/nxp_imx/rt/soc.c +++ b/soc/arm/nxp_imx/rt/soc.c @@ -38,7 +38,7 @@ const clock_usb_pll_config_t usb1PllConfig = { #ifdef CONFIG_INIT_ENET_PLL /* ENET PLL configuration for RUN mode */ const clock_enet_pll_config_t ethPllConfig = { -#ifdef CONFIG_SOC_MIMXRT1021 +#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015) .enableClkOutput500M = true, #endif #ifdef CONFIG_ETH_MCUX