diff --git a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
index 82f37189c4581..ab518ee57842a 100644
--- a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
+++ b/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
@@ -168,6 +168,8 @@ features:
 +===========+============+=====================================+
 | NVIC      | on-chip    | nested vector interrupt controller  |
 +-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 ``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig``
diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml
index 88049075c0052..639b2fa496558 100644
--- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml
+++ b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml
@@ -6,8 +6,11 @@ toolchain:
   - zephyr
   - gccarmemb
   - xtools
+supported:
+  - gpio
 testing:
   ignore_tags:
+    - cmsis_rtos_v2
     - net
     - mpu
     - tinycrypt
@@ -16,7 +19,6 @@ testing:
     - cmm
     - shell
     - LED
-    - gpio
     - nfc
 ram: 256
 flash: 64
diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig
index 19fd10e70fff4..5066a9a5d441a 100644
--- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig
+++ b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig
@@ -6,8 +6,11 @@ CONFIG_CORTEX_M_SYSTICK=y
 # 209 MHz system clock
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000
 
+# enable GPIO
+CONFIG_GPIO=y
+
 # clock configuration
-CONFIG_CLOCK_CONTROL=n
+CONFIG_CLOCK_CONTROL=y
 
 #remote proc console
 CONFIG_CONSOLE=y
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index d52e8a2662856..6ce011d15f43f 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -8,16 +8,19 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE            quark_se_clock_con
 zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
-  zephyr_sources(stm32_ll_clock.c)
-
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X stm32f0x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X stm32f1x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X stm32f2x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X stm32f3x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X stm32f4x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X stm32f7x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X stm32l0x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X stm32l1x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X stm32l4x_ll_clock.c)
-  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX stm32wbx_ll_clock.c)
+if(CONFIG_SOC_SERIES_STM32MP1X)
+  zephyr_sources(clock_stm32_ll_mp1x.c)
+else()
+  zephyr_sources(clock_stm32_ll_common.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f3x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f4x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f7x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l1x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4x.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32wbx.c)
+endif()
 endif()
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 9b44de15bc7d6..0aebee4024127 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -11,6 +11,7 @@ if SOC_FAMILY_STM32
 menuconfig CLOCK_CONTROL_STM32_CUBE
 	bool "STM32 Reset & Clock Control"
 	select USE_STM32_LL_UTILS
+	select USE_STM32_LL_RCC if SOC_SERIES_STM32MP1X
 	help
 	  Enable driver for Reset & Clock Control subsystem found
 	  in STM32 family of MCUs
diff --git a/drivers/clock_control/stm32_ll_clock.c b/drivers/clock_control/clock_stm32_ll_common.c
similarity index 99%
rename from drivers/clock_control/stm32_ll_clock.c
rename to drivers/clock_control/clock_stm32_ll_common.c
index 462092ec74e2d..24844494ef7f2 100644
--- a/drivers/clock_control/stm32_ll_clock.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 /* Macros to fill up prescaler values */
 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
diff --git a/drivers/clock_control/stm32_ll_clock.h b/drivers/clock_control/clock_stm32_ll_common.h
similarity index 100%
rename from drivers/clock_control/stm32_ll_clock.h
rename to drivers/clock_control/clock_stm32_ll_common.h
diff --git a/drivers/clock_control/clock_stm32_ll_mp1x.c b/drivers/clock_control/clock_stm32_ll_mp1x.c
new file mode 100644
index 0000000000000..e2365386bede4
--- /dev/null
+++ b/drivers/clock_control/clock_stm32_ll_mp1x.c
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <clock_control.h>
+#include <misc/util.h>
+#include <clock_control/stm32_clock_control.h>
+
+/**
+ * @brief fill in AHB/APB buses configuration structure
+ */
+static inline int stm32_clock_control_on(struct device *dev,
+					 clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+
+	ARG_UNUSED(dev);
+
+	switch (pclken->bus) {
+	case STM32_CLOCK_BUS_APB1:
+		LL_APB1_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB2:
+		LL_APB2_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB3:
+		LL_APB3_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB4:
+		LL_APB4_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB5:
+		LL_APB5_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB2:
+		LL_AHB2_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB3:
+		LL_AHB3_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB4:
+		LL_AHB4_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB5:
+		LL_AHB5_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB6:
+		LL_AHB6_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AXI:
+		LL_AXI_GRP1_EnableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_MLAHB:
+		LL_MLAHB_GRP1_EnableClock(pclken->enr);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static inline int stm32_clock_control_off(struct device *dev,
+					  clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+
+	ARG_UNUSED(dev);
+
+	switch (pclken->bus) {
+	case STM32_CLOCK_BUS_APB1:
+		LL_APB1_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB2:
+		LL_APB2_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB3:
+		LL_APB3_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB4:
+		LL_APB4_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_APB5:
+		LL_APB5_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB2:
+		LL_AHB2_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB3:
+		LL_AHB3_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB4:
+		LL_AHB4_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB5:
+		LL_AHB5_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AHB6:
+		LL_AHB6_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_AXI:
+		LL_AXI_GRP1_DisableClock(pclken->enr);
+		break;
+	case STM32_CLOCK_BUS_MLAHB:
+		LL_MLAHB_GRP1_DisableClock(pclken->enr);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int stm32_clock_control_get_subsys_rate(struct device *clock,
+					clock_control_subsys_t sub_system,
+					u32_t *rate)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+
+	ARG_UNUSED(clock);
+
+	switch (pclken->bus) {
+	case STM32_CLOCK_BUS_APB1:
+		switch (pclken->enr) {
+		case LL_APB1_GRP1_PERIPH_TIM2:
+		case LL_APB1_GRP1_PERIPH_TIM3:
+		case LL_APB1_GRP1_PERIPH_TIM4:
+		case LL_APB1_GRP1_PERIPH_TIM5:
+		case LL_APB1_GRP1_PERIPH_TIM6:
+		case LL_APB1_GRP1_PERIPH_TIM7:
+		case LL_APB1_GRP1_PERIPH_TIM12:
+		case LL_APB1_GRP1_PERIPH_TIM13:
+		case LL_APB1_GRP1_PERIPH_TIM14:
+			*rate = LL_RCC_GetTIMGClockFreq(LL_RCC_TIMG1PRES);
+			break;
+		case LL_APB1_GRP1_PERIPH_LPTIM1:
+			*rate = LL_RCC_GetLPTIMClockFreq(
+					LL_RCC_LPTIM1_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_SPI2:
+		case LL_APB1_GRP1_PERIPH_SPI3:
+			*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_USART2:
+		case LL_APB1_GRP1_PERIPH_UART4:
+			*rate = LL_RCC_GetUARTClockFreq(
+					LL_RCC_UART24_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_USART3:
+		case LL_APB1_GRP1_PERIPH_UART5:
+			*rate = LL_RCC_GetUARTClockFreq(
+					LL_RCC_UART35_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_UART7:
+		case LL_APB1_GRP1_PERIPH_UART8:
+			*rate = LL_RCC_GetUARTClockFreq(
+					LL_RCC_UART78_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_I2C1:
+		case LL_APB1_GRP1_PERIPH_I2C2:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_I2C3:
+		case LL_APB1_GRP1_PERIPH_I2C5:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C35_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_SPDIF:
+			*rate = LL_RCC_GetSPDIFRXClockFreq(
+					LL_RCC_SPDIFRX_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_CEC:
+			*rate = LL_RCC_GetCECClockFreq(LL_RCC_CEC_CLKSOURCE);
+			break;
+		case LL_APB1_GRP1_PERIPH_WWDG1:
+		case LL_APB1_GRP1_PERIPH_DAC12:
+		case LL_APB1_GRP1_PERIPH_MDIOS:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_APB2:
+		switch (pclken->enr) {
+		case LL_APB2_GRP1_PERIPH_TIM1:
+		case LL_APB2_GRP1_PERIPH_TIM8:
+		case LL_APB2_GRP1_PERIPH_TIM15:
+		case LL_APB2_GRP1_PERIPH_TIM16:
+		case LL_APB2_GRP1_PERIPH_TIM17:
+			*rate = LL_RCC_GetTIMGClockFreq(LL_RCC_TIMG2PRES);
+			break;
+		case LL_APB2_GRP1_PERIPH_SPI1:
+			*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_SPI4:
+		case LL_APB2_GRP1_PERIPH_SPI5:
+			*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI45_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_USART6:
+			*rate = LL_RCC_GetUARTClockFreq(
+					LL_RCC_USART6_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_SAI1:
+			*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_SAI2:
+			*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_SAI3:
+			*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI3_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_DFSDM1:
+			*rate = LL_RCC_GetDFSDMClockFreq(
+					LL_RCC_DFSDM_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_FDCAN:
+			*rate = LL_RCC_GetFDCANClockFreq(
+					LL_RCC_FDCAN_CLKSOURCE);
+			break;
+		case LL_APB2_GRP1_PERIPH_ADFSDM1:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_APB3:
+		switch (pclken->enr) {
+		case LL_APB3_GRP1_PERIPH_LPTIM2:
+		case LL_APB3_GRP1_PERIPH_LPTIM3:
+			*rate = LL_RCC_GetLPTIMClockFreq(
+					LL_RCC_LPTIM23_CLKSOURCE);
+			break;
+		case LL_APB3_GRP1_PERIPH_LPTIM4:
+		case LL_APB3_GRP1_PERIPH_LPTIM5:
+			*rate = LL_RCC_GetLPTIMClockFreq(
+					LL_RCC_LPTIM45_CLKSOURCE);
+			break;
+		case LL_APB3_GRP1_PERIPH_SAI4:
+			*rate = LL_RCC_GetSAIClockFreq(LL_RCC_SAI4_CLKSOURCE);
+			break;
+		case LL_APB3_GRP1_PERIPH_SYSCFG:
+		case LL_APB3_GRP1_PERIPH_VREF:
+		case LL_APB3_GRP1_PERIPH_TMPSENS:
+		case LL_APB3_GRP1_PERIPH_PMBCTRL:
+		case LL_APB3_GRP1_PERIPH_HDP:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_APB4:
+		switch (pclken->enr) {
+		case LL_APB4_GRP1_PERIPH_LTDC:
+			*rate = LL_RCC_GetLTDCClockFreq();
+			break;
+		case LL_APB4_GRP1_PERIPH_DSI:
+			*rate = LL_RCC_GetDSIClockFreq(LL_RCC_DSI_CLKSOURCE);
+			break;
+		case LL_APB4_GRP1_PERIPH_USBPHY:
+			*rate = LL_RCC_GetUSBPHYClockFreq(
+					LL_RCC_USBPHY_CLKSOURCE);
+			break;
+		case LL_APB4_GRP1_PERIPH_DDRPERFM:
+		case LL_APB4_GRP1_PERIPH_STGENRO:
+		case LL_APB4_GRP1_PERIPH_STGENROSTP:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_APB5:
+		switch (pclken->enr) {
+		case LL_APB5_GRP1_PERIPH_SPI6:
+			*rate = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
+			break;
+		case LL_APB5_GRP1_PERIPH_I2C4:
+		case LL_APB5_GRP1_PERIPH_I2C6:
+			*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C46_CLKSOURCE);
+		case LL_APB5_GRP1_PERIPH_USART1:
+			*rate = LL_RCC_GetUARTClockFreq(
+					LL_RCC_USART1_CLKSOURCE);
+			break;
+		case LL_APB5_GRP1_PERIPH_STGEN:
+		case LL_APB5_GRP1_PERIPH_STGENSTP:
+			*rate = LL_RCC_GetSTGENClockFreq(
+					LL_RCC_STGEN_CLKSOURCE);
+			break;
+		case LL_APB5_GRP1_PERIPH_RTCAPB:
+			*rate = LL_RCC_GetRTCClockFreq();
+			break;
+		case LL_APB5_GRP1_PERIPH_TZC1:
+		case LL_APB5_GRP1_PERIPH_TZC2:
+		case LL_APB5_GRP1_PERIPH_TZPC:
+		case LL_APB5_GRP1_PERIPH_BSEC:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_AHB2:
+		switch (pclken->enr) {
+		case LL_AHB2_GRP1_PERIPH_ADC12:
+			*rate = LL_RCC_GetADCClockFreq(LL_RCC_ADC_CLKSOURCE);
+			break;
+		case LL_AHB2_GRP1_PERIPH_USBO:
+			*rate = LL_RCC_GetUSBOClockFreq(LL_RCC_USBO_CLKSOURCE);
+			break;
+		case LL_AHB2_GRP1_PERIPH_SDMMC3:
+			*rate = LL_RCC_GetSDMMCClockFreq(
+					LL_RCC_SDMMC3_CLKSOURCE);
+			break;
+		case LL_AHB2_GRP1_PERIPH_DMA1:
+		case LL_AHB2_GRP1_PERIPH_DMA2:
+		case LL_AHB2_GRP1_PERIPH_DMAMUX:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_AHB3:
+		switch (pclken->enr) {
+		case LL_AHB3_GRP1_PERIPH_RNG2:
+			*rate = LL_RCC_GetRNGClockFreq(LL_RCC_RNG2_CLKSOURCE);
+			break;
+		case LL_AHB3_GRP1_PERIPH_DCMI:
+		case LL_AHB3_GRP1_PERIPH_CRYP2:
+		case LL_AHB3_GRP1_PERIPH_HASH2:
+		case LL_AHB3_GRP1_PERIPH_CRC2:
+		case LL_AHB3_GRP1_PERIPH_HSEM:
+		case LL_AHB3_GRP1_PERIPH_IPCC:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_AHB4:
+		return -ENOTSUP;
+	case STM32_CLOCK_BUS_AHB5:
+		switch (pclken->enr) {
+		case LL_AHB5_GRP1_PERIPH_RNG1:
+			*rate = LL_RCC_GetRNGClockFreq(LL_RCC_RNG1_CLKSOURCE);
+			break;
+		case LL_AHB5_GRP1_PERIPH_GPIOZ:
+		case LL_AHB5_GRP1_PERIPH_CRYP1:
+		case LL_AHB5_GRP1_PERIPH_HASH1:
+		case LL_AHB5_GRP1_PERIPH_BKPSRAM:
+		case LL_AHB5_GRP1_PERIPH_AXIMC:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_AHB6:
+		switch (pclken->enr) {
+		case LL_AHB6_GRP1_PERIPH_ETH1CK:
+		case LL_AHB6_GRP1_PERIPH_ETH1TX:
+		case LL_AHB6_GRP1_PERIPH_ETH1RX:
+		case LL_AHB6_GRP1_PERIPH_ETH1MAC:
+		case LL_AHB6_GRP1_PERIPH_ETH1STP:
+			*rate = LL_RCC_GetETHClockFreq(LL_RCC_ETH_CLKSOURCE);
+			break;
+		case LL_AHB6_GRP1_PERIPH_FMC:
+			*rate = LL_RCC_GetFMCClockFreq(LL_RCC_FMC_CLKSOURCE);
+			break;
+		case LL_AHB6_GRP1_PERIPH_QSPI:
+			*rate = LL_RCC_GetQSPIClockFreq(LL_RCC_QSPI_CLKSOURCE);
+			break;
+		case LL_AHB6_GRP1_PERIPH_SDMMC1:
+		case LL_AHB6_GRP1_PERIPH_SDMMC2:
+			*rate = LL_RCC_GetSDMMCClockFreq(
+					LL_RCC_SDMMC12_CLKSOURCE);
+			break;
+		case LL_AHB6_GRP1_PERIPH_MDMA:
+		case LL_AHB6_GRP1_PERIPH_GPU:
+		case LL_AHB6_GRP1_PERIPH_CRC1:
+		case LL_AHB6_GRP1_PERIPH_USBH:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_AXI:
+		switch (pclken->enr) {
+		case LL_AXI_GRP1_PERIPH_SYSRAMEN:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	case STM32_CLOCK_BUS_MLAHB:
+		switch (pclken->enr) {
+		case LL_MLAHB_GRP1_PERIPH_RETRAMEN:
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+
+static struct clock_control_driver_api stm32_clock_control_api = {
+	.on = stm32_clock_control_on,
+	.off = stm32_clock_control_off,
+	.get_rate = stm32_clock_control_get_subsys_rate,
+};
+
+static int stm32_clock_control_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 0;
+}
+
+/**
+ * @brief RCC device, note that priority is intentionally set to 1 so
+ * that the device init runs just after SOC init
+ */
+DEVICE_AND_API_INIT(rcc_stm32, STM32_CLOCK_CONTROL_NAME,
+		    &stm32_clock_control_init,
+		    NULL, NULL,
+		    PRE_KERNEL_1,
+		    CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY,
+		    &stm32_clock_control_api);
diff --git a/drivers/clock_control/stm32f0x_ll_clock.c b/drivers/clock_control/clock_stm32f0x.c
similarity index 98%
rename from drivers/clock_control/stm32f0x_ll_clock.c
rename to drivers/clock_control/clock_stm32f0x.c
index 95f1949993b4e..ca55c9b8f5123 100644
--- a/drivers/clock_control/stm32f0x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f0x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32f1x_ll_clock.c b/drivers/clock_control/clock_stm32f1x.c
similarity index 98%
rename from drivers/clock_control/stm32f1x_ll_clock.c
rename to drivers/clock_control/clock_stm32f1x.c
index 92c012403b701..e76f0d5e3ed40 100644
--- a/drivers/clock_control/stm32f1x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f1x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32f2x_ll_clock.c b/drivers/clock_control/clock_stm32f2x.c
similarity index 96%
rename from drivers/clock_control/stm32f2x_ll_clock.c
rename to drivers/clock_control/clock_stm32f2x.c
index 6fae07d1e5400..350eec3965227 100644
--- a/drivers/clock_control/stm32f2x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f2x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32f3x_ll_clock.c b/drivers/clock_control/clock_stm32f3x.c
similarity index 98%
rename from drivers/clock_control/stm32f3x_ll_clock.c
rename to drivers/clock_control/clock_stm32f3x.c
index 254e0eb6e38ad..303cca145fcc5 100644
--- a/drivers/clock_control/stm32f3x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f3x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32f4x_ll_clock.c b/drivers/clock_control/clock_stm32f4x.c
similarity index 96%
rename from drivers/clock_control/stm32f4x_ll_clock.c
rename to drivers/clock_control/clock_stm32f4x.c
index 7856644618117..70031f8cbbafc 100644
--- a/drivers/clock_control/stm32f4x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f4x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32f7x_ll_clock.c b/drivers/clock_control/clock_stm32f7x.c
similarity index 96%
rename from drivers/clock_control/stm32f7x_ll_clock.c
rename to drivers/clock_control/clock_stm32f7x.c
index 43f49f3b9f01c..cac835a84e3ca 100644
--- a/drivers/clock_control/stm32f7x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32f7x.c
@@ -9,7 +9,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32l0x_ll_clock.c b/drivers/clock_control/clock_stm32l0x.c
similarity index 96%
rename from drivers/clock_control/stm32l0x_ll_clock.c
rename to drivers/clock_control/clock_stm32l0x.c
index 296623ef5b356..188e06b6cfd88 100644
--- a/drivers/clock_control/stm32l0x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32l0x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32l1x_ll_clock.c b/drivers/clock_control/clock_stm32l1x.c
similarity index 96%
rename from drivers/clock_control/stm32l1x_ll_clock.c
rename to drivers/clock_control/clock_stm32l1x.c
index 222a01ebea30c..3c2338eff6f34 100644
--- a/drivers/clock_control/stm32l1x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32l1x.c
@@ -10,7 +10,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32l4x_ll_clock.c b/drivers/clock_control/clock_stm32l4x.c
similarity index 97%
rename from drivers/clock_control/stm32l4x_ll_clock.c
rename to drivers/clock_control/clock_stm32l4x.c
index 1ee58bf442a7f..ca2c706fe5c2c 100644
--- a/drivers/clock_control/stm32l4x_ll_clock.c
+++ b/drivers/clock_control/clock_stm32l4x.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
diff --git a/drivers/clock_control/stm32wbx_ll_clock.c b/drivers/clock_control/clock_stm32wbx.c
similarity index 96%
rename from drivers/clock_control/stm32wbx_ll_clock.c
rename to drivers/clock_control/clock_stm32wbx.c
index 1554f929c7114..397a6d7e0ed09 100644
--- a/drivers/clock_control/stm32wbx_ll_clock.c
+++ b/drivers/clock_control/clock_stm32wbx.c
@@ -11,7 +11,7 @@
 #include <clock_control.h>
 #include <misc/util.h>
 #include <clock_control/stm32_clock_control.h>
-#include "stm32_ll_clock.h"
+#include "clock_stm32_ll_common.h"
 
 #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
 
diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c
index 68a2b0c57fbf5..7e87081600601 100644
--- a/drivers/gpio/gpio_stm32.c
+++ b/drivers/gpio/gpio_stm32.c
@@ -94,6 +94,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
 	GPIO_TypeDef *gpio = (GPIO_TypeDef *)base_addr;
 
 	int pin_ll = stm32_pinval_get(pin);
+
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 	ARG_UNUSED(altf);
 
@@ -179,7 +180,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
 
 	LL_GPIO_SetPinPull(gpio, pin_ll, pupd >> STM32_PUPDR_SHIFT);
 
-#endif /* CONFIG_SOC_SERIES_STM32F1X */
+#endif  /* CONFIG_SOC_SERIES_STM32F1X */
 
 	return 0;
 }
@@ -189,7 +190,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
  */
 const int gpio_stm32_enable_int(int port, int pin)
 {
-#if defined(CONFIG_SOC_SERIES_STM32F2X) || \
+#if defined(CONFIG_SOC_SERIES_STM32F2X) ||     \
 	defined(CONFIG_SOC_SERIES_STM32F3X) || \
 	defined(CONFIG_SOC_SERIES_STM32F4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F7X) || \
@@ -213,6 +214,8 @@ const int gpio_stm32_enable_int(int port, int pin)
 #if defined(CONFIG_SOC_SERIES_STM32L0X) || \
 	defined(CONFIG_SOC_SERIES_STM32F0X)
 	line = ((pin % 4 * 4) << 16) | (pin / 4);
+#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
+	line = (((pin * 8) % 32) << 16) | (pin / 4);
 #else
 	line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
 #endif
@@ -230,6 +233,8 @@ const int gpio_stm32_enable_int(int port, int pin)
 
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 	LL_GPIO_AF_SetEXTISource(port, line);
+#elif CONFIG_SOC_SERIES_STM32MP1X
+	LL_EXTI_SetEXTISource(port, line);
 #else
 	LL_SYSCFG_SetEXTISource(port, line);
 #endif
@@ -282,7 +287,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 
 			if ((flags & GPIO_INT_DOUBLE_EDGE) != 0) {
 				edge = STM32_EXTI_TRIG_RISING |
-					STM32_EXTI_TRIG_FALLING;
+				       STM32_EXTI_TRIG_FALLING;
 			} else if ((flags & GPIO_INT_ACTIVE_HIGH) != 0) {
 				edge = STM32_EXTI_TRIG_RISING;
 			} else {
@@ -411,7 +416,7 @@ static int gpio_stm32_init(struct device *device)
 		device_get_binding(STM32_CLOCK_CONTROL_NAME);
 
 	if (clock_control_on(clk,
-		(clock_control_subsys_t *) &cfg->pclken) != 0) {
+			     (clock_control_subsys_t *)&cfg->pclken) != 0) {
 		return -EIO;
 	}
 
@@ -427,36 +432,35 @@ static int gpio_stm32_init(struct device *device)
 			LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
 		}
 	}
-#endif /* PWR_CR2_IOSV */
+#endif  /* PWR_CR2_IOSV */
 
 	return 0;
 }
 
 
 #define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr, __bus) \
-static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = {	\
-	.base = (u32_t *)__base_addr,				\
-	.port = __port,							\
-	.pclken = { .bus = __bus, .enr = __cenr }			\
-};									\
-static struct gpio_stm32_data gpio_stm32_data_## __suffix;		\
-DEVICE_AND_API_INIT(gpio_stm32_## __suffix,				\
-		    __name,						\
-		    gpio_stm32_init,					\
-		    &gpio_stm32_data_## __suffix,			\
-		    &gpio_stm32_cfg_## __suffix,			\
-		    POST_KERNEL,					\
-		    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,			\
-		    &gpio_stm32_driver);
-
-
-#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX)				\
-	GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL,		\
-			__suffix,						\
-			DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, 	\
-			STM32_PORT##__SUFFIX,					\
-			DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS,		\
-			DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS)
+	static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = {   \
+		.base = (u32_t *)__base_addr,				       \
+		.port = __port,						       \
+		.pclken = { .bus = __bus, .enr = __cenr }		       \
+	};								       \
+	static struct gpio_stm32_data gpio_stm32_data_## __suffix;	       \
+	DEVICE_AND_API_INIT(gpio_stm32_## __suffix,			       \
+			    __name,					       \
+			    gpio_stm32_init,				       \
+			    &gpio_stm32_data_## __suffix,		       \
+			    &gpio_stm32_cfg_## __suffix,		       \
+			    POST_KERNEL,				       \
+			    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	       \
+			    &gpio_stm32_driver)
+
+#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX)		      \
+	GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL,	      \
+			 __suffix,				      \
+			 DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \
+			 STM32_PORT##__SUFFIX,			      \
+			 DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS,   \
+			 DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS)
 
 #ifdef CONFIG_GPIO_STM32_PORTA
 GPIO_DEVICE_INIT_STM32(a, A);
diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h
index c77a4816bd72e..970d9c68667ef 100644
--- a/drivers/gpio/gpio_stm32.h
+++ b/drivers/gpio/gpio_stm32.h
@@ -112,6 +112,19 @@
 #define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
 #define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
 #define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
+#elif CONFIG_SOC_SERIES_STM32MP1X
+#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
+#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
+#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
+#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
+#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
+#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
+#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
+#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
+#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
+#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
+#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
+#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
 #elif CONFIG_SOC_SERIES_STM32WBX
 #define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
 #define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
@@ -123,17 +136,21 @@
 #endif /* CONFIG_SOC_SERIES_.. */
 
 #ifdef CONFIG_SOC_SERIES_STM32F1X
-#define STM32_PINCFG_MODE_OUTPUT	STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT | STM32_CNF_PUSH_PULL
-#define STM32_PINCFG_MODE_INPUT		STM32_MODE_INPUT
-#define STM32_PINCFG_PULL_UP		STM32_CNF_IN_PUPD | STM32_PUPD_PULL_UP
-#define STM32_PINCFG_PULL_DOWN		STM32_CNF_IN_PUPD | STM32_PUPD_PULL_DOWN
-#define STM32_PINCFG_FLOATING		STM32_CNF_IN_FLOAT | STM32_PUPD_NO_PULL
+#define STM32_PINCFG_MODE_OUTPUT        (STM32_MODE_OUTPUT     \
+					 | STM32_CNF_GP_OUTPUT \
+					 | STM32_CNF_PUSH_PULL)
+#define STM32_PINCFG_MODE_INPUT         STM32_MODE_INPUT
+#define STM32_PINCFG_PULL_UP            (STM32_CNF_IN_PUPD | STM32_PUPD_PULL_UP)
+#define STM32_PINCFG_PULL_DOWN          (STM32_CNF_IN_PUPD | \
+					STM32_PUPD_PULL_DOWN)
+#define STM32_PINCFG_FLOATING           (STM32_CNF_IN_FLOAT | \
+					STM32_PUPD_NO_PULL)
 #else
-#define STM32_PINCFG_MODE_OUTPUT	STM32_MODER_OUTPUT_MODE
-#define STM32_PINCFG_MODE_INPUT		STM32_MODER_INPUT_MODE
-#define STM32_PINCFG_PULL_UP		STM32_PUPDR_PULL_UP
-#define STM32_PINCFG_PULL_DOWN		STM32_PUPDR_PULL_DOWN
-#define STM32_PINCFG_FLOATING		STM32_PUPDR_NO_PULL
+#define STM32_PINCFG_MODE_OUTPUT        STM32_MODER_OUTPUT_MODE
+#define STM32_PINCFG_MODE_INPUT         STM32_MODER_INPUT_MODE
+#define STM32_PINCFG_PULL_UP            STM32_PUPDR_PULL_UP
+#define STM32_PINCFG_PULL_DOWN          STM32_PUPDR_PULL_DOWN
+#define STM32_PINCFG_FLOATING           STM32_PUPDR_NO_PULL
 #endif /* CONFIG_SOC_SERIES_STM32F1X */
 
 /**
diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi
index 04b394b190c12..36dba666b1d23 100644
--- a/dts/arm/st/mp1/stm32mp157.dtsi
+++ b/dts/arm/st/mp1/stm32mp157.dtsi
@@ -6,6 +6,8 @@
 
 #include <mem.h>
 #include <arm/armv7-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/stm32_clock.h>
 
 / {
 	cpus {
@@ -33,12 +35,117 @@
 	soc {
 		rcc: rcc@50000000 {
 			compatible = "st,stm32-rcc";
-			clocks-controller;
-			#clocks-cells = <2>;
 			reg = <0x50000000 0x1000>;
+			clocks-controller;
+			#clock-cells = <2>;
 			label = "STM32_CLK_RCC";
 		};
 
+		pinctrl: pin-controller@50002000 {
+			compatible = "st,stm32-pinmux";
+			reg = <0x50002000 0x9000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@50002000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50002000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
+				label = "GPIOA";
+			};
+
+			gpiob: gpio@50003000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50003000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
+				label = "GPIOB";
+			};
+
+			gpioc: gpio@50004000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50004000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
+				label = "GPIOC";
+			};
+
+			gpiod: gpio@50005000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50005000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
+				label = "GPIOD";
+			};
+
+			gpioe: gpio@50006000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50006000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
+				label = "GPIOE";
+			};
+
+			gpiof: gpio@50007000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50007000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
+				label = "GPIOF";
+			};
+
+			gpiog: gpio@50008000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50008000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
+				label = "GPIOG";
+			};
+
+			gpioh: gpio@50009000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50009000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
+				label = "GPIOH";
+			};
+
+			gpioi: gpio@5000a000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000a000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
+				label = "GPIOI";
+			};
+
+			gpioj: gpio@5000b000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000b000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@5000c000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000c000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
+				label = "GPIOK";
+			};
+		};
 	};
 };
 
diff --git a/include/dt-bindings/clock/stm32_clock.h b/include/dt-bindings/clock/stm32_clock.h
index 9e187783682b3..a669f49b92c60 100644
--- a/include/dt-bindings/clock/stm32_clock.h
+++ b/include/dt-bindings/clock/stm32_clock.h
@@ -13,6 +13,14 @@
 #define STM32_CLOCK_BUS_APB2    3
 #define STM32_CLOCK_BUS_APB1_2  4
 #define STM32_CLOCK_BUS_IOP     5
-
+#define STM32_CLOCK_BUS_AHB3    6
+#define STM32_CLOCK_BUS_AHB4    7
+#define STM32_CLOCK_BUS_AHB5    8
+#define STM32_CLOCK_BUS_AHB6    9
+#define STM32_CLOCK_BUS_APB3    10
+#define STM32_CLOCK_BUS_APB4    11
+#define STM32_CLOCK_BUS_APB5    12
+#define STM32_CLOCK_BUS_AXI     13
+#define STM32_CLOCK_BUS_MLAHB   14
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ */
diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series
index 4f843ee4fbd61..2dc3d722376f5 100644
--- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series
+++ b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series
@@ -16,4 +16,32 @@ config STM32_CORE_CM4
 	bool "define stm32 core"
 	default y
 
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTH
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
 endif # SOC_SERIES_STM32MP1X
diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.series
index 53f252cb7051b..5678c0b284f8f 100644
--- a/soc/arm/st_stm32/stm32mp1/Kconfig.series
+++ b/soc/arm/st_stm32/stm32mp1/Kconfig.series
@@ -11,5 +11,6 @@ config SOC_SERIES_STM32MP1X
 	select SOC_FAMILY_STM32
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
 	help
 		Enable support for STM32MP1 MPU series
diff --git a/soc/arm/st_stm32/stm32mp1/dts_fixup.h b/soc/arm/st_stm32/stm32mp1/dts_fixup.h
index 668704a3efd73..51eb1eb3c6cc5 100644
--- a/soc/arm/st_stm32/stm32mp1/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32mp1/dts_fixup.h
@@ -8,4 +8,190 @@
 
 #define DT_NUM_IRQ_PRIO_BITS  DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
 
+#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50002000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50002000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50002000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50002000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOA_LABEL               \
+				DT_ST_STM32_GPIO_50002000_LABEL
+#define DT_GPIO_STM32_GPIOA_SIZE                \
+				DT_ST_STM32_GPIO_50002000_SIZE
+#define DT_GPIO_STM32_GPIOA_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50002000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOA_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50002000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50003000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50003000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50003000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50003000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOB_LABEL               \
+				DT_ST_STM32_GPIO_50003000_LABEL
+#define DT_GPIO_STM32_GPIOB_SIZE                \
+				DT_ST_STM32_GPIO_50003000_SIZE
+#define DT_GPIO_STM32_GPIOB_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50003000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOB_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50003000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50004000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50004000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50004000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50004000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOC_LABEL               \
+				DT_ST_STM32_GPIO_50004000_LABEL
+#define DT_GPIO_STM32_GPIOC_SIZE                \
+				DT_ST_STM32_GPIO_50004000_SIZE
+#define DT_GPIO_STM32_GPIOC_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50004000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOC_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50004000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50005000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50005000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0         \
+				T_ST_STM32_GPIO_50005000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50005000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOD_LABEL               \
+				DT_ST_STM32_GPIO_50005000_LABEL
+#define DT_GPIO_STM32_GPIOD_SIZE                \
+				DT_ST_STM32_GPIO_50005000_SIZE
+#define DT_GPIO_STM32_GPIOD_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50005000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOD_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50005000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50006000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50006000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50006000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50006000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOE_LABEL               \
+				DT_ST_STM32_GPIO_50006000_LABEL
+#define DT_GPIO_STM32_GPIOE_SIZE                \
+				DT_ST_STM32_GPIO_50006000_SIZE
+#define DT_GPIO_STM32_GPIOE_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50006000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOE_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50006000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50007000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50007000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50007000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50007000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOF_LABEL               \
+				DT_ST_STM32_GPIO_50007000_LABEL
+#define DT_GPIO_STM32_GPIOF_SIZE                \
+				DT_ST_STM32_GPIO_50007000_SIZE
+#define DT_GPIO_STM32_GPIOF_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50007000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOF_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50007000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50008000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50008000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50008000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50008000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOG_LABEL               \
+				DT_ST_STM32_GPIO_50008000_LABEL
+#define DT_GPIO_STM32_GPIOG_SIZE                \
+				DT_ST_STM32_GPIO_50008000_SIZE
+#define DT_GPIO_STM32_GPIOG_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50008000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOG_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50008000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_50009000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_50009000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_50009000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_50009000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOH_LABEL               \
+				DT_ST_STM32_GPIO_50009000_LABEL
+#define DT_GPIO_STM32_GPIOH_SIZE                \
+				DT_ST_STM32_GPIO_50009000_SIZE
+#define DT_GPIO_STM32_GPIOH_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_50009000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOH_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_50009000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_5000A000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_5000A000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_5000A000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_5000A000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOI_LABEL               \
+				DT_ST_STM32_GPIO_5000A000_LABEL
+#define DT_GPIO_STM32_GPIOI_SIZE                \
+				DT_ST_STM32_GPIO_5000A000_SIZE
+#define DT_GPIO_STM32_GPIOI_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_5000A000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOI_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_5000A000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOJ_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_5000B000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_5000B000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_5000B000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_5000B000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOJ_LABEL               \
+				DT_ST_STM32_GPIO_5000B000_LABEL
+#define DT_GPIO_STM32_GPIOJ_SIZE                \
+				DT_ST_STM32_GPIO_5000B000_SIZE
+#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_5000B000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_5000B000_CLOCK_BUS
+
+#define DT_GPIO_STM32_GPIOK_BASE_ADDRESS        \
+				DT_ST_STM32_GPIO_5000C000_BASE_ADDRESS
+#define DT_GPIO_STM32_GPIOK_CLOCK_BITS_0        \
+				DT_ST_STM32_GPIO_5000C000_CLOCK_BITS_0
+#define DT_GPIO_STM32_GPIOK_CLOCK_BUS_0         \
+				DT_ST_STM32_GPIO_5000C000_CLOCK_BUS_0
+#define DT_GPIO_STM32_GPIOK_CLOCK_CONTROLLER    \
+				DT_ST_STM32_GPIO_5000C000_CLOCK_CONTROLLER
+#define DT_GPIO_STM32_GPIOK_LABEL               \
+				DT_ST_STM32_GPIO_5000C000_LABEL
+#define DT_GPIO_STM32_GPIOK_SIZE                \
+				DT_ST_STM32_GPIO_5000C000_SIZE
+#define DT_GPIO_STM32_GPIOK_CLOCK_BITS          \
+				DT_ST_STM32_GPIO_5000C000_CLOCK_BITS
+#define DT_GPIO_STM32_GPIOK_CLOCK_BUS           \
+				DT_ST_STM32_GPIO_5000C000_CLOCK_BUS
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32mp1/soc.h b/soc/arm/st_stm32/stm32mp1/soc.h
index 6e38119b9ec13..7ac56bcfabe5b 100644
--- a/soc/arm/st_stm32/stm32mp1/soc.h
+++ b/soc/arm/st_stm32/stm32mp1/soc.h
@@ -31,6 +31,17 @@
 #include <stm32mp1xx_ll_exti.h>
 #endif
 
+#ifdef CONFIG_GPIO_STM32
+#include <stm32mp1xx_ll_gpio.h>
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32mp1xx_ll_utils.h>
+#include <stm32mp1xx_ll_bus.h>
+#include <stm32mp1xx_ll_rcc.h>
+#include <stm32mp1xx_ll_system.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32MP1SOC_H_ */