diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 96619ce8bc25d..a344547909e57 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -18,6 +18,10 @@ config CPU_ATOM select CPU_HAS_FPU select ARCH_HAS_STACK_PROTECTION if X86_MMU select ARCH_HAS_USERSPACE if X86_MMU + select X86_CPU_HAS_MMX + select X86_CPU_HAS_SSE + select X86_CPU_HAS_SSE2 + select X86_CPU_HAS_SSE3 help This option signifies the use of a CPU from the Atom family. @@ -33,6 +37,14 @@ config CPU_APOLLO_LAKE select CPU_HAS_FPU select ARCH_HAS_STACK_PROTECTION if X86_MMU select ARCH_HAS_USERSPACE if X86_MMU + select X86_MMU + select X86_CPU_HAS_MMX + select X86_CPU_HAS_SSE + select X86_CPU_HAS_SSE2 + select X86_CPU_HAS_SSE3 + select X86_CPU_HAS_SSSE3 + select X86_CPU_HAS_SSE41 + select X86_CPU_HAS_SSE42 help This option signifies the use of a CPU from the Apollo Lake family. @@ -47,6 +59,114 @@ config X86_64 select USE_SWITCH_SUPPORTED select SCHED_IPI_SUPPORTED select X86_MMU + select X86_CPU_HAS_MMX + select X86_CPU_HAS_SSE + select X86_CPU_HAS_SSE2 + select X86_MMX + select X86_SSE + select X86_SSE2 + +menu "x86 Features" + +config X86_CPU_HAS_MMX + bool + +config X86_CPU_HAS_SSE + bool + +config X86_CPU_HAS_SSE2 + bool + +config X86_CPU_HAS_SSE3 + bool + +config X86_CPU_HAS_SSSE3 + bool + +config X86_CPU_HAS_SSE41 + bool + +config X86_CPU_HAS_SSE42 + bool + +config X86_CPU_HAS_SSE4A + bool + +if FPU || X86_64 + +config X86_MMX + bool "Enable MMX Support" + depends on X86_CPU_HAS_MMX + help + This option enables MMX support, and the use of MMX registers + by threads. + +config X86_SSE + bool "Enable SSE Support" + depends on X86_CPU_HAS_SSE + help + This option enables SSE support, and the use of SSE registers + by threads. + +config X86_SSE2 + bool "Enable SSE2 Support" + depends on X86_CPU_HAS_SSE2 + select X86_SSE + help + This option enables SSE2 support. + +config X86_SSE3 + bool "Enable SSE3 Support" + depends on X86_CPU_HAS_SSE3 + select X86_SSE + help + This option enables SSE3 support. + +config X86_SSSE3 + bool "Enable SSSE3 (Supplemental SSE3) Support" + depends on X86_CPU_HAS_SSSE3 + select X86_SSE + help + This option enables Supplemental SSE3 support. + +config X86_SSE41 + bool "Enable SSE4.1 Support" + depends on X86_CPU_HAS_SSE41 + select X86_SSE + help + This option enables SSE4.1 support. + +config X86_SSE42 + bool "Enable SSE4.2 Support" + depends on X86_CPU_HAS_SSE42 + select X86_SSE + help + This option enables SSE4.2 support. + +config X86_SSE4A + bool "Enable SSE4A Support" + depends on X86_CPU_HAS_SSE4A + select X86_SSE + help + This option enables SSE4A support. + +config X86_SSE_FP_MATH + bool "Compiler-generated SSEx instructions for floating point math" + depends on X86_SSE + help + This option allows the compiler to generate SSEx instructions for + performing floating point math. This can greatly improve performance + when exactly the same operations are to be performed on multiple + data objects; however, it can also significantly reduce performance + when preemptive task switches occur because of the larger register + set that must be saved and restored. + + Disabling this option means that the compiler utilizes only the + x87 instruction set for floating point operations. + +endif # FPU || X86_64 + +endmenu config X86_KERNEL_OFFSET int "Kernel offset from beginning of RAM" diff --git a/arch/x86/core/Kconfig.ia32 b/arch/x86/core/Kconfig.ia32 index 864318a5f8f78..0fee770c46331 100644 --- a/arch/x86/core/Kconfig.ia32 +++ b/arch/x86/core/Kconfig.ia32 @@ -92,22 +92,16 @@ if CPU_HAS_FPU config SSE bool "SSE registers" depends on FPU + select X86_SSE help - This option enables the use of SSE registers by threads. + This option is deprecated. Please use CONFIG_X86_SSE instead. config SSE_FP_MATH bool "Compiler-generated SSEx instructions" - depends on SSE + depends on X86_SSE + select X86_SSE_FP_MATH help - This option allows the compiler to generate SSEx instructions for - performing floating point math. This can greatly improve performance - when exactly the same operations are to be performed on multiple - data objects; however, it can also significantly reduce performance - when preemptive task switches occur because of the larger register - set that must be saved and restored. - - Disabling this option means that the compiler utilizes only the - x87 instruction set for floating point operations. + This option is deprecated. Please use CONFIG_X86_SSE_FP_MATH instead. config EAGER_FPU_SHARING bool diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S index 2f2cbaa328daf..58ac45b447c68 100644 --- a/arch/x86/core/ia32/crt0.S +++ b/arch/x86/core/ia32/crt0.S @@ -34,7 +34,7 @@ #endif -#if defined(CONFIG_SSE) +#if defined(CONFIG_X86_SSE) GDATA(_sse_mxcsr_default_value) #endif @@ -101,7 +101,7 @@ __csSet: fninit /* set x87 FPU to its default state */ - #if defined(CONFIG_SSE) + #if defined(CONFIG_X86_SSE) /* * Permit use of SSE instructions * @@ -116,7 +116,7 @@ __csSet: ldmxcsr _sse_mxcsr_default_value /* initialize SSE control/status reg */ - #endif /* CONFIG_SSE */ + #endif /* CONFIG_X86_SSE */ #endif /* !CONFIG_FPU */ @@ -236,7 +236,7 @@ __csSet: _x86_bss_zero: /* ECX = size, EDI = starting address */ -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE /* use XMM register to clear 16 bytes at a time */ pxor %xmm0, %xmm0 /* zero out xmm0 register */ @@ -258,7 +258,7 @@ bssWords: rep stosl /* zero memory per 4 bytes */ -#else /* !CONFIG_SSE */ +#else /* !CONFIG_X86_SSE */ /* clear out BSS double words (32-bits at a time) */ @@ -267,13 +267,13 @@ bssWords: rep stosl /* zero memory per 4 bytes */ -#endif /* CONFIG_SSE */ +#endif /* CONFIG_X86_SSE */ ret #ifdef CONFIG_XIP _x86_data_copy: /* EDI = dest, ESI = source, ECX = size in 32-bit chunks */ - #ifdef CONFIG_SSE + #ifdef CONFIG_X86_SSE /* copy 16 bytes at a time using XMM until < 16 bytes remain */ movl %ecx ,%edx /* save number of quad bytes */ @@ -290,7 +290,7 @@ dataDQ: dataWords: movl %edx, %ecx /* restore # quad bytes */ andl $0x3, %ecx /* only need to copy at most 3 quad bytes */ - #endif /* CONFIG_SSE */ + #endif /* CONFIG_X86_SSE */ rep movsl /* copy data 4 bytes at a time */ @@ -298,14 +298,14 @@ dataWords: #endif /* CONFIG_XIP */ -#if defined(CONFIG_SSE) +#if defined(CONFIG_X86_SSE) /* SSE control & status register initial value */ _sse_mxcsr_default_value: .long 0x1f80 /* all SSE exceptions clear & masked */ -#endif /* CONFIG_SSE */ +#endif /* CONFIG_X86_SSE */ /* Interrupt Descriptor Table (IDT) definition */ diff --git a/arch/x86/core/ia32/float.c b/arch/x86/core/ia32/float.c index ea860aa70fc88..3f52232041928 100644 --- a/arch/x86/core/ia32/float.c +++ b/arch/x86/core/ia32/float.c @@ -145,7 +145,7 @@ static inline void z_do_sse_regs_init(void) */ static void FpCtxSave(struct k_thread *thread) { -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE if ((thread->base.user_options & K_SSE_REGS) != 0) { z_do_fp_and_sse_regs_save(&thread->arch.preempFloatReg); return; @@ -163,7 +163,7 @@ static void FpCtxSave(struct k_thread *thread) static inline void FpCtxInit(struct k_thread *thread) { z_do_fp_regs_init(); -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE if ((thread->base.user_options & K_SSE_REGS) != 0) { z_do_sse_regs_init(); } diff --git a/arch/x86/core/ia32/swap.S b/arch/x86/core/ia32/swap.S index 1fb132ab45db9..11040132f6cbb 100644 --- a/arch/x86/core/ia32/swap.S +++ b/arch/x86/core/ia32/swap.S @@ -131,18 +131,18 @@ SECTION_FUNC(TEXT, arch_swap) * switch. */ /* Save outgpoing thread context */ -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE fxsave _thread_offset_to_preempFloatReg(%edx) fninit #else fnsave _thread_offset_to_preempFloatReg(%edx) #endif /* Restore incoming thread context */ -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE fxrstor _thread_offset_to_preempFloatReg(%eax) #else frstor _thread_offset_to_preempFloatReg(%eax) -#endif /* CONFIG_SSE */ +#endif /* CONFIG_X86_SSE */ #elif defined(CONFIG_LAZY_FPU_SHARING) /* * Clear the CR0[TS] bit (in the event the current thread @@ -206,7 +206,7 @@ SECTION_FUNC(TEXT, arch_swap) je restoreContext_NoFloatSave -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE testb $K_SSE_REGS, _thread_offset_to_user_options(%ebx) je x87FloatSave @@ -221,7 +221,7 @@ SECTION_FUNC(TEXT, arch_swap) jmp floatSaveDone x87FloatSave: -#endif /* CONFIG_SSE */ +#endif /* CONFIG_X86_SSE */ /* 'fnsave' performs an implicit 'fninit' after saving state! */ @@ -245,7 +245,7 @@ restoreContext_NoFloatSave: testb $X86_THREAD_FLAG_ALL, _thread_offset_to_flags(%eax) je restoreContext_NoFloatRestore -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE testb $K_SSE_REGS, _thread_offset_to_user_options(%eax) je x87FloatRestore @@ -254,7 +254,7 @@ restoreContext_NoFloatSave: x87FloatRestore: -#endif /* CONFIG_SSE */ +#endif /* CONFIG_X86_SSE */ frstor _thread_offset_to_preempFloatReg(%eax) diff --git a/arch/x86/ia32.cmake b/arch/x86/ia32.cmake index 1f8134b872b4d..6f7182154562a 100644 --- a/arch/x86/ia32.cmake +++ b/arch/x86/ia32.cmake @@ -21,7 +21,60 @@ if(CMAKE_C_COMPILER_ID STREQUAL "Clang") ) endif() -zephyr_cc_option_ifndef(CONFIG_SSE_FP_MATH -mno-sse) +if(CONFIG_X86_MMX) + zephyr_cc_option(-mmmx) +else() + zephyr_cc_option(-mno-mmx) +endif() + +if(CONFIG_X86_SSE) + zephyr_cc_option(-msse) + + if(CONFIG_X86_SSE_FP_MATH) + zephyr_cc_option(-mfpmath=sse) + else() + zephyr_cc_option(-mfpmath=387) + endif() + + if(CONFIG_X86_SSE2) + zephyr_cc_option(-msse2) + else() + zephyr_cc_option(-mno-sse2) + endif() + + if(CONFIG_X86_SSE3) + zephyr_cc_option(-msse3) + else() + zephyr_cc_option(-mno-sse3) + endif() + + if(CONFIG_X86_SSSE3) + zephyr_cc_option(-mssse3) + else() + zephyr_cc_option(-mno-ssse3) + endif() + + if(CONFIG_X86_SSE41) + zephyr_cc_option(-msse4.1) + else() + zephyr_cc_option(-mno-sse4.1) + endif() + + if(CONFIG_X86_SSE42) + zephyr_cc_option(-msse4.2) + else() + zephyr_cc_option(-mno-sse4.2) + endif() + + if(CONFIG_X86_SSE4A) + zephyr_cc_option(-msse4a) + else() + zephyr_cc_option(-mno-sse4a) + endif() + +else() + zephyr_cc_option(-mno-sse) +endif() if(CMAKE_VERBOSE_MAKEFILE) set(GENIDT_EXTRA_ARGS --verbose) diff --git a/arch/x86/include/ia32/kernel_arch_data.h b/arch/x86/include/ia32/kernel_arch_data.h index 49dc1981fe9c5..449578588c022 100644 --- a/arch/x86/include/ia32/kernel_arch_data.h +++ b/arch/x86/include/ia32/kernel_arch_data.h @@ -44,7 +44,7 @@ #define _THREAD_WRAPPER_REQUIRED #endif -#if defined(CONFIG_LAZY_FPU_SHARING) && defined(CONFIG_SSE) +#if defined(CONFIG_LAZY_FPU_SHARING) && defined(CONFIG_X86_SSE) #define _FP_USER_MASK (K_FP_REGS | K_SSE_REGS) #elif defined(CONFIG_LAZY_FPU_SHARING) #define _FP_USER_MASK (K_FP_REGS) diff --git a/arch/x86/intel64.cmake b/arch/x86/intel64.cmake index a2a9f73b88922..fcc075addc20d 100644 --- a/arch/x86/intel64.cmake +++ b/arch/x86/intel64.cmake @@ -8,4 +8,40 @@ set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf64-x86-64") get_property(OUTPUT_ARCH GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH) get_property(OUTPUT_FORMAT GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT) +if(CONFIG_X86_SSE) + # x86-64 by default has SSE and SSE2 + # so no need to add compiler flags for them. + + if(CONFIG_X86_SSE3) + zephyr_cc_option(-msse3) + else() + zephyr_cc_option(-mno-sse3) + endif() + + if(CONFIG_X86_SSSE3) + zephyr_cc_option(-mssse3) + else() + zephyr_cc_option(-mno-ssse3) + endif() + + if(CONFIG_X86_SSE41) + zephyr_cc_option(-msse4.1) + else() + zephyr_cc_option(-mno-sse4.1) + endif() + + if(CONFIG_X86_SSE42) + zephyr_cc_option(-msse4.2) + else() + zephyr_cc_option(-mno-sse4.2) + endif() + + if(CONFIG_X86_SSE4A) + zephyr_cc_option(-msse4a) + else() + zephyr_cc_option(-mno-sse4a) + endif() + +endif() + add_subdirectory(core) diff --git a/doc/reference/kernel/other/float.rst b/doc/reference/kernel/other/float.rst index 7043bfb3e4d44..201732deb3f5a 100644 --- a/doc/reference/kernel/other/float.rst +++ b/doc/reference/kernel/other/float.rst @@ -303,8 +303,8 @@ Also, ensure that any thread that uses the floating point registers has sufficient added stack space for saving floating point register values during context switches, as described above. -Use the :option:`CONFIG_SSE` configuration option to enable support for -SSEx instructions (x86 only). +For x86, use the :option:`CONFIG_X86_SSE` configuration option to enable +support for SSEx instructions. API Reference ************* diff --git a/include/arch/x86/ia32/thread.h b/include/arch/x86/ia32/thread.h index 756202a0b2279..937f7c958c06f 100644 --- a/include/arch/x86/ia32/thread.h +++ b/include/arch/x86/ia32/thread.h @@ -27,7 +27,7 @@ * cases a 4 byte boundary is sufficient. */ #if defined(CONFIG_EAGER_FPU_SHARING) || defined(CONFIG_LAZY_FPU_SHARING) -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE #define FP_REG_SET_ALIGN 16 #else #define FP_REG_SET_ALIGN 4 @@ -82,7 +82,7 @@ typedef struct _callee_saved _callee_saved_t; * The macros CONFIG_{LAZY|EAGER}_FPU_SHARING shall be set to indicate that the * saving/restoring of the traditional x87 floating point (and MMX) registers * are supported by the kernel's context swapping code. The macro - * CONFIG_SSE shall _also_ be set if saving/restoring of the XMM + * CONFIG_X86_SSE shall _also_ be set if saving/restoring of the XMM * registers is also supported in the kernel's context swapping code. */ @@ -120,7 +120,7 @@ typedef struct s_FpRegSet { /* # of bytes: name of register */ tFpReg fpReg[8]; /* 80 : ST0 -> ST7 */ } tFpRegSet __aligned(FP_REG_SET_ALIGN); -#ifdef CONFIG_SSE +#ifdef CONFIG_X86_SSE /* definition of a single x87 (floating point / MMX) register */ @@ -168,12 +168,12 @@ typedef struct s_FpRegSetEx /* # of bytes: name of register */ unsigned char rsrvd3[176]; /* 176 : reserved */ } tFpRegSetEx __aligned(FP_REG_SET_ALIGN); -#else /* CONFIG_SSE == 0 */ +#else /* CONFIG_X86_SSE == 0 */ typedef struct s_FpRegSetEx { } tFpRegSetEx; -#endif /* CONFIG_SSE == 0 */ +#endif /* CONFIG_X86_SSE == 0 */ #else /* !CONFIG_LAZY_FPU_SHARING && !CONFIG_EAGER_FPU_SHARING */ diff --git a/include/kernel.h b/include/kernel.h index b576cd082267a..2856f17c97fb7 100644 --- a/include/kernel.h +++ b/include/kernel.h @@ -236,7 +236,7 @@ extern void k_thread_foreach_unlocked( #ifdef CONFIG_X86 /* x86 Bitmask definitions for threads user options */ -#if defined(CONFIG_FPU_SHARING) && defined(CONFIG_SSE) +#if defined(CONFIG_FPU_SHARING) && defined(CONFIG_X86_SSE) /* thread uses SSEx (and also FP) registers */ #define K_SSE_REGS (BIT(7)) #endif diff --git a/soc/x86/ia32/Kconfig.soc b/soc/x86/ia32/Kconfig.soc index 8b00c5bf3e58b..75c86855a0750 100644 --- a/soc/x86/ia32/Kconfig.soc +++ b/soc/x86/ia32/Kconfig.soc @@ -4,4 +4,6 @@ config SOC_IA32 bool "Generic IA32 SoC" select X86 select CPU_MINUTEIA + select X86_CPU_HAS_MMX + select X86_CPU_HAS_SSE select ARCH_HAS_RESERVED_PAGE_FRAMES if SRAM_BASE_ADDRESS = 0 diff --git a/tests/benchmarks/app_kernel/prj_fp.conf b/tests/benchmarks/app_kernel/prj_fp.conf index c7f1ff4230593..215cf57a3da4e 100644 --- a/tests/benchmarks/app_kernel/prj_fp.conf +++ b/tests/benchmarks/app_kernel/prj_fp.conf @@ -4,9 +4,7 @@ CONFIG_STDOUT_CONSOLE=y CONFIG_MAIN_THREAD_PRIORITY=6 CONFIG_FPU=y -CONFIG_SSE=y CONFIG_FPU_SHARING=y -CONFIG_SSE_FP_MATH=y # eliminate timer interrupts during the benchmark CONFIG_SYS_CLOCK_TICKS_PER_SEC=1 @@ -17,3 +15,5 @@ CONFIG_FORCE_NO_ASSERT=y # Disable HW Stack Protection (see #28664) CONFIG_TEST_HW_STACK_PROTECTION=n CONFIG_HW_STACK_PROTECTION=n + +CONFIG_MP_NUM_CPUS=1 diff --git a/tests/benchmarks/app_kernel/testcase.yaml b/tests/benchmarks/app_kernel/testcase.yaml index 8860913f4be63..2f1ce40f0fcfd 100644 --- a/tests/benchmarks/app_kernel/testcase.yaml +++ b/tests/benchmarks/app_kernel/testcase.yaml @@ -5,6 +5,39 @@ tests: min_ram: 32 tags: benchmark timeout: 300 + benchmark.kernel.application.fp.arm: + extra_args: CONF_FILE=prj_fp.conf + arch_allow: arm + filter: CONFIG_ARMV7_M_ARMV8_M_FP + min_flash: 34 + min_ram: 32 + tags: benchmark + slow: true + timeout: 300 + benchmark.kernel.application.fp.x86.fpu: + extra_args: CONF_FILE=prj_fp.conf + extra_configs: + - CONFIG_X86_SSE=y + - CONFIG_X86_SSE_FP_MATH=n + arch_allow: x86 + filter: CONFIG_CPU_HAS_FPU + min_flash: 34 + min_ram: 32 + tags: benchmark + slow: true + timeout: 300 + benchmark.kernel.application.fp.x86.sse: + extra_args: CONF_FILE=prj_fp.conf + extra_configs: + - CONFIG_X86_SSE=y + - CONFIG_X86_SSE_FP_MATH=y + arch_allow: x86 + filter: CONFIG_CPU_HAS_FPU + min_flash: 34 + min_ram: 32 + tags: benchmark + slow: true + timeout: 300 benchmark.kernel.application.posix: arch_allow: posix min_ram: 32 diff --git a/tests/kernel/fpu_sharing/float_disable/prj_x86.conf b/tests/kernel/fpu_sharing/float_disable/prj_x86.conf index 1bc68cde9ae8d..ed987a5581e50 100644 --- a/tests/kernel/fpu_sharing/float_disable/prj_x86.conf +++ b/tests/kernel/fpu_sharing/float_disable/prj_x86.conf @@ -2,5 +2,4 @@ CONFIG_ZTEST=y CONFIG_TEST_USERSPACE=y CONFIG_FPU=y CONFIG_FPU_SHARING=y -CONFIG_SSE=y -CONFIG_SSE_FP_MATH=y +CONFIG_X86_SSE=y diff --git a/tests/kernel/fpu_sharing/float_disable/testcase.yaml b/tests/kernel/fpu_sharing/float_disable/testcase.yaml index 19af97ab822f2..3b2a08ea7faad 100644 --- a/tests/kernel/fpu_sharing/float_disable/testcase.yaml +++ b/tests/kernel/fpu_sharing/float_disable/testcase.yaml @@ -17,7 +17,15 @@ tests: filter: CONFIG_CPU_HAS_FPU arch_allow: sparc tags: kernel userspace - kernel.fpu_sharing.float_disable.x86: + kernel.fpu_sharing.float_disable.x86.fpu: extra_args: CONF_FILE=prj_x86.conf + extra_configs: + - CONFIG_X86_SSE_FP_MATH=n + platform_allow: qemu_x86 + tags: kernel userspace + kernel.fpu_sharing.float_disable.x86.sse: + extra_args: CONF_FILE=prj_x86.conf + extra_configs: + - CONFIG_X86_SSE_FP_MATH=y platform_allow: qemu_x86 tags: kernel userspace diff --git a/tests/kernel/fpu_sharing/generic/prj_x86.conf b/tests/kernel/fpu_sharing/generic/prj_x86.conf index a341e4a17f8a6..20c8ab2466905 100644 --- a/tests/kernel/fpu_sharing/generic/prj_x86.conf +++ b/tests/kernel/fpu_sharing/generic/prj_x86.conf @@ -1,6 +1,5 @@ CONFIG_ZTEST=y CONFIG_FPU=y -CONFIG_SSE=y +CONFIG_X86_SSE=y CONFIG_FPU_SHARING=y -CONFIG_SSE_FP_MATH=y CONFIG_STDOUT_CONSOLE=y diff --git a/tests/kernel/fpu_sharing/generic/src/main.c b/tests/kernel/fpu_sharing/generic/src/main.c index 2cd3d98a4378e..3d420aa27e58f 100644 --- a/tests/kernel/fpu_sharing/generic/src/main.c +++ b/tests/kernel/fpu_sharing/generic/src/main.c @@ -17,7 +17,7 @@ #error Rebuild with the FPU_SHARING config option enabled #endif -#if defined(CONFIG_X86) && !defined(CONFIG_SSE) +#if defined(CONFIG_X86) && !defined(CONFIG_X86_SSE) #error Rebuild with the SSE config option enabled #endif diff --git a/tests/kernel/fpu_sharing/generic/testcase.yaml b/tests/kernel/fpu_sharing/generic/testcase.yaml index f3eff516da8e6..d900614dc7beb 100644 --- a/tests/kernel/fpu_sharing/generic/testcase.yaml +++ b/tests/kernel/fpu_sharing/generic/testcase.yaml @@ -33,8 +33,18 @@ tests: arch_allow: sparc tags: kernel timeout: 600 - kernel.fpu_sharing.generic.x86: + kernel.fpu_sharing.generic.x86.fpu: extra_args: CONF_FILE=prj_x86.conf + extra_configs: + - CONFIG_X86_SSE_FP_MATH=n + platform_allow: qemu_x86 + slow: true + tags: kernel + timeout: 600 + kernel.fpu_sharing.generic.x86.sse: + extra_args: CONF_FILE=prj_x86.conf + extra_configs: + - CONFIG_X86_SSE_FP_MATH=y platform_allow: qemu_x86 slow: true tags: kernel