From 27580641d29b82aea296c315eb833d5001445279 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 9 Feb 2021 13:26:40 -0800 Subject: [PATCH 1/6] x86: add kconfig CONFIG_X86_PC_COMPATIBLE This is an hidden option to indicate we are building for PC-compatible devices (where there are BIOS, ACPI, etc. which are standard on such devices). Signed-off-by: Daniel Leung --- arch/x86/Kconfig | 10 ++++++++++ arch/x86/core/x86_mmu.c | 17 ++++++++++------- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a344547909e57..e9cffa0609c49 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -215,6 +215,7 @@ endchoice config ACPI bool "ACPI (Advanced Configuration and Power Interface) support" + depends on X86_PC_COMPATIBLE select ARCH_MAPS_ALL_RAM help Allow retrieval of platform configuration at runtime. @@ -230,6 +231,14 @@ config PCIE_MMIO_CFG config KERNEL_VM_SIZE default 0xC0000000 if ACPI +config X86_PC_COMPATIBLE + bool + default y + select ARCH_HAS_RESERVED_PAGE_FRAMES + help + Hidden option to signal building for PC-compatible platforms + with BIOS, ACPI, etc. + config X86_MEMMAP_ENTRIES int "Number of memory map entries" range 1 256 @@ -240,6 +249,7 @@ config X86_MEMMAP_ENTRIES config MULTIBOOT bool "Generate multiboot header" + depends on X86_PC_COMPATIBLE default y help Embed a multiboot header in the output executable. This is used diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index b0b4cbba14d73..45acc94d2dfbf 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -1723,16 +1723,19 @@ static void mark_addr_page_reserved(uintptr_t addr, size_t len) } } -/* Selected on PC-like targets at the SOC level. - * - * Best is to do some E820 or similar enumeration to specifically identify - * all page frames which are reserved by the hardware or firmware. - * - * For now, just reserve everything in the first megabyte of physical memory. - */ void arch_reserved_pages_update(void) { +#ifdef CONFIG_X86_PC_COMPATIBLE + /* + * Best is to do some E820 or similar enumeration to specifically + * identify all page frames which are reserved by the hardware or + * firmware. Or use x86_memmap[] with Multiboot if available. + * + * But still, reserve everything in the first megabyte of physical + * memory on PC-compatible platforms. + */ mark_addr_page_reserved(0, MB(1)); +#endif /* CONFIG_X86_PC_COMPATIBLE */ for (int i = 0; i < CONFIG_X86_MEMMAP_ENTRIES; i++) { struct x86_memmap_entry *entry = &x86_memmap[i]; From a9fc5bdb99e49ef64b1298ff1b4cb314f0cf4919 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 9 Feb 2021 13:42:46 -0800 Subject: [PATCH 2/6] x86: add kconfig CONFIG_X86_MEMMAP This adds a new kconfig to enable the use of memory map. This map can be populated automatically if CONFIG_MULTIBOOT_MEMMAP=y or can be manually defined via x86_memmap[]. Signed-off-by: Daniel Leung --- arch/x86/Kconfig | 12 ++++++++++++ arch/x86/core/CMakeLists.txt | 3 ++- arch/x86/core/x86_mmu.c | 2 ++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e9cffa0609c49..7e3dc1a9c4a25 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -239,8 +239,19 @@ config X86_PC_COMPATIBLE Hidden option to signal building for PC-compatible platforms with BIOS, ACPI, etc. +config X86_MEMMAP + bool "Use memory map" + select ARCH_HAS_RESERVED_PAGE_FRAMES + help + Enable the use of memory map to identify regions of memory. + + The memory map can be populated via Multiboot + (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or + can be manually defined via x86_memmap[]. + config X86_MEMMAP_ENTRIES int "Number of memory map entries" + depends on X86_MEMMAP range 1 256 default 1 if !MULTIBOOT_MEMMAP default 64 if MULTIBOOT_MEMMAP @@ -270,6 +281,7 @@ config MULTIBOOT_INFO config MULTIBOOT_MEMMAP bool "Use multiboot memory map if provided" select MULTIBOOT_INFO + select X86_MEMMAP help Use the multiboot memory map if the loader provides one. diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt index 0711cefabb85c..e91bf735c75cf 100644 --- a/arch/x86/core/CMakeLists.txt +++ b/arch/x86/core/CMakeLists.txt @@ -9,11 +9,12 @@ if (CONFIG_COVERAGE) endif () zephyr_library_sources(cpuhalt.c) -zephyr_library_sources(memmap.c) zephyr_library_sources(prep_c.c) zephyr_library_sources(fatal.c) zephyr_library_sources(spec_ctrl.c) +zephyr_library_sources_ifdef(CONFIG_X86_MEMMAP memmap.c) + zephyr_library_sources_ifdef(CONFIG_PCIE pcie.c) zephyr_library_sources_ifdef(CONFIG_REBOOT_RST_CNT reboot_rst_cnt.c) zephyr_library_sources_ifdef(CONFIG_MULTIBOOT multiboot.c) diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index 45acc94d2dfbf..efad000c86a16 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -1737,6 +1737,7 @@ void arch_reserved_pages_update(void) mark_addr_page_reserved(0, MB(1)); #endif /* CONFIG_X86_PC_COMPATIBLE */ +#ifdef CONFIG_X86_MEMMAP for (int i = 0; i < CONFIG_X86_MEMMAP_ENTRIES; i++) { struct x86_memmap_entry *entry = &x86_memmap[i]; @@ -1758,6 +1759,7 @@ void arch_reserved_pages_update(void) mark_addr_page_reserved(entry->base, entry->length); } +#endif /* CONFIG_X86_MEMMAP */ } #endif /* CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES */ From 5f572701ab3945fc612897e5ed0db344d230dbda Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 17 Feb 2021 15:57:11 -0800 Subject: [PATCH 3/6] boards: x86/qemu: enable CPU flags for MMX/SSE Tells QEMU to enable CPU flags corresponding to MMX/SSE kconfigs. Signed-off-by: Daniel Leung --- boards/x86/qemu_x86/board.cmake | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/boards/x86/qemu_x86/board.cmake b/boards/x86/qemu_x86/board.cmake index 6083d256e85d0..ca0bf054fc41f 100644 --- a/boards/x86/qemu_x86/board.cmake +++ b/boards/x86/qemu_x86/board.cmake @@ -26,9 +26,36 @@ else() math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") endif() +set(QEMU_CPU_FLAGS "") +if(CONFIG_X86_MMX) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx") + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext") +endif() +if(CONFIG_X86_SSE) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse") +endif() +if(CONFIG_X86_SSE2) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2") +endif() +if(CONFIG_X86_SSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni") +endif() +if(CONFIG_X86_SSSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3") +endif() +if(CONFIG_X86_SSE41) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1") +endif() +if(CONFIG_X86_SSE42) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2") +endif() +if(CONFIG_X86_SSE4A) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a") +endif() + set(QEMU_FLAGS_${ARCH} -m ${QEMU_MEMORY_SIZE_MB} - -cpu ${QEMU_CPU_TYPE_${ARCH}} + -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} -device isa-debug-exit,iobase=0xf4,iosize=0x04 ${REBOOT_FLAG} -nographic From 09a44bfc6c2982c85ff9a28752fbc303b37e9d68 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Mon, 8 Feb 2021 14:25:47 -0800 Subject: [PATCH 4/6] soc: x86: add Lakemont SoC This adds a very basic SoC configuration for Intel Lakemont SoC. Signed-off-by: Daniel Leung --- arch/x86/Kconfig | 13 +++++++++ dts/bindings/cpu/intel,lakemont.yml | 8 ++++++ dts/x86/lakemont.dtsi | 42 +++++++++++++++++++++++++++++ soc/x86/lakemont/CMakeLists.txt | 5 ++++ soc/x86/lakemont/Kconfig.defconfig | 23 ++++++++++++++++ soc/x86/lakemont/Kconfig.soc | 14 ++++++++++ soc/x86/lakemont/linker.ld | 8 ++++++ soc/x86/lakemont/soc.h | 10 +++++++ 8 files changed, 123 insertions(+) create mode 100644 dts/bindings/cpu/intel,lakemont.yml create mode 100644 dts/x86/lakemont.dtsi create mode 100644 soc/x86/lakemont/CMakeLists.txt create mode 100644 soc/x86/lakemont/Kconfig.defconfig create mode 100644 soc/x86/lakemont/Kconfig.soc create mode 100644 soc/x86/lakemont/linker.ld create mode 100644 soc/x86/lakemont/soc.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 7e3dc1a9c4a25..832ad14e200f1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -48,6 +48,19 @@ config CPU_APOLLO_LAKE help This option signifies the use of a CPU from the Apollo Lake family. +config CPU_LAKEMONT + bool + select CPU_HAS_FPU + select ARCH_HAS_STACK_PROTECTION if X86_MMU + select ARCH_HAS_USERSPACE if X86_MMU + select X86_CPU_HAS_MMX + select X86_CPU_HAS_SSE + select X86_CPU_HAS_SSE2 + select X86_CPU_HAS_SSE3 + select X86_CPU_HAS_SSSE3 + help + This option signifies the use of a CPU from the Lakemont family. + # # Configuration common to both IA32 and Intel64 sub-architectures. # diff --git a/dts/bindings/cpu/intel,lakemont.yml b/dts/bindings/cpu/intel,lakemont.yml new file mode 100644 index 0000000000000..04904e4c77339 --- /dev/null +++ b/dts/bindings/cpu/intel,lakemont.yml @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Intel Corp. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel Lakemont CPU + +compatible: "intel,lakemont" + +include: cpu.yaml diff --git a/dts/x86/lakemont.dtsi b/dts/x86/lakemont.dtsi new file mode 100644 index 0000000000000..708944b986c61 --- /dev/null +++ b/dts/x86/lakemont.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,lakemont"; + d-cache-line-size = <64>; + reg = <0>; + }; + + }; + + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + reg = <0xfec00000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + /* + * Platforms with Lakemont SoC can have different hardware + * configurations. So RAM and peripherals need to be + * defined in the board configuration's DTS. + */ + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + }; +}; diff --git a/soc/x86/lakemont/CMakeLists.txt b/soc/x86/lakemont/CMakeLists.txt new file mode 100644 index 0000000000000..6f44c89f7ad6f --- /dev/null +++ b/soc/x86/lakemont/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_cc_option(-march=pentium) diff --git a/soc/x86/lakemont/Kconfig.defconfig b/soc/x86/lakemont/Kconfig.defconfig new file mode 100644 index 0000000000000..3e21fbe3e0047 --- /dev/null +++ b/soc/x86/lakemont/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2021 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LAKEMONT + +config SOC + default "lakemont" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Can be enabled once UART is defined in board +# configuration. +config X86_VERY_EARLY_CONSOLE + default n + +# Target platforms are usually not PC-compatible +# (e.g. without BIOS, ACPI, etc.). +config X86_PC_COMPATIBLE + default n + +endif diff --git a/soc/x86/lakemont/Kconfig.soc b/soc/x86/lakemont/Kconfig.soc new file mode 100644 index 0000000000000..9a62a2d1e44f4 --- /dev/null +++ b/soc/x86/lakemont/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LAKEMONT + bool "Intel Lakemont SoC" + select X86 + select CPU_LAKEMONT + select X86_MMU if FPU + select X86_SSE if FPU + select X86_SSE2 if FPU + select X86_SSE3 if FPU + select X86_SSSE3 if FPU + select ARCH_HAS_USERSPACE diff --git a/soc/x86/lakemont/linker.ld b/soc/x86/lakemont/linker.ld new file mode 100644 index 0000000000000..779efe1ae550c --- /dev/null +++ b/soc/x86/lakemont/linker.ld @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2011-2014, Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include diff --git a/soc/x86/lakemont/soc.h b/soc/x86/lakemont/soc.h new file mode 100644 index 0000000000000..112dd16702bed --- /dev/null +++ b/soc/x86/lakemont/soc.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2021 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SOC_H_ +#define __SOC_H_ + +#endif /* __SOC_H_ */ From 9f7aaa8dc0eaf022ce22ad943206e06232072774 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 17 Feb 2021 16:09:20 -0800 Subject: [PATCH 5/6] board: x86: add new board qemu_x86_lakemont This adds a new board qemu_x86_lakemont for testing the Lakemont SoC configuration. Signed-off-by: Daniel Leung --- boards/x86/qemu_x86/Kconfig.board | 7 +++ boards/x86/qemu_x86/Kconfig.defconfig | 21 +++++++ boards/x86/qemu_x86/qemu_x86_lakemont.dts | 62 +++++++++++++++++++ boards/x86/qemu_x86/qemu_x86_lakemont.yaml | 13 ++++ .../x86/qemu_x86/qemu_x86_lakemont_defconfig | 19 ++++++ soc/x86/lakemont/soc.h | 5 ++ 6 files changed, 127 insertions(+) create mode 100644 boards/x86/qemu_x86/qemu_x86_lakemont.dts create mode 100644 boards/x86/qemu_x86/qemu_x86_lakemont.yaml create mode 100644 boards/x86/qemu_x86/qemu_x86_lakemont_defconfig diff --git a/boards/x86/qemu_x86/Kconfig.board b/boards/x86/qemu_x86/Kconfig.board index f00f2c0f9342a..2c3739b3397d3 100644 --- a/boards/x86/qemu_x86/Kconfig.board +++ b/boards/x86/qemu_x86/Kconfig.board @@ -13,3 +13,10 @@ config BOARD_QEMU_X86_64 select QEMU_TARGET select X86_64 select HAS_COVERAGE_SUPPORT + +config BOARD_QEMU_X86_LAKEMONT + bool "QEMU x86 (Lakemont)" + depends on SOC_LAKEMONT + select QEMU_TARGET + select CPU_HAS_FPU + select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/qemu_x86/Kconfig.defconfig b/boards/x86/qemu_x86/Kconfig.defconfig index b34ca5cff9ff2..56abe634b3e1b 100644 --- a/boards/x86/qemu_x86/Kconfig.defconfig +++ b/boards/x86/qemu_x86/Kconfig.defconfig @@ -35,3 +35,24 @@ config KERNEL_VM_SIZE default 0x10000000 if ACPI endif # BOARD_QEMU_X86_64 + +if BOARD_QEMU_X86_LAKEMONT + +config BUILD_OUTPUT_BIN + default n + +config BOARD + default "qemu_x86_lakemont" + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +endif # BOARD_QEMU_X86_LAKEMONT diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.dts b/boards/x86/qemu_x86/qemu_x86_lakemont.dts new file mode 100644 index 0000000000000..373e33f7b74be --- /dev/null +++ b/boards/x86/qemu_x86/qemu_x86_lakemont.dts @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#ifndef DT_DRAM_BASE +#define DT_DRAM_BASE 0 +#endif +#ifndef DT_DRAM_SIZE +#define DT_DRAM_SIZE DT_SIZE_K(4096) +#endif + +#include + +/ { + model = "QEMU X86 (Lakemont) emulator"; + compatible = "qemu,x86_lakemont_emulator"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &dram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + dram0: memory@0 { + device_type = "memory"; + reg = ; + }; + + soc { + uart0: uart@3f8 { + compatible = "ns16550"; + reg = <0x000003f8 0x100>; + label = "UART_0"; + clock-frequency = <1843200>; + interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; + interrupt-parent = <&intc>; + current-speed = <115200>; + + status = "okay"; + }; + + hpet: hpet@fed00000 { + label = "HPET"; + compatible = "intel,hpet"; + reg = <0xfed00000 0x400>; + interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; + interrupt-parent = <&intc>; + + status = "okay"; + }; + }; +}; diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.yaml b/boards/x86/qemu_x86/qemu_x86_lakemont.yaml new file mode 100644 index 0000000000000..94dbcc103bd67 --- /dev/null +++ b/boards/x86/qemu_x86/qemu_x86_lakemont.yaml @@ -0,0 +1,13 @@ +identifier: qemu_x86_lakemont +name: QEMU Emulation for X86 (Lakemont) +type: qemu +simulation: qemu +arch: x86 +toolchain: + - zephyr + - xtools + - llvm +testing: + default: true + only_tags: + - kernel diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig b/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig new file mode 100644 index 0000000000000..423798f2b08ce --- /dev/null +++ b/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_LAKEMONT=y +CONFIG_BOARD_QEMU_X86_LAKEMONT=y +CONFIG_HPET_TIMER=y +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 +CONFIG_TEST_RANDOM_GENERATOR=y +CONFIG_X86_MMU=y +CONFIG_DEBUG_INFO=y +CONFIG_SCHED_SCALABLE=y +CONFIG_WAITQ_SCALABLE=y +CONFIG_X86_VERY_EARLY_CONSOLE=y +CONFIG_QEMU_ICOUNT_SHIFT=5 diff --git a/soc/x86/lakemont/soc.h b/soc/x86/lakemont/soc.h index 112dd16702bed..7d3478c7112a7 100644 --- a/soc/x86/lakemont/soc.h +++ b/soc/x86/lakemont/soc.h @@ -7,4 +7,9 @@ #ifndef __SOC_H_ #define __SOC_H_ +#ifdef CONFIG_BOARD_QEMU_X86_LAKEMONT +/* QEMU uses IO port based UART */ +#define UART_NS16550_ACCESS_IOPORT 0x3f8 +#endif + #endif /* __SOC_H_ */ From 0cd1f8c1ba36df7cdeac0c7bf8f0569743453c82 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Wed, 17 Feb 2021 16:21:53 -0800 Subject: [PATCH 6/6] tests: fpu_sharing: allow board qemu_x86_lakemont This adds qemu_x86_lakemont to the platform allow list for the FPU sharing tests. Since Lakemont supports SSE3 and SSSE3, it is better to test them also. Signed-off-by: Daniel Leung --- tests/kernel/fpu_sharing/float_disable/testcase.yaml | 4 ++-- tests/kernel/fpu_sharing/generic/testcase.yaml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/kernel/fpu_sharing/float_disable/testcase.yaml b/tests/kernel/fpu_sharing/float_disable/testcase.yaml index 3b2a08ea7faad..68d4ba90ce55e 100644 --- a/tests/kernel/fpu_sharing/float_disable/testcase.yaml +++ b/tests/kernel/fpu_sharing/float_disable/testcase.yaml @@ -21,11 +21,11 @@ tests: extra_args: CONF_FILE=prj_x86.conf extra_configs: - CONFIG_X86_SSE_FP_MATH=n - platform_allow: qemu_x86 + platform_allow: qemu_x86 qemu_x86_lakemont tags: kernel userspace kernel.fpu_sharing.float_disable.x86.sse: extra_args: CONF_FILE=prj_x86.conf extra_configs: - CONFIG_X86_SSE_FP_MATH=y - platform_allow: qemu_x86 + platform_allow: qemu_x86 qemu_x86_lakemont tags: kernel userspace diff --git a/tests/kernel/fpu_sharing/generic/testcase.yaml b/tests/kernel/fpu_sharing/generic/testcase.yaml index d900614dc7beb..39d87df0fcb5c 100644 --- a/tests/kernel/fpu_sharing/generic/testcase.yaml +++ b/tests/kernel/fpu_sharing/generic/testcase.yaml @@ -37,7 +37,7 @@ tests: extra_args: CONF_FILE=prj_x86.conf extra_configs: - CONFIG_X86_SSE_FP_MATH=n - platform_allow: qemu_x86 + platform_allow: qemu_x86 qemu_x86_lakemont slow: true tags: kernel timeout: 600 @@ -45,7 +45,7 @@ tests: extra_args: CONF_FILE=prj_x86.conf extra_configs: - CONFIG_X86_SSE_FP_MATH=y - platform_allow: qemu_x86 + platform_allow: qemu_x86 qemu_x86_lakemont slow: true tags: kernel timeout: 600