From 2c73fb5ff89b94046b53cf518d48e5e734d23b7b Mon Sep 17 00:00:00 2001 From: Jeremy Wood Date: Thu, 27 May 2021 16:58:26 -0700 Subject: [PATCH 1/4] dts: arm: st: Add can, can1 to stm32h7.dtsi. * Add can, can1 to stm32h7.dtsi. Signed-off-by: Jeremy Wood --- dts/arm/st/h7/stm32h7.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 2fb09e1336604..0177da6dc5d2b 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -444,6 +444,31 @@ label = "SPI_6"; }; + can { + compatible = "bosch,m-can-base"; + #address-cells = <1>; + #size-cells = <1>; + std-filter-elements = <28>; + ext-filter-elements = <8>; + rx-fifo0-elements = <3>; + rx-fifo1-elements = <3>; + rx-buffer-elements = <0>; + tx-buffer-elements = <3>; + + can1: can@4000a000 { + compatible = "st,stm32-fdcan"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000a000 0x400>, <0x4000ac00 0xd48>; + reg-names = "m_can", "message_ram"; + interrupts = <19 0>, <21 0>, <63 0>; + interrupt-names = "LINE_0", "LINE_1", "CALIB"; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; + status = "disabled"; + label = "CAN_1"; + }; + }; + timers1: timers@40010000 { compatible = "st,stm32-timers"; reg = <0x40010000 0x400>; From b020e42d2cb8b8c1bb438e8ffbbc3e13e63f6a85 Mon Sep 17 00:00:00 2001 From: Jeremy Wood Date: Thu, 27 May 2021 17:01:31 -0700 Subject: [PATCH 2/4] boards: arm: Add can1 to nucleo_h743/753. * Add can1 config to nucleo_h743/753. Signed-off-by: Jeremy Wood --- boards/arm/nucleo_h743zi/nucleo_h743zi.dts | 12 ++++++++++++ boards/arm/nucleo_h753zi/nucleo_h753zi.dts | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts index 0b03c2e34ee0b..39fbd5547f8fc 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts @@ -20,6 +20,7 @@ zephyr,flash = &flash0; zephyr,dtcm = &dtcm; zephyr,code-partition = &slot0_partition; + zephyr,can-primary = &can1; }; leds { @@ -124,6 +125,17 @@ status = "okay"; }; +&can1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + bus-speed = <125000>; + sjw = <1>; + sample-point = <875>; + bus-speed-data = <1000000>; + sjw-data = <1>; + sample-point-data = <875>; + status = "okay"; +}; + /* * WARNING: * Possible pin conflicts: diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts index 02a1422b3d293..6664b77766c8c 100644 --- a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts @@ -20,6 +20,7 @@ zephyr,flash = &flash0; zephyr,dtcm = &dtcm; zephyr,code-partition = &slot0_partition; + zephyr,can-primary = &can1; }; leds { @@ -124,6 +125,17 @@ status = "okay"; }; +&can1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + bus-speed = <125000>; + sjw = <1>; + sample-point = <875>; + bus-speed-data = <1000000>; + sjw-data = <1>; + sample-point-data = <875>; + status = "okay"; +}; + /* * WARNING: * Possible pin conflicts: From d1aa885da63dab6c3db2d84312661a4203b4eda3 Mon Sep 17 00:00:00 2001 From: Jeremy Wood Date: Thu, 27 May 2021 17:47:02 -0700 Subject: [PATCH 3/4] drivers: can: STM32H7 in can_mcan_reg, clock config. * Add STM32h7 fields to can_mcan_reg. * STM32H FDCAN clock config changes. Signed-off-by: Jeremy Wood --- drivers/can/can_mcan_int.h | 26 ++++++++++++++++++++++++++ drivers/can/can_stm32fd.c | 9 +++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/can/can_mcan_int.h b/drivers/can/can_mcan_int.h index 421be753a1019..5279aeb260b2a 100644 --- a/drivers/can/can_mcan_int.h +++ b/drivers/can/can_mcan_int.h @@ -1478,14 +1478,33 @@ struct can_mcan_reg { volatile uint32_t ile; /* Interrupt Line Enable */ uint32_t res3[8]; /* Reserved (8) */ volatile uint32_t rxgfc; /* Global Filter Configuration */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + volatile uint32_t sidfc; /* Standard ID Filter Configuration */ + volatile uint32_t xidfc; /* Extended ID Filter Configuration */ + uint32_t res31; /* Reserved (1) */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ volatile uint32_t xidam; /* Extended ID AND Mask */ volatile uint32_t hpms; /* High Priority Message Status */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + volatile uint32_t ndat1; /* New Data 1 */ + volatile uint32_t ndat2; /* New Data 2 */ + volatile uint32_t rxf0c; /* Rx FIFO 0 Configuration */ +#else uint32_t res4; /* Reserved (1) */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ volatile uint32_t rxf0s; /* Rx FIFO 0 Status */ volatile uint32_t rxf0a; /* Rx FIFO 0 Acknowledge */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + volatile uint32_t rxbc; /* Rx Buffer Configuration */ + volatile uint32_t rxf1c; /* Rx FIFO 1 Configuration */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ volatile uint32_t rxf1s; /* Rx FIFO 1 Status */ volatile uint32_t rxf1a; /* Rx FIFO 1 Acknowledge */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + volatile uint32_t rxesc; /* Rx Buffer/FIFO Element Size Configuration */ +#else uint32_t res5[8]; /* Reserved (8) */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ volatile uint32_t txbc; /* Tx Buffer Configuration */ volatile uint32_t txfqs; /* Tx FIFO/Queue Status */ volatile uint32_t txbrp; /* Tx Buffer Request Pending */ @@ -1495,8 +1514,15 @@ struct can_mcan_reg { volatile uint32_t txbcf; /* Tx Buffer Cancellation Finished */ volatile uint32_t txbtie; /* Tx Buffer Transmission Interrupt Enable */ volatile uint32_t txcbie; /* Tx Buffer Cancellation Fi.Interrupt En. */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + uint32_t res5[2]; /* Reserved (2) */ + volatile uint32_t txefc; /* Tx Event FIFO Configuration */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ volatile uint32_t txefs; /* Tx Event FIFO Status */ volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + uint32_t res6; /* Reserved (1) */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ }; #else /* CONFIG_CAN_STM32FD */ diff --git a/drivers/can/can_stm32fd.c b/drivers/can/can_stm32fd.c index 43256d95641cf..7ef531970f375 100644 --- a/drivers/can/can_stm32fd.c +++ b/drivers/can/can_stm32fd.c @@ -40,10 +40,19 @@ int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate) void can_stm32fd_clock_enable(void) { +#if defined(CONFIG_SOC_SERIES_STM32H7X) + LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q); + __HAL_RCC_FDCAN_CLK_ENABLE(); + + if (!LL_RCC_PLL1Q_IsEnabled()) { + LOG_ERR("PLL1Q clock must be enabled!"); + } +#else LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); __HAL_RCC_FDCAN_CLK_ENABLE(); FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1; +#endif } void can_stm32fd_register_state_change_isr(const struct device *dev, From 75962f4eb7ae1cd8bdf4ecadc4917f8f4209cff9 Mon Sep 17 00:00:00 2001 From: Jeremy Wood Date: Thu, 3 Jun 2021 17:41:39 -0700 Subject: [PATCH 4/4] WIP: Changed CONFIG_CAN_STM32FD to CONFIG_CAN_STM32FD_LITE in can_mcan.c and can_mcan_int.h, added lots of debug logging. Also modified /samples/drivers/can to turn on logging, etc. Loopback mode doesn't work. When loopback is OFF, I see some activity on CAN H/L, looks like the first CAN frame is being auto-retransmitted constantly. Tried connecting two boards, that doesn't work either. --- boards/arm/nucleo_f429zi/nucleo_f429zi.dts | 7 ++ boards/arm/nucleo_h753zi/nucleo_h753zi.dts | 2 +- drivers/can/can_mcan.c | 26 ++++- drivers/can/can_mcan_int.h | 105 +++++++++++---------- drivers/can/can_stm32fd.c | 9 ++ samples/drivers/can/prj.conf | 7 ++ samples/drivers/can/src/main.c | 5 +- 7 files changed, 104 insertions(+), 57 deletions(-) diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts b/boards/arm/nucleo_f429zi/nucleo_f429zi.dts index 4401e57bd95d2..d56a6b49c05b5 100644 --- a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts +++ b/boards/arm/nucleo_f429zi/nucleo_f429zi.dts @@ -20,6 +20,7 @@ zephyr,flash = &flash0; zephyr,ccm = &ccm0; zephyr,code-partition = &slot0_partition; + zephyr,can-primary = &can1; }; leds { @@ -54,6 +55,12 @@ }; }; +&can1 { + pinctrl-0 = <&can1_rx_pd0 &can1_tx_pd1>; + bus-speed = <125000>; + status = "okay"; +}; + &clk_hse { hse-bypass; clock-frequency = ; /* STLink 8MHz clock */ diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts index 6664b77766c8c..ad673bfbbdf4e 100644 --- a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/arm/nucleo_h753zi/nucleo_h753zi.dts @@ -130,7 +130,7 @@ bus-speed = <125000>; sjw = <1>; sample-point = <875>; - bus-speed-data = <1000000>; + bus-speed-data = <125000>; sjw-data = <1>; sample-point-data = <875>; status = "okay"; diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index 39d3790493678..0c4e38eb496dd 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -238,7 +238,7 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, (can->crel & CAN_MCAN_CREL_MON) >> CAN_MCAN_CREL_MON_POS, (can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS); -#ifndef CONFIG_CAN_STM32FD +#ifndef CONFIG_CAN_STM32FD_LITE can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) | (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS); can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) | @@ -291,7 +291,7 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, #endif -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE can->rxgfc |= (CONFIG_CAN_MAX_STD_ID_FILTER << CAN_MCAN_RXGFC_LSS_POS) | (CONFIG_CAN_MAX_EXT_ID_FILTER << CAN_MCAN_RXGFC_LSE_POS) | (0x2 << CAN_MCAN_RXGFC_ANFS_POS) | @@ -299,7 +299,7 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, #else can->gfc |= (0x2 << CAN_MCAN_GFC_ANFE_POS) | (0x2 << CAN_MCAN_GFC_ANFS_POS); -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ if (cfg->sample_point) { ret = can_calc_timing(dev, &timing, cfg->bus_speed, @@ -356,7 +356,7 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, CAN_MCAN_IE_RF0N | CAN_MCAN_IE_RF1N | CAN_MCAN_IE_RF0L | CAN_MCAN_IE_RF1L; -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE can->ils = CAN_MCAN_ILS_RXFIFO0 | CAN_MCAN_ILS_RXFIFO1; #else can->ils = CAN_MCAN_ILS_RF0N | CAN_MCAN_ILS_RF1N; @@ -428,16 +428,20 @@ void can_mcan_line_0_isr(const struct can_mcan_config *cfg, { struct can_mcan_reg *can = cfg->can; + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + do { if (can->ir & (CAN_MCAN_IR_BO | CAN_MCAN_IR_EP | CAN_MCAN_IR_EW)) { can->ir = CAN_MCAN_IR_BO | CAN_MCAN_IR_EP | CAN_MCAN_IR_EW; + LOG_DBG("%s: %s: state_change, %d", __func__, __FILE__, __LINE__); can_mcan_state_change_handler(cfg, data); } /* TX event FIFO new entry */ if (can->ir & CAN_MCAN_IR_TEFN) { can->ir = CAN_MCAN_IR_TEFN; + LOG_DBG("%s: %s: CAN_MCAN_IR_TEFN, %d", __func__, __FILE__, __LINE__); can_mcan_tc_event_handler(can, msg_ram, data); } @@ -656,16 +660,24 @@ int can_mcan_send(const struct can_mcan_config *cfg, return CAN_TX_BUS_OFF; } + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + ret = k_sem_take(&data->tx_sem, timeout); if (ret != 0) { return CAN_TIMEOUT; } + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + __ASSERT_NO_MSG((can->txfqs & CAN_MCAN_TXFQS_TFQF) != CAN_MCAN_TXFQS_TFQF); + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + k_mutex_lock(&data->tx_mtx, K_FOREVER); + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + put_idx = ((can->txfqs & CAN_MCAN_TXFQS_TFQPI) >> CAN_MCAN_TXFQS_TFQPI_POS); @@ -689,6 +701,8 @@ int can_mcan_send(const struct can_mcan_config *cfg, *dst = *src; } + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + data->tx_fin_cb[put_idx] = callback; data->tx_fin_cb_arg[put_idx] = callback_arg; @@ -696,11 +710,15 @@ int can_mcan_send(const struct can_mcan_config *cfg, k_mutex_unlock(&data->tx_mtx); + LOG_DBG("%s: %s, %d", __func__, __FILE__, __LINE__); + if (callback == NULL) { LOG_DBG("Waiting for TX complete"); k_sem_take(&data->tx_fin_sem[put_idx], K_FOREVER); } + LOG_INF("%s: %s, %d! Yay!", __func__, __FILE__, __LINE__); + return CAN_TX_OK; } diff --git a/drivers/can/can_mcan_int.h b/drivers/can/can_mcan_int.h index 5279aeb260b2a..a92da63e5df50 100644 --- a/drivers/can/can_mcan_int.h +++ b/drivers/can/can_mcan_int.h @@ -307,7 +307,7 @@ #define CAN_MCAN_TDCR_TDCO CAN_MCAN_TDCR_TDCO_MSK /*************** Bit definition for CAN_MCAN_IR register ********************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 0 New Message */ #define CAN_MCAN_IR_RF0N_POS (0U) #define CAN_MCAN_IR_RF0N_MSK (0x1UL << CAN_MCAN_IR_RF0N_POS) @@ -405,7 +405,7 @@ #define CAN_MCAN_IR_ARA_MSK (0x1UL << CAN_MCAN_IR_ARA_POS) #define CAN_MCAN_IR_ARA CAN_MCAN_IR_ARA_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Rx FIFO 0 New Message */ #define CAN_MCAN_IR_RF0N_POS (0U) @@ -528,10 +528,10 @@ #define CAN_MCAN_IR_ARA_MSK (0x1UL << CAN_MCAN_IR_ARA_POS) #define CAN_MCAN_IR_ARA CAN_MCAN_IR_ARA_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_IE register ********************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 0 New Message Enable */ #define CAN_MCAN_IE_RF0N_POS (0U) #define CAN_MCAN_IE_RF0N_MSK (0x1UL << CAN_MCAN_IE_RF0N_POS) @@ -629,7 +629,7 @@ #define CAN_MCAN_IE_ARA_MSK (0x1UL << CAN_MCAN_IE_ARA_POS) #define CAN_MCAN_IE_ARA CAN_MCAN_IE_ARA_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Rx FIFO 0 New Message */ #define CAN_MCAN_IE_RF0N_POS (0U) @@ -752,10 +752,10 @@ #define CAN_MCAN_IE_ARA_MSK (0x1UL << CAN_MCAN_IE_ARA_POS) #define CAN_MCAN_IE_ARA CAN_MCAN_IE_ARA_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_ILS register *******************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 0 */ #define CAN_MCAN_ILS_RXFIFO0_POS (0U) #define CAN_MCAN_ILS_RXFIFO0_MSK (0x1UL << CAN_MCAN_ILS_RXFIFO0_POS) @@ -785,7 +785,7 @@ #define CAN_MCAN_ILS_PERR_MSK (0x1UL << CAN_MCAN_ILS_PERR_POS) #define CAN_MCAN_ILS_PERR CAN_MCAN_ILS_PERR_MSK -#else/* CONFIG_CAN_STM32FD */ +#else/* CONFIG_CAN_STM32FD_LITE */ /* Rx FIFO 0 New Message */ #define CAN_MCAN_ILS_RF0N_POS (0U) #define CAN_MCAN_ILS_RF0N_MSK (0x1UL << CAN_MCAN_ILS_RF0N_POS) @@ -907,7 +907,7 @@ #define CAN_MCAN_ILS_ARA_MSK (0x1UL << CAN_MCAN_ILS_ARA_POS) #define CAN_MCAN_ILS_ARA CAN_MCAN_IL_ARA_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_ILE register *******************/ /* Enable Interrupt Line 0 */ @@ -920,7 +920,7 @@ #define CAN_MCAN_ILE_EINT1 CAN_MCAN_ILE_EINT1_MSK /*************** Bit definition for CAN_MCAN_RXGFC register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Reject Remote Frames Extended */ #define CAN_MCAN_RXGFC_RRFE_POS (0U) #define CAN_MCAN_RXGFC_RRFE_MSK (0x1UL << CAN_MCAN_RXGFC_RRFE_POS) @@ -954,7 +954,7 @@ #define CAN_MCAN_RXGFC_LSE_MSK (0xFUL << CAN_MCAN_RXGFC_LSE_POS) #define CAN_MCAN_RXGFC_LSE CAN_MCAN_RXGFC_LSE_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Reject Remote Frames Extended */ #define CAN_MCAN_GFC_RRFE_POS (0U) @@ -991,7 +991,7 @@ #define CAN_MCAN_XIDFC_LSS_MSK (0x7FUL << CAN_MCAN_XIDFC_LSS_POS) #define CAN_MCAN_XIDFC_LSS CAN_MCAN_XIDFC_LSS_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_XIDAM register *****************/ /* Extended ID Mask */ @@ -1000,7 +1000,7 @@ #define CAN_MCAN_XIDAM_EIDM CAN_MCAN_XIDAM_EIDM_MSK /*************** Bit definition for CAN_MCAN_HPMS register ******************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Buffer Index */ #define CAN_MCAN_HPMS_BIDX_POS (0U) #define CAN_MCAN_HPMS_BIDX_MSK (0x7UL << CAN_MCAN_HPMS_BIDX_POS) @@ -1018,7 +1018,7 @@ #define CAN_MCAN_HPMS_FLST_MSK (0x1UL << CAN_MCAN_HPMS_FLST_POS) #define CAN_MCAN_HPMS_FLST CAN_MCAN_HPMS_FLST_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Buffer Index */ #define CAN_MCAN_HPMS_BIDX_POS (0U) @@ -1037,7 +1037,7 @@ #define CAN_MCAN_HPMS_FLST_MSK (0x1UL << CAN_MCAN_HPMS_FLST_POS) #define CAN_MCAN_HPMS_FLST CAN_MCAN_HPMS_FLST_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_RXF0C register *****************/ /* Rx FIFO 0 Start Address */ @@ -1058,7 +1058,7 @@ #define CAN_MCAN_RXF0C_F0OM CAN_MCAN_RXF0C_F0OM_MSK /*************** Bit definition for CAN_MCAN_RXF0S register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 0 Fill Level */ #define CAN_MCAN_RXF0S_F0FL_POS (0U) #define CAN_MCAN_RXF0S_F0FL_MSK (0xFUL << CAN_MCAN_RXF0S_F0FL_POS) @@ -1080,7 +1080,7 @@ #define CAN_MCAN_RXF0S_RF0L_MSK (0x1UL << CAN_MCAN_RXF0S_RF0L_POS) #define CAN_MCAN_RXF0S_RF0L CAN_MCAN_RXF0S_RF0L_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Rx FIFO 0 Fill Level */ #define CAN_MCAN_RXF0S_F0FL_POS (0U) @@ -1105,7 +1105,7 @@ #endif /*************** Bit definition for CAN_MCAN_RXF0A register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 0 Acknowledge Index */ #define CAN_MCAN_RXF0A_F0AI_POS (0U) #define CAN_MCAN_RXF0A_F0AI_MSK (0x7UL << CAN_MCAN_RXF0A_F0AI_POS) @@ -1116,7 +1116,7 @@ #define CAN_MCAN_RXF0A_F0AI_MSK (0x3FUL << CAN_MCAN_RXF0A_F0AI_POS) #define CAN_MCAN_RXF0A_F0AI CAN_MCAN_RXF0A_F0AI_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_RXBC register ******************/ /* Rx Buffer Start Address */ @@ -1143,7 +1143,7 @@ #define CAN_MCAN_RXF1C_F1OM CAN_MCAN_RXF1C_F1OM_MSK /*************** Bit definition for CAN_MCAN_RXF1S register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Rx FIFO 1 Fill Level */ #define CAN_MCAN_RXF1S_F1FL_POS (0U) #define CAN_MCAN_RXF1S_F1FL_MSK (0xFUL << CAN_MCAN_RXF1S_F1FL_POS) @@ -1165,7 +1165,7 @@ #define CAN_MCAN_RXF1S_RF1L_MSK (0x1UL << CAN_MCAN_RXF1S_RF1L_POS) #define CAN_MCAN_RXF1S_RF1L CAN_MCAN_RXF1S_RF1L_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Rx FIFO 1 Fill Level */ #define CAN_MCAN_RXF1S_F1FL_POS (0U) @@ -1188,11 +1188,11 @@ #define CAN_MCAN_RXF1S_RF1L_MSK (0x1UL << CAN_MCAN_RXF1S_RF1L_POS) #define CAN_MCAN_RXF1S_RF1L CAN_MCAN_RXF1S_RF1L_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_RXF1A register *****************/ /* Rx FIFO 1 Acknowledge Index */ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE #define CAN_MCAN_RXF1A_F1AI_POS (0U) #define CAN_MCAN_RXF1A_F1AI_MSK (0x7UL << CAN_MCAN_RXF1A_F1AI_POS) #define CAN_MCAN_RXF1A_F1AI CAN_MCAN_RXF1A_F1AI_MSK @@ -1200,7 +1200,7 @@ #define CAN_MCAN_RXF1A_F1AI_POS (0U) #define CAN_MCAN_RXF1A_F1AI_MSK (0x3FUL << CAN_MCAN_RXF1A_F1AI_POS) #define CAN_MCAN_RXF1A_F1AI CAN_MCAN_RXF1A_F1AI_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_RXESC register *****************/ /* Rx FIFO 0 Data Field Size */ @@ -1217,7 +1217,7 @@ #define CAN_MCAN_RXESC_RBDS CAN_MCAN_RXESC_RBDS_MSK /*************** Bit definition for CAN_MCAN_TXBC register ******************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Tx FIFO/Queue Mode */ #define CAN_MCAN_TXBC_TFQM_POS (24U) #define CAN_MCAN_TXBC_TFQM_MSK (0x1UL << CAN_MCAN_TXBC_TFQM_POS) @@ -1240,10 +1240,10 @@ #define CAN_MCAN_TXBC_TFQM_MSK (0x3FUL << CAN_MCAN_TXBC_TFQM_POS) #define CAN_MCAN_TXBC_TFQM CAN_MCAN_TXBC_TFQM_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXFQS register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Tx FIFO Free Level */ #define CAN_MCAN_TXFQS_TFFL_POS (0U) #define CAN_MCAN_TXFQS_TFFL_MSK (0x7UL << CAN_MCAN_TXFQS_TFFL_POS) @@ -1261,7 +1261,7 @@ #define CAN_MCAN_TXFQS_TFQF_MSK (0x1UL << CAN_MCAN_TXFQS_TFQF_POS) #define CAN_MCAN_TXFQS_TFQF CAN_MCAN_TXFQS_TFQF_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Tx FIFO Free Level */ #define CAN_MCAN_TXFQS_TFFL_POS (0U) @@ -1280,7 +1280,7 @@ #define CAN_MCAN_TXFQS_TFQF_MSK (0x1UL << CAN_MCAN_TXFQS_TFQF_POS) #define CAN_MCAN_TXFQS_TFQF CAN_MCAN_TXFQS_TFQF_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXESC register *****************/ /* Tx Buffer Data Field Size */ @@ -1289,7 +1289,7 @@ #define CAN_MCAN_TXESC_TBDS CAN_MCAN_TXESC_TBDS_MSK /*************** Bit definition for CAN_MCAN_TXBRP register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Transmission Request Pending */ #define CAN_MCAN_TXBRP_TRP_POS (0U) #define CAN_MCAN_TXBRP_TRP_MSK (0x7UL << CAN_MCAN_TXBRP_TRP_POS) @@ -1299,10 +1299,10 @@ #define CAN_MCAN_TXBRP_TRP_POS (0U) #define CAN_MCAN_TXBRP_TRP_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBRP_TRP_POS) #define CAN_MCAN_TXBRP_TRP CAN_MCAN_TXBRP_TRP_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXBAR register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Add Request */ #define CAN_MCAN_TXBAR_AR_POS (0U) #define CAN_MCAN_TXBAR_AR_MSK (0x7UL << CAN_MCAN_TXBAR_AR_POS) @@ -1312,10 +1312,10 @@ #define CAN_MCAN_TXBAR_AR_POS (0U) #define CAN_MCAN_TXBAR_AR_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBAR_AR_POS) #define CAN_MCAN_TXBAR_AR CAN_MCAN_TXBAR_AR_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXBCR register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Cancellation Request */ #define CAN_MCAN_TXBCR_CR_POS (0U) #define CAN_MCAN_TXBCR_CR_MSK (0x7UL << CAN_MCAN_TXBCR_CR_POS) @@ -1325,10 +1325,10 @@ #define CAN_MCAN_TXBCR_CR_POS (0U) #define CAN_MCAN_TXBCR_CR_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBCR_CR_POS) #define CAN_MCAN_TXBCR_CR CAN_MCAN_TXBCR_CR_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXBTO register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Transmission Occurred */ #define CAN_MCAN_TXBTO_TO_POS (0U) #define CAN_MCAN_TXBTO_TO_MSK (0x7UL << CAN_MCAN_TXBTO_TO_POS) @@ -1338,10 +1338,10 @@ #define CAN_MCAN_TXBTO_TO_POS (0U) #define CAN_MCAN_TXBTO_TO_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBTO_TO_POS) #define CAN_MCAN_TXBTO_TO CAN_MCAN_TXBTO_TO_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXBCF register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Cancellation Finished */ #define CAN_MCAN_TXBCF_CF_POS (0U) #define CAN_MCAN_TXBCF_CF_MSK (0x7UL << CAN_MCAN_TXBCF_CF_POS) @@ -1351,10 +1351,10 @@ #define CAN_MCAN_TXBCF_CF_POS (0U) #define CAN_MCAN_TXBCF_CF_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBCF_CF_POS) #define CAN_MCAN_TXBCF_CF CAN_MCAN_TXBCF_CF_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXBTIE register ****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Transmission Interrupt Enable */ #define CAN_MCAN_TXBTIE_TIE_POS (0U) #define CAN_MCAN_TXBTIE_TIE_MSK (0x7UL << CAN_MCAN_TXBTIE_TIE_POS) @@ -1364,10 +1364,10 @@ #define CAN_MCAN_TXBTIE_TIE_POS (0U) #define CAN_MCAN_TXBTIE_TIE_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBTIE_TIE_POS) #define CAN_MCAN_TXBTIE_TIE CAN_MCAN_TXBTIE_TIE_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_ TXBCIE register ***************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Cancellation Finished Interrupt Enable */ #define CAN_MCAN_TXBCIE_CFIE_POS (0U) #define CAN_MCAN_TXBCIE_CFIE_MSK (0x7UL << CAN_MCAN_TXBCIE_CFIE_POS) @@ -1377,7 +1377,7 @@ #define CAN_MCAN_TXBCIE_CFIE_POS (0U) #define CAN_MCAN_TXBCIE_CFIE_MSK (0xFFFFFFFFUL << CAN_MCAN_TXBCIE_CFIE_POS) #define CAN_MCAN_TXBCIE_CFIE CAN_MCAN_TXBCIE_CFIE_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXEFC register *****************/ /* Event FIFO Watermark */ @@ -1394,7 +1394,7 @@ #define CAN_MCAN_TXEFC_EFWM CAN_MCAN_TXEFC_EFWM_POS /*************** Bit definition for CAN_MCAN_TXEFS register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Event FIFO Fill Level */ #define CAN_MCAN_TXEFS_EFFL_POS (0U) #define CAN_MCAN_TXEFS_EFFL_MSK (0x7UL << CAN_MCAN_TXEFS_EFFL_POS) @@ -1416,7 +1416,7 @@ #define CAN_MCAN_TXEFS_TEFL_MSK (0x1UL << CAN_MCAN_TXEFS_TEFL_POS) #define CAN_MCAN_TXEFS_TEFL CAN_MCAN_TXEFS_TEFL_MSK -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ /* Event FIFO Fill Level */ #define CAN_MCAN_TXEFS_EFFL_POS (0U) #define CAN_MCAN_TXEFS_EFFL_MSK (0x3FUL << CAN_MCAN_TXEFS_EFFL_POS) @@ -1438,10 +1438,10 @@ #define CAN_MCAN_TXEFS_TEFL_MSK (0x1UL << CAN_MCAN_TXEFS_TEFL_POS) #define CAN_MCAN_TXEFS_TEFL CAN_MCAN_TXEFS_TEFL_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ /*************** Bit definition for CAN_MCAN_TXEFA register *****************/ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE /* Event FIFO Acknowledge Index */ #define CAN_MCAN_TXEFA_EFAI_POS (0U) #define CAN_MCAN_TXEFA_EFAI_MSK (0x3UL << CAN_MCAN_TXEFA_EFAI_POS) @@ -1451,9 +1451,9 @@ #define CAN_MCAN_TXEFA_EFAI_POS (0U) #define CAN_MCAN_TXEFA_EFAI_MSK (0x1FUL << CAN_MCAN_TXEFA_EFAI_POS) #define CAN_MCAN_TXEFA_EFAI CAN_MCAN_TXEFA_EFAI_MSK -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ -#ifdef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_STM32FD_LITE struct can_mcan_reg { volatile uint32_t crel; /* Core Release Register */ volatile uint32_t endn; /* Endian Register */ @@ -1524,7 +1524,7 @@ struct can_mcan_reg { uint32_t res6; /* Reserved (1) */ #endif /* CONFIG_SOC_SERIES_STM32H7X */ }; -#else /* CONFIG_CAN_STM32FD */ +#else /* CONFIG_CAN_STM32FD_LITE */ struct can_mcan_reg { volatile uint32_t crel; /* Core Release Register */ @@ -1579,8 +1579,11 @@ struct can_mcan_reg { volatile uint32_t txefc; /* Tx Event FIFO Configuration */ volatile uint32_t txefs; /* Tx Event FIFO Status */ volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */ +#if defined(CONFIG_SOC_SERIES_STM32H7X) + uint32_t res6; /* Reserved (1) */ +#endif /* CONFIG_SOC_SERIES_STM32H7X */ }; -#endif /* CONFIG_CAN_STM32FD */ +#endif /* CONFIG_CAN_STM32FD_LITE */ #endif /*ZEPHYR_DRIVERS_CAN_MCAN_INT_H_*/ diff --git a/drivers/can/can_stm32fd.c b/drivers/can/can_stm32fd.c index 7ef531970f375..75bc4ea2ca571 100644 --- a/drivers/can/can_stm32fd.c +++ b/drivers/can/can_stm32fd.c @@ -35,9 +35,14 @@ int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate) *rate = rate_tmp / CONFIG_CAN_STM32_CLOCK_DIVISOR; + LOG_DBG("%s: rate=%d", __func__, *rate); + return 0; } +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + + void can_stm32fd_clock_enable(void) { #if defined(CONFIG_SOC_SERIES_STM32H7X) @@ -47,6 +52,8 @@ void can_stm32fd_clock_enable(void) if (!LL_RCC_PLL1Q_IsEnabled()) { LOG_ERR("PLL1Q clock must be enabled!"); } + + LOG_DBG("can_stm32fd_clock_enable"); #else LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); __HAL_RCC_FDCAN_CLK_ENABLE(); @@ -109,6 +116,8 @@ int can_stm32fd_send(const struct device *dev, const struct zcan_frame *frame, struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data; struct can_mcan_msg_sram *msg_ram = cfg->msg_sram; + LOG_DBG("%s:", __func__); + return can_mcan_send(mcan_cfg, mcan_data, msg_ram, frame, timeout, callback, callback_arg); } diff --git a/samples/drivers/can/prj.conf b/samples/drivers/can/prj.conf index de1bf3ea7b541..bafb7663c45b3 100644 --- a/samples/drivers/can/prj.conf +++ b/samples/drivers/can/prj.conf @@ -1,8 +1,15 @@ CONFIG_CAN=y CONFIG_CAN_INIT_PRIORITY=80 CONFIG_CAN_MAX_FILTER=5 +# CONFIG_CAN_FD_MODE=n CONFIG_SHELL=y CONFIG_CAN_SHELL=y CONFIG_DEVICE_SHELL=y CONFIG_SHELL_ARGC_MAX=13 + +CONFIG_LOG=y +CONFIG_CAN_LOG_LEVEL_ERR=y +CONFIG_CAN_LOG_LEVEL_INF=y +CONFIG_CAN_LOG_LEVEL_DBG=y +CONFIG_LOOPBACK_MODE=y diff --git a/samples/drivers/can/src/main.c b/samples/drivers/can/src/main.c index a56fde56c1780..fbfd6f413fc63 100644 --- a/samples/drivers/can/src/main.c +++ b/samples/drivers/can/src/main.c @@ -166,6 +166,8 @@ void state_change_isr(enum can_state state, struct can_bus_err_cnt err_cnt) void main(void) { + int rc; + const struct zcan_filter change_led_filter = { .id_type = CAN_STANDARD_IDENTIFIER, .rtr = CAN_DATAFRAME, @@ -260,7 +262,8 @@ void main(void) (uint16_t *)&counter_frame.data[0]); counter++; /* This sending call is blocking until the message is sent. */ - can_send(can_dev, &counter_frame, K_MSEC(100), NULL, NULL); + rc = can_send(can_dev, &counter_frame, K_MSEC(100), NULL, NULL); + printk("can_send() rc=%d\n", rc); k_sleep(SLEEP_TIME); } }