From d1858ce9f01cb311cb07d26ebb70d5f063851c17 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 3 Jan 2022 09:18:00 +0100 Subject: [PATCH 1/8] drivers: can: mcan: fix CAN_MCAN_TXEFC_EFSA_POS value The Event FIFO start address (EFSA) field within the Tx event FIFO configuration register (TXEFC) occupies bit 15:2. Change the CAN_MCAN_TXEFC_EFSA_POS definition to reflect this. Signed-off-by: Henrik Brix Andersen --- drivers/can/can_mcan_int.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/can/can_mcan_int.h b/drivers/can/can_mcan_int.h index 421be753a1019..e326294bd441c 100644 --- a/drivers/can/can_mcan_int.h +++ b/drivers/can/can_mcan_int.h @@ -1381,7 +1381,7 @@ /*************** Bit definition for CAN_MCAN_TXEFC register *****************/ /* Event FIFO Watermark */ -#define CAN_MCAN_TXEFC_EFSA_POS (0U) +#define CAN_MCAN_TXEFC_EFSA_POS (2U) #define CAN_MCAN_TXEFC_EFSA_MSK (0x3FFFUL << CAN_MCAN_TXEFC_EFSA_POS) #define CAN_MCAN_TXEFC_EFSA CAN_MCAN_TXEFC_EFSA_MSK /* Event FIFO Size */ From 458b22c1a04624028a6436f0e2e91d58ec292836 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:11:23 +0200 Subject: [PATCH 2/8] modules: mcux: add support for indicating the presence of MCAN Add Kconfig option for indicating that a given SoC contains the NXP MCAN CAN FD controller. Signed-off-by: Henrik Brix Andersen --- modules/Kconfig.mcux | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index 04a397c72bd90..3cd9104a20d5b 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -314,4 +314,9 @@ config HAS_MCUX_I2S help Set if the I2S/SAI module is present on the Soc +config HAS_MCUX_MCAN + bool + help + Set if the MCAN module is present on the SoC. + endif # HAS_MCUX From d38269a06fb2ea32d18c4aa96f45cf2e31de7c63 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:13:49 +0200 Subject: [PATCH 3/8] drivers: clock_control: lpc: syscon: add MCAN clock support Add support for the LPC MCAN clock to the LPC SYSCON clock controller driver. Signed-off-by: Henrik Brix Andersen --- .../clock_control/clock_control_mcux_syscon.c | 20 ++++++++++++++++++- .../dt-bindings/clock/mcux_lpc_syscon_clock.h | 1 + 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 7691563e7d136..9af71194ce783 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -18,6 +18,14 @@ LOG_MODULE_REGISTER(clock_control); static int mcux_lpc_syscon_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) { +#if defined(CONFIG_CAN_MCUX_MCAN) + uint32_t clock_name = (uint32_t)sub_system; + + if (clock_name == MCUX_MCAN_CLK) { + CLOCK_EnableClock(kCLOCK_Mcan); + } +#endif /* defined(CONFIG_CAN_MCUX_MCAN) */ + return 0; } @@ -35,11 +43,15 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( #if defined(CONFIG_I2C_MCUX_FLEXCOMM) || \ defined(CONFIG_SPI_MCUX_FLEXCOMM) || \ defined(CONFIG_UART_MCUX_FLEXCOMM) || \ - defined(CONFIG_COUNTER_MCUX_CTIMER) + defined(CONFIG_COUNTER_MCUX_CTIMER) || \ + defined(CONFIG_CAN_MCUX_MCAN) uint32_t clock_name = (uint32_t) sub_system; switch (clock_name) { +#if defined(CONFIG_I2C_MCUX_FLEXCOMM) || \ + defined(CONFIG_SPI_MCUX_FLEXCOMM) || \ + defined(CONFIG_UART_MCUX_FLEXCOMM) case MCUX_FLEXCOMM0_CLK: *rate = CLOCK_GetFlexCommClkFreq(0); break; @@ -84,6 +96,11 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( *rate = CLOCK_GetSdioClkFreq(1); break; #endif +#if defined(CONFIG_CAN_MCUX_MCAN) + case MCUX_MCAN_CLK: + *rate = CLOCK_GetMCanClkFreq(); + break; +#endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_COUNTER_MCUX_CTIMER) case (MCUX_CTIMER0_CLK + MCUX_CTIMER_CLK_OFFSET): *rate = CLOCK_GetCTimerClkFreq(0); @@ -102,6 +119,7 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( break; #endif } +#endif #endif return 0; diff --git a/include/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/dt-bindings/clock/mcux_lpc_syscon_clock.h index 7c29d2005733f..456b5a7b3c56b 100644 --- a/include/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -17,6 +17,7 @@ #define MCUX_FLEXCOMM7_CLK 7 #define MCUX_PMIC_I2C_CLK 16 #define MCUX_HS_SPI_CLK 8 +#define MCUX_MCAN_CLK 9 #define MCUX_USDHC1_CLK 9 #define MCUX_USDHC2_CLK 10 From 30b6e4b8180ad9f2fee5e525e4ae2ce1e0e9de34 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:17:04 +0200 Subject: [PATCH 4/8] dts: bindings: can: add NXP LPC MCAN devicetree binding Add devicetree binding for the NXP LPC MCAN CAN-FD controller. Signed-off-by: Henrik Brix Andersen --- dts/bindings/can/nxp,lpc-mcan.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 dts/bindings/can/nxp,lpc-mcan.yaml diff --git a/dts/bindings/can/nxp,lpc-mcan.yaml b/dts/bindings/can/nxp,lpc-mcan.yaml new file mode 100644 index 0000000000000..53ece095e45b4 --- /dev/null +++ b/dts/bindings/can/nxp,lpc-mcan.yaml @@ -0,0 +1,15 @@ +description: NXP LPC SoC series MCAN CAN-FD controller + +compatible: "nxp,lpc-mcan" + +include: [can-fd-controller.yaml, "bosch,m-can-base.yaml"] + +properties: + reg: + required: true + + interrupts: + required: true + + clocks: + required: true From 7bf390c9949dc01bbde232110117ac296aa527f7 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:18:48 +0200 Subject: [PATCH 5/8] drivers: can: add NXP LPC MCAN front-end for the Bosch MCAN driver Add a NXP LPC MCAN-specific front-end for the generic Bosch MCAN driver. Signed-off-by: Henrik Brix Andersen --- drivers/can/CMakeLists.txt | 1 + drivers/can/Kconfig.mcux | 7 + drivers/can/can_mcan.c | 20 +++ drivers/can/can_mcan.h | 20 ++- drivers/can/can_mcan_int.h | 12 ++ drivers/can/can_mcux_mcan.c | 266 ++++++++++++++++++++++++++++++++++++ 6 files changed, 319 insertions(+), 7 deletions(-) create mode 100644 drivers/can/can_mcux_mcan.c diff --git a/drivers/can/CMakeLists.txt b/drivers/can/CMakeLists.txt index d4dd97f4b97ed..1553cc23ca84e 100644 --- a/drivers/can/CMakeLists.txt +++ b/drivers/can/CMakeLists.txt @@ -1,6 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library() +zephyr_sources_ifdef(CONFIG_CAN_MCUX_MCAN can_mcux_mcan.c) zephyr_library_sources_ifdef(CONFIG_CAN can_common.c) zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK can_loopback.c) diff --git a/drivers/can/Kconfig.mcux b/drivers/can/Kconfig.mcux index 35fd32b365127..7d27ddc5aed59 100644 --- a/drivers/can/Kconfig.mcux +++ b/drivers/can/Kconfig.mcux @@ -18,3 +18,10 @@ config CAN_MAX_FILTER range 1 64 if SOC_SERIES_IMX_RT help Defines maximum number of concurrent active RX filters + +config CAN_MCUX_MCAN + bool "MCUX MCAN driver" + depends on HAS_MCUX_MCAN && CLOCK_CONTROL + select CAN_MCAN + help + Enable support for mcux mcan driver. diff --git a/drivers/can/can_mcan.c b/drivers/can/can_mcan.c index 9927c07c89e45..fdf935dcc9fb7 100644 --- a/drivers/can/can_mcan.c +++ b/drivers/can/can_mcan.c @@ -297,6 +297,24 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, (can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS); #ifndef CONFIG_CAN_STM32FD +#ifdef CONFIG_CAN_MCUX_MCAN + uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK; + + can->mrba = mrba; + can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) | + (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS); + can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) | + (ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS); + can->rxf0c = (((uint32_t)msg_ram->rx_fifo0 - mrba) & CAN_MCAN_RXF0C_F0SA) | + (ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS); + can->rxf1c = (((uint32_t)msg_ram->rx_fifo1 - mrba) & CAN_MCAN_RXF1C_F1SA) | + (ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS); + can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA); + can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) | + (ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS); + can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) | + (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS); +#else /* CONFIG_CAN_MCUX_MCAN */ can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) | (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS); can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) | @@ -311,6 +329,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg, CAN_MCAN_TXEFC_EFS_POS); can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) | (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS); +#endif /* !CONFIG_CAN_MCUX_MCAN */ + if (sizeof(msg_ram->tx_buffer[0].data) <= 24) { can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4; } else { diff --git a/drivers/can/can_mcan.h b/drivers/can/can_mcan.h index e94573b42d24d..068b167f8436a 100644 --- a/drivers/can/can_mcan.h +++ b/drivers/can/can_mcan.h @@ -8,14 +8,20 @@ #ifndef ZEPHYR_DRIVERS_CAN_MCAN_H_ #define ZEPHYR_DRIVERS_CAN_MCAN_H_ -#define NUM_STD_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), std_filter_elements) -#define NUM_EXT_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), ext_filter_elements) -#define NUM_RX_FIFO0_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements) -#define NUM_RX_FIFO1_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements) -#define NUM_RX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_buffer_elements) +#ifdef CONFIG_CAN_MCUX_MCAN +#define MCAN_DT_PATH DT_NODELABEL(can0) +#else +#define MCAN_DT_PATH DT_PATH(soc, can) +#endif + +#define NUM_STD_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, std_filter_elements) +#define NUM_EXT_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, ext_filter_elements) +#define NUM_RX_FIFO0_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements) +#define NUM_RX_FIFO1_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements) +#define NUM_RX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_buffer_elements) #define NUM_TX_EVENT_FIFO_ELEMENTS \ - DT_PROP(DT_PATH(soc, can), tx_event_fifo_elements) -#define NUM_TX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), tx_buffer_elements) + DT_PROP(MCAN_DT_PATH, tx_event_fifo_elements) +#define NUM_TX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, tx_buffer_elements) #ifdef CONFIG_CAN_STM32FD diff --git a/drivers/can/can_mcan_int.h b/drivers/can/can_mcan_int.h index e326294bd441c..63d2ec06fa951 100644 --- a/drivers/can/can_mcan_int.h +++ b/drivers/can/can_mcan_int.h @@ -1453,6 +1453,14 @@ #define CAN_MCAN_TXEFA_EFAI CAN_MCAN_TXEFA_EFAI_MSK #endif /* CONFIG_CAN_STM32FD */ +/*************** Bit definition for CAN_MCAN_MRBA register *****************/ +#ifdef CONFIG_CAN_MCUX_MCAN +/* Event FIFO Acknowledge Index */ +#define CAN_MCAN_MRBA_BA_POS (16U) +#define CAN_MCAN_MRBA_BA_MSK (0xFFFFUL << CAN_MCAN_MRBA_BA_POS) +#define CAN_MCAN_MRBA_BA CAN_MCAN_MRBA_BA_MSK +#endif /* CONFIG_CAN_MCUX_MCAN */ + #ifdef CONFIG_CAN_STM32FD struct can_mcan_reg { volatile uint32_t crel; /* Core Release Register */ @@ -1553,6 +1561,10 @@ struct can_mcan_reg { volatile uint32_t txefc; /* Tx Event FIFO Configuration */ volatile uint32_t txefs; /* Tx Event FIFO Status */ volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */ +#ifdef CONFIG_CAN_MCUX_MCAN + volatile uint32_t res6[65]; /* Reserved (65) */ + volatile uint32_t mrba; /* Message RAM Base Address */ +#endif /* CONFIG_CAN_MCUX_MCAN */ }; #endif /* CONFIG_CAN_STM32FD */ diff --git a/drivers/can/can_mcux_mcan.c b/drivers/can/can_mcux_mcan.c new file mode 100644 index 0000000000000..60ee7f73ddeda --- /dev/null +++ b/drivers/can/can_mcux_mcan.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2021 Henrik Brix Andersen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "can_mcan.h" + +LOG_MODULE_REGISTER(mcux_mcan, CONFIG_CAN_LOG_LEVEL); + +#define DT_DRV_COMPAT nxp_lpc_mcan + +struct mcux_mcan_config { + struct can_mcan_config mcan; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; + void (*irq_config_func)(const struct device *dev); +}; + +struct mcux_mcan_data { + struct can_mcan_data mcan; + struct can_mcan_msg_sram msg_ram __nocache; +}; + +static int mcux_mcan_set_mode(const struct device *dev, enum can_mode mode) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_set_mode(&config->mcan, mode); +} + +static int mcux_mcan_set_timing(const struct device *dev, + const struct can_timing *timing, + const struct can_timing *timing_data) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_set_timing(&config->mcan, timing, timing_data); +} + +static int mcux_mcan_send(const struct device *dev, const struct zcan_frame *msg, + k_timeout_t timeout, can_tx_callback_t callback, + void *user_data) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + return can_mcan_send(&config->mcan, &data->mcan, &data->msg_ram, + msg, timeout, callback, user_data); +} + +static int mcux_mcan_add_rx_filter(const struct device *dev, + can_rx_callback_t cb, + void *user_data, + const struct zcan_filter *filter) +{ + struct mcux_mcan_data *data = dev->data; + + return can_mcan_add_rx_filter(&data->mcan, &data->msg_ram, + cb, user_data, filter); +} + +static void mcux_mcan_remove_rx_filter(const struct device *dev, int filter_id) +{ + struct mcux_mcan_data *data = dev->data; + + can_mcan_remove_rx_filter(&data->mcan, &data->msg_ram, filter_id); +} + +static enum can_state mcux_mcan_get_state(const struct device *dev, + struct can_bus_err_cnt *err_cnt) +{ + const struct mcux_mcan_config *config = dev->config; + + return can_mcan_get_state(&config->mcan, err_cnt); +} + +static void mcux_mcan_set_state_change_callback(const struct device *dev, + can_state_change_callback_t cb) +{ + struct mcux_mcan_data *data = dev->data; + + data->mcan.state_change_cb = cb; +} + +static int mcux_mcan_get_core_clock(const struct device *dev, uint32_t *rate) +{ + const struct mcux_mcan_config *config = dev->config; + + return clock_control_get_rate(config->clock_dev, config->clock_subsys, + rate); +} + +static void mcux_mcan_line_0_isr(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + can_mcan_line_0_isr(&config->mcan, &data->msg_ram, &data->mcan); +} + +static void mcux_mcan_line_1_isr(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + + can_mcan_line_1_isr(&config->mcan, &data->msg_ram, &data->mcan); +} + +static int mcux_mcan_init(const struct device *dev) +{ + const struct mcux_mcan_config *config = dev->config; + struct mcux_mcan_data *data = dev->data; + int err; + + err = clock_control_on(config->clock_dev, config->clock_subsys); + if (err) { + LOG_ERR("failed to enable clock (err %d)", err); + return -EINVAL; + } + + err = can_mcan_init(dev, &config->mcan, &data->msg_ram, &data->mcan); + if (err) { + LOG_ERR("failed to initialize mcan (err %d)", err); + return err; + } + + config->irq_config_func(dev); + + return 0; +} + +static const struct can_driver_api mcux_mcan_driver_api = { + .set_mode = mcux_mcan_set_mode, + .set_timing = mcux_mcan_set_timing, + .send = mcux_mcan_send, + .add_rx_filter = mcux_mcan_add_rx_filter, + .remove_rx_filter = mcux_mcan_remove_rx_filter, +#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY + .recover = can_mcan_recover, +#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ + .get_state = mcux_mcan_get_state, + .set_state_change_callback = mcux_mcan_set_state_change_callback, + .get_core_clock = mcux_mcan_get_core_clock, + /* + * MCUX MCAN timing limits are specified in the "Nominal bit timing and + * prescaler register (NBTP)" table in the SoC reference manual. + * + * Note that the values here are the "physical" timing limits, whereas + * the register field limits are physical values minus 1 (which is + * handled by the register assignments in the common MCAN driver code). + */ + .timing_min = { + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1 + }, + .timing_max = { + .sjw = 128, + .prop_seg = 0, + .phase_seg1 = 256, + .phase_seg2 = 128, + .prescaler = 512, + }, +#ifdef CONFIG_CAN_FD_MODE + /* + * MCUX MCAN data timing limits are specified in the "Data bit timing + * and prescaler register (DBTP)" table in the SoC reference manual. + * + * Note that the values here are the "physical" timing limits, whereas + * the register field limits are physical values minus 1 (which is + * handled by the register assignments in the common MCAN driver code). + */ + .timing_min_data = { + .sjw = 1, + .prop_seg = 0, + .phase_seg1 = 1, + .phase_seg2 = 1, + .prescaler = 1, + }, + .timing_max_data = { + .sjw = 16, + .prop_seg = 0, + .phase_seg1 = 16, + .phase_seg2 = 16, + .prescaler = 32, + } +#endif /* CONFIG_CAN_FD_MODE */ +}; + +#ifdef CONFIG_CAN_FD_MODE +#define MCUX_MCAN_MCAN_INIT(n) \ + { \ + .can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \ + .bus_speed = DT_INST_PROP(n, bus_speed), \ + .sjw = DT_INST_PROP(n, sjw), \ + .sample_point = DT_INST_PROP_OR(n, sample_point, 0), \ + .prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \ + DT_INST_PROP_OR(n, phase_seg1, 0), \ + .ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \ + .bus_speed_data = DT_INST_PROP(n, bus_speed_data), \ + .sjw_data = DT_INST_PROP(n, sjw_data), \ + .sample_point_data = \ + DT_INST_PROP_OR(n, sample_point_data, 0), \ + .prop_ts1_data = DT_INST_PROP_OR(n, prop_seg_data, 0) + \ + DT_INST_PROP_OR(n, phase_seg1_data, 0), \ + .ts2_data = DT_INST_PROP_OR(n, phase_seg2_data, 0), \ + .tx_delay_comp_offset = \ + DT_INST_PROP(n, tx_delay_comp_offset) \ + } +#else /* CONFIG_CAN_FD_MODE */ +#define MCUX_MCAN_MCAN_INIT(n) \ + { \ + .can = (struct can_mcan_reg *)DT_INST_REG_ADDR(n), \ + .bus_speed = DT_INST_PROP(n, bus_speed), \ + .sjw = DT_INST_PROP(n, sjw), \ + .sample_point = DT_INST_PROP_OR(n, sample_point, 0), \ + .prop_ts1 = DT_INST_PROP_OR(n, prop_seg, 0) + \ + DT_INST_PROP_OR(n, phase_seg1, 0), \ + .ts2 = DT_INST_PROP_OR(n, phase_seg2, 0), \ + } +#endif /* !CONFIG_CAN_FD_MODE */ + +#define MCUX_MCAN_INIT(n) \ + static void mcux_mcan_irq_config_##n(const struct device *dev); \ + \ + static const struct mcux_mcan_config mcux_mcan_config_##n = { \ + .mcan = MCUX_MCAN_MCAN_INIT(n), \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ + .clock_subsys = (clock_control_subsys_t) \ + DT_INST_CLOCKS_CELL(n, name), \ + .irq_config_func = mcux_mcan_irq_config_##n, \ + }; \ + \ + static struct mcux_mcan_data mcux_mcan_data_##n; \ + \ + DEVICE_DT_INST_DEFINE(n, &mcux_mcan_init, NULL, \ + &mcux_mcan_data_##n, \ + &mcux_mcan_config_##n, \ + POST_KERNEL, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + &mcux_mcan_driver_api); \ + \ + static void mcux_mcan_irq_config_##n(const struct device *dev) \ + { \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \ + DT_INST_IRQ_BY_IDX(n, 0, priority), \ + mcux_mcan_line_0_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \ + \ + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \ + DT_INST_IRQ_BY_IDX(n, 1, priority), \ + mcux_mcan_line_1_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \ + } + +DT_INST_FOREACH_STATUS_OKAY(MCUX_MCAN_INIT) From 81f0b60c842df4c7669b6aff6c295199d5f85405 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:21:02 +0200 Subject: [PATCH 6/8] dts: arm: nxp: lpc55S1x: add MCAN devicetree node Add devicetree node for the NXP LPC MCAN. Signed-off-by: Henrik Brix Andersen --- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index de2bc66a1c3bc..1f918307874da 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -215,6 +215,25 @@ status = "disabled"; }; + can0: can@9d000 { + compatible = "nxp,lpc-mcan"; + reg = <0x9d000 0x1000>; + interrupts = <43 0>, <44 0>; + clocks = <&syscon MCUX_MCAN_CLK>; + label = "CAN_0"; + std-filter-elements = <128>; + ext-filter-elements = <64>; + rx-fifo0-elements = <64>; + rx-fifo1-elements = <64>; + rx-buffer-elements = <64>; + tx-buffer-elements = <32>; + sjw = <1>; + sample-point = <875>; + sjw-data = <1>; + sample-point-data = <875>; + status = "disabled"; + }; + hs_lspi: spi@9f000 { compatible = "nxp,lpc-spi"; reg = <0x9f000 0x1000>; From 47f2b94ea97a9b9fff7422cd73a5e41544610ff4 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:22:11 +0200 Subject: [PATCH 7/8] soc: arm: nxp: lpc55xxx: add MCAN support Add support for the NXP LPC MCAN CAN-FD controller. Signed-off-by: Henrik Brix Andersen --- soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 | 4 ++++ soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc | 1 + soc/arm/nxp_lpc/lpc55xxx/soc.c | 6 ++++++ 3 files changed, 11 insertions(+) diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 index 83fa8c7bc5ba8..c9f6d6f83def2 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 +++ b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 @@ -24,4 +24,8 @@ config SOC_FLASH_MCUX default y depends on FLASH +config CAN_MCUX_MCAN + default y + depends on CAN + endif # SOC_LPC55S16 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc index 0eed944e08158..3928c4371076d 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc +++ b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc @@ -17,6 +17,7 @@ config SOC_LPC55S16 select ARM_TRUSTZONE_M select CLOCK_CONTROL select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE + select HAS_MCUX_MCAN config SOC_LPC55S28 bool "SOC_LPC55S28 M33" diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c index 38781715f7f4f..ada03977deb5f 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c @@ -175,6 +175,12 @@ DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7); #endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(can0), nxp_lpc_mcan, okay) + CLOCK_SetClkDiv(kCLOCK_DivCanClk, 1U, false); + CLOCK_AttachClk(kMCAN_DIV_to_MCAN); + RESET_PeripheralReset(kMCAN_RST_SHIFT_RSTn); +#endif + #endif /* CONFIG_SOC_LPC55S69_CPU0 */ } From 21cff9ba3dfe4d2b8ca3d4a668d2b27cb44bbe7f Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 31 May 2021 22:23:15 +0200 Subject: [PATCH 8/8] boards: arm: lpcxpresso55s16: add MCAN support Add NXP LPC MCAN support for the NXP lpcxpresso55s16 board definition. Fixes #35437 Signed-off-by: Henrik Brix Andersen --- boards/arm/lpcxpresso55s16/doc/index.rst | 6 +++++ .../arm/lpcxpresso55s16/lpcxpresso55s16.yaml | 2 ++ .../lpcxpresso55s16_common.dtsi | 7 ++++++ boards/arm/lpcxpresso55s16/pinmux.c | 22 +++++++++++++++++++ 4 files changed, 37 insertions(+) diff --git a/boards/arm/lpcxpresso55s16/doc/index.rst b/boards/arm/lpcxpresso55s16/doc/index.rst index 803ca1bf08e2a..2bb31c09bae4d 100644 --- a/boards/arm/lpcxpresso55s16/doc/index.rst +++ b/boards/arm/lpcxpresso55s16/doc/index.rst @@ -73,6 +73,8 @@ hardware features: +-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ +| CAN | on-chip | canbus | ++-----------+------------+-------------------------------------+ Other hardware features are not currently enabled. @@ -119,6 +121,10 @@ the functionality of a pin. +---------+-----------------+----------------------------+ | PIO1_26 | GPIO | FXOS8700 INT1 | +---------+-----------------+----------------------------+ +| PIO1_22 | CAN | CAN RXD | ++---------+-----------------+----------------------------+ +| PIO1_27 | CAN | CAN TXD | ++---------+-----------------+----------------------------+ System Clock ============ diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml index e2afc5e58867d..6ffaa94250d10 100644 --- a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml +++ b/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml @@ -18,6 +18,8 @@ supported: - arduino_gpio - arduino_i2c - arduino_spi + - can + - canfd - gpio - i2c - spi diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi index e85b20fdd4dd0..e6969a822988c 100644 --- a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi +++ b/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi @@ -12,6 +12,7 @@ zephyr,console = &flexcomm0; zephyr,shell-uart = &flexcomm0; zephyr,entropy = &rng; + zephyr,canbus = &can0; }; aliases{ @@ -131,6 +132,12 @@ }; }; +&can0 { + status = "okay"; + bus-speed = <125000>; + bus-speed-data = <1000000>; +}; + &hs_lspi { status = "okay"; }; diff --git a/boards/arm/lpcxpresso55s16/pinmux.c b/boards/arm/lpcxpresso55s16/pinmux.c index ecc978ae21e8c..75af471070101 100644 --- a/boards/arm/lpcxpresso55s16/pinmux.c +++ b/boards/arm/lpcxpresso55s16/pinmux.c @@ -181,6 +181,28 @@ static int lpcxpresso_55s16_pinmux_init(const struct device *dev) IOCON_PIO_OPENDRAIN_DI); #endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(can0), nxp_lpc_mcan, okay) && CONFIG_CAN + /* CAN RXD, TXD */ + uint32_t port1_pin22_config = ( + IOCON_PIO_FUNC9 | + IOCON_PIO_MODE_INACT | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_SLEW_STANDARD | + IOCON_PIO_OPENDRAIN_DI + ); + uint32_t port1_pin27_config = ( + IOCON_PIO_FUNC9 | + IOCON_PIO_MODE_INACT | + IOCON_PIO_INV_DI | + IOCON_PIO_DIGITAL_EN | + IOCON_PIO_SLEW_STANDARD | + IOCON_PIO_OPENDRAIN_DI + ); + pinmux_pin_set(port1, 22, port1_pin22_config); + pinmux_pin_set(port1, 27, port1_pin27_config); +#endif + return 0; }