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Merged
merged 8 commits into from
Jan 10, 2022
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Merged

NXP: CAN: Add LPC MCAN support #35832

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d1858ce
drivers: can: mcan: fix CAN_MCAN_TXEFC_EFSA_POS value
henrikbrixandersen Jan 3, 2022
458b22c
modules: mcux: add support for indicating the presence of MCAN
henrikbrixandersen May 31, 2021
d38269a
drivers: clock_control: lpc: syscon: add MCAN clock support
henrikbrixandersen May 31, 2021
30b6e4b
dts: bindings: can: add NXP LPC MCAN devicetree binding
henrikbrixandersen May 31, 2021
7bf390c
drivers: can: add NXP LPC MCAN front-end for the Bosch MCAN driver
henrikbrixandersen May 31, 2021
81f0b60
dts: arm: nxp: lpc55S1x: add MCAN devicetree node
henrikbrixandersen May 31, 2021
47f2b94
soc: arm: nxp: lpc55xxx: add MCAN support
henrikbrixandersen May 31, 2021
21cff9b
boards: arm: lpcxpresso55s16: add MCAN support
henrikbrixandersen May 31, 2021
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6 changes: 6 additions & 0 deletions boards/arm/lpcxpresso55s16/doc/index.rst
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Expand Up @@ -73,6 +73,8 @@ hardware features:
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| CAN | on-chip | canbus |
+-----------+------------+-------------------------------------+

Other hardware features are not currently enabled.

Expand Down Expand Up @@ -119,6 +121,10 @@ the functionality of a pin.
+---------+-----------------+----------------------------+
| PIO1_26 | GPIO | FXOS8700 INT1 |
+---------+-----------------+----------------------------+
| PIO1_22 | CAN | CAN RXD |
+---------+-----------------+----------------------------+
| PIO1_27 | CAN | CAN TXD |
+---------+-----------------+----------------------------+

System Clock
============
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2 changes: 2 additions & 0 deletions boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml
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Expand Up @@ -18,6 +18,8 @@ supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- can
- canfd
- gpio
- i2c
- spi
7 changes: 7 additions & 0 deletions boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi
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Expand Up @@ -12,6 +12,7 @@
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
zephyr,entropy = &rng;
zephyr,canbus = &can0;
};

aliases{
Expand Down Expand Up @@ -131,6 +132,12 @@
};
};

&can0 {
status = "okay";
bus-speed = <125000>;
bus-speed-data = <1000000>;
};

&hs_lspi {
status = "okay";
};
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22 changes: 22 additions & 0 deletions boards/arm/lpcxpresso55s16/pinmux.c
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Expand Up @@ -181,6 +181,28 @@ static int lpcxpresso_55s16_pinmux_init(const struct device *dev)
IOCON_PIO_OPENDRAIN_DI);
#endif

#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(can0), nxp_lpc_mcan, okay) && CONFIG_CAN
/* CAN RXD, TXD */
uint32_t port1_pin22_config = (
IOCON_PIO_FUNC9 |
IOCON_PIO_MODE_INACT |
IOCON_PIO_INV_DI |
IOCON_PIO_DIGITAL_EN |
IOCON_PIO_SLEW_STANDARD |
IOCON_PIO_OPENDRAIN_DI
);
uint32_t port1_pin27_config = (
IOCON_PIO_FUNC9 |
IOCON_PIO_MODE_INACT |
IOCON_PIO_INV_DI |
IOCON_PIO_DIGITAL_EN |
IOCON_PIO_SLEW_STANDARD |
IOCON_PIO_OPENDRAIN_DI
);
pinmux_pin_set(port1, 22, port1_pin22_config);
pinmux_pin_set(port1, 27, port1_pin27_config);
#endif

return 0;
}

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1 change: 1 addition & 0 deletions drivers/can/CMakeLists.txt
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@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

zephyr_library()
zephyr_sources_ifdef(CONFIG_CAN_MCUX_MCAN can_mcux_mcan.c)

zephyr_library_sources_ifdef(CONFIG_CAN can_common.c)
zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK can_loopback.c)
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7 changes: 7 additions & 0 deletions drivers/can/Kconfig.mcux
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Expand Up @@ -18,3 +18,10 @@ config CAN_MAX_FILTER
range 1 64 if SOC_SERIES_IMX_RT
help
Defines maximum number of concurrent active RX filters

config CAN_MCUX_MCAN
bool "MCUX MCAN driver"
depends on HAS_MCUX_MCAN && CLOCK_CONTROL
select CAN_MCAN
help
Enable support for mcux mcan driver.
20 changes: 20 additions & 0 deletions drivers/can/can_mcan.c
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Expand Up @@ -297,6 +297,24 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
(can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS);

#ifndef CONFIG_CAN_STM32FD
#ifdef CONFIG_CAN_MCUX_MCAN
uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;

can->mrba = mrba;
can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) |
(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) |
(ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS);
can->rxf0c = (((uint32_t)msg_ram->rx_fifo0 - mrba) & CAN_MCAN_RXF0C_F0SA) |
(ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS);
can->rxf1c = (((uint32_t)msg_ram->rx_fifo1 - mrba) & CAN_MCAN_RXF1C_F1SA) |
(ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS);
can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA);
can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) |
(ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS);
can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) |
(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
#else /* CONFIG_CAN_MCUX_MCAN */
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@dleach02 dleach02 Sep 28, 2021

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So much magic ;-). Just curious but why is this done?

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@henrikbrixandersen henrikbrixandersen Nov 1, 2021

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@henrikbrixandersen what will it take to move this PR out of draft state?

I will need to revisit it. As I recall it, there were some issues with CAN-FD with the current solution.

Also, github added an STM32 tag because of the one dts file you touched. Was that your intention because it doesn't really align with the title of the PR.

One of the commits is touching the generic Bosch M-CAN driver, and thus needed to make a change to the STM32 front-end. I still need to decide if this is the right fix.

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@henrikbrixandersen henrikbrixandersen Jan 3, 2022

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I found the bug in the generic driver, that I was trying to work-around with the commit that touched the STM32 front-end. I have fixed it properly and removed the STM32 changes + label.

The "magic" above is to calculate the relative addresses of the various elements of the Message RAM.

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@alexanderwachter alexanderwachter Jan 9, 2022

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The addressing part is getting tricky as more front-ends are dropping in.
I propose to merge this as is (and also the new STM32H7) and refactor it.
My idea is to have a function ptr in the config structure that is called somewhere during the init.
Somehow a vendor-specific config.

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@henrikbrixandersen henrikbrixandersen Jan 9, 2022

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I agree.

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@henrikbrixandersen henrikbrixandersen Jan 9, 2022

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I propose to merge this as is (and also the new STM32H7) and refactor it.

@alexanderwachter Does that mean you approve this PR?

can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) |
(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) |
Expand All @@ -311,6 +329,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
CAN_MCAN_TXEFC_EFS_POS);
can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) |
(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
#endif /* !CONFIG_CAN_MCUX_MCAN */

if (sizeof(msg_ram->tx_buffer[0].data) <= 24) {
can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4;
} else {
Expand Down
20 changes: 13 additions & 7 deletions drivers/can/can_mcan.h
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Expand Up @@ -8,14 +8,20 @@
#ifndef ZEPHYR_DRIVERS_CAN_MCAN_H_
#define ZEPHYR_DRIVERS_CAN_MCAN_H_

#define NUM_STD_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), std_filter_elements)
#define NUM_EXT_FILTER_ELEMENTS DT_PROP(DT_PATH(soc, can), ext_filter_elements)
#define NUM_RX_FIFO0_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements)
#define NUM_RX_FIFO1_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_fifo0_elements)
#define NUM_RX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), rx_buffer_elements)
#ifdef CONFIG_CAN_MCUX_MCAN
#define MCAN_DT_PATH DT_NODELABEL(can0)
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@alexanderwachter alexanderwachter Jan 9, 2022 •
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Can we do something like

#define MCAN_DT_PATH DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT)

?

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@henrikbrixandersen henrikbrixandersen Jan 10, 2022

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The current approach does not allow for different devicetree configurations of the M_CAN message RAM for multiple M_CAN frontend instances, so it needs to be reworked.

I'd prefer to leave this for the general refactoring of the M_CAN driver once the other frontend drivers are in (#41549 and #41674).

#else
#define MCAN_DT_PATH DT_PATH(soc, can)
#endif

#define NUM_STD_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, std_filter_elements)
#define NUM_EXT_FILTER_ELEMENTS DT_PROP(MCAN_DT_PATH, ext_filter_elements)
#define NUM_RX_FIFO0_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements)
#define NUM_RX_FIFO1_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_fifo0_elements)
#define NUM_RX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, rx_buffer_elements)
#define NUM_TX_EVENT_FIFO_ELEMENTS \
DT_PROP(DT_PATH(soc, can), tx_event_fifo_elements)
#define NUM_TX_BUF_ELEMENTS DT_PROP(DT_PATH(soc, can), tx_buffer_elements)
DT_PROP(MCAN_DT_PATH, tx_event_fifo_elements)
#define NUM_TX_BUF_ELEMENTS DT_PROP(MCAN_DT_PATH, tx_buffer_elements)


#ifdef CONFIG_CAN_STM32FD
Expand Down
14 changes: 13 additions & 1 deletion drivers/can/can_mcan_int.h
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Expand Up @@ -1381,7 +1381,7 @@

/*************** Bit definition for CAN_MCAN_TXEFC register *****************/
/* Event FIFO Watermark */
#define CAN_MCAN_TXEFC_EFSA_POS (0U)
#define CAN_MCAN_TXEFC_EFSA_POS (2U)
#define CAN_MCAN_TXEFC_EFSA_MSK (0x3FFFUL << CAN_MCAN_TXEFC_EFSA_POS)
#define CAN_MCAN_TXEFC_EFSA CAN_MCAN_TXEFC_EFSA_MSK
/* Event FIFO Size */
Expand Down Expand Up @@ -1453,6 +1453,14 @@
#define CAN_MCAN_TXEFA_EFAI CAN_MCAN_TXEFA_EFAI_MSK
#endif /* CONFIG_CAN_STM32FD */

/*************** Bit definition for CAN_MCAN_MRBA register *****************/
#ifdef CONFIG_CAN_MCUX_MCAN
/* Event FIFO Acknowledge Index */
#define CAN_MCAN_MRBA_BA_POS (16U)
#define CAN_MCAN_MRBA_BA_MSK (0xFFFFUL << CAN_MCAN_MRBA_BA_POS)
#define CAN_MCAN_MRBA_BA CAN_MCAN_MRBA_BA_MSK
#endif /* CONFIG_CAN_MCUX_MCAN */

#ifdef CONFIG_CAN_STM32FD
struct can_mcan_reg {
volatile uint32_t crel; /* Core Release Register */
Expand Down Expand Up @@ -1553,6 +1561,10 @@ struct can_mcan_reg {
volatile uint32_t txefc; /* Tx Event FIFO Configuration */
volatile uint32_t txefs; /* Tx Event FIFO Status */
volatile uint32_t txefa; /* Tx Event FIFO Acknowledge */
#ifdef CONFIG_CAN_MCUX_MCAN
volatile uint32_t res6[65]; /* Reserved (65) */
volatile uint32_t mrba; /* Message RAM Base Address */
#endif /* CONFIG_CAN_MCUX_MCAN */
};

#endif /* CONFIG_CAN_STM32FD */
Expand Down
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