diff --git a/boards/arm/gd32e103v_eval/Kconfig.board b/boards/arm/gd32e103v_eval/Kconfig.board new file mode 100644 index 0000000000000..848f4d82a6a36 --- /dev/null +++ b/boards/arm/gd32e103v_eval/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E103V_EVAL + bool "GigaDevice GD32E103V Evaluation Kit" + depends on SOC_GD32E103 diff --git a/boards/arm/gd32e103v_eval/Kconfig.defconfig b/boards/arm/gd32e103v_eval/Kconfig.defconfig new file mode 100644 index 0000000000000..4681d2b2464a5 --- /dev/null +++ b/boards/arm/gd32e103v_eval/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GD32E103V_EVAL + +config BOARD + default "gd32e103v_eval" + +endif # BOARD_GD32E103V_EVAL diff --git a/boards/arm/gd32e103v_eval/board.cmake b/boards/arm/gd32e103v_eval/board.cmake new file mode 100644 index 0000000000000..26032e6d5dc74 --- /dev/null +++ b/boards/arm/gd32e103v_eval/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(gd32isp "--device=GD32E103VBT6") +include(${ZEPHYR_BASE}/boards/common/gd32isp.board.cmake) diff --git a/boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.png b/boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.png new file mode 100644 index 0000000000000..3f984b8889dc7 Binary files /dev/null and b/boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.png differ diff --git a/boards/arm/gd32e103v_eval/doc/index.rst b/boards/arm/gd32e103v_eval/doc/index.rst new file mode 100644 index 0000000000000..c50bbe3035b08 --- /dev/null +++ b/boards/arm/gd32e103v_eval/doc/index.rst @@ -0,0 +1,217 @@ +.. _gd32e103v_eval: + +GigaDevice GD32E103V-EVAL +######################### + + +Overview +******** + +The GD32E103V-EVAL board is a hardware platform that enables design and debug +of the GigaDevice E103 Cortex-M4F High Performance MCU. + +The GD32E103VB features a single-core ARM Cortex-M4F MCU which can run up +to 120-MHz with flash accesses zero wait states, 128kiB of Flash, 32kiB of +SRAM and 80 GPIOs. + +.. image:: img/gd32e103v_eval.png + :width: 800px + :align: center + :alt: gd32e103v_eval + + +Hardware +******** + +- USB interface with mini-USB connector +- 4 user LEDs +- 4 user push buttons +- Reset Button +- ADC connected to a potentiometer +- 2 DAC channels +- GD25Q16 2Mib SPI Flash +- AT24C02C 2KiB EEPROM +- 3.2 TFT LCD (320x240) +- PCM1770 Stereo DAC with Headphone Amplifier +- GD-Link interface + + - CMSIS-DAP swd debug interface over USB HID. + +- 2 CAN port(support CAN-FD) + + - This function is not available in this board due to hardware issues, please check ``GD32C103`` . + +For more information about the GD32E103 SoC and GD32E103V-EVAL board: + +- `GigaDevice Cortex-M4F High Performance SoC Website`_ +- `GD32E103 Datasheet`_ +- `GD32E103 Reference Manual`_ +- `GD32E103V Eval Schematics`_ +- `GD32 ISP Console`_ + + +Supported Features +================== + +The board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v7m-nvic` + * - SYSTICK + - N/A + - N/A + * - USART + - :kconfig:`CONFIG_SERIAL` + - :dtcompatible:`gd,gd32-usart` + + +Serial Port +=========== + +The GD32E103V-EVAL board has 5 serial communication ports. The default port +is UART0 at PIN-9 and PIN-10. + +Programming and Debugging +************************* + +Before program your board make sure to configure boot setting and serial port. +The default serial port is USART0. This port uses header JP-5/6 to route +signals between USB VBUS/ID and USART J2. + ++--------+--------+------------+ +| Boot-0 | Boot-1 | Function | ++========+========+============+ +| 1-2 | 1-2 | SRAM | ++--------+--------+------------+ +| 1-2 | 2-3 | Bootloader | ++--------+--------+------------+ +| 2-3 | Any | Flash | ++--------+--------+------------+ + ++------+------+-------------+ +| JP-5 | JP-6 | Function | ++======+======+=============+ +| 1-2 | 1-2 | USART0 / J2 | ++------+------+-------------+ +| 2-3 | 2-3 | USB VBUS/ID | ++------+------+-------------+ +| open | open | Free | ++------+------+-------------+ + +Using GD-Link +============= + +The GD32E103V-EVAL includes an onboard programmer/debugger (GD-Link) which +allow flash programming and debug over USB. There are also program and debug +headers J1 and J100 that can be used with any ARM compatible tools. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32e103v_eval + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32e103v_eval + :goals: flash + :compact: + + You should see "Hello World! gd32e103v_eval" in your terminal. + +#. To debug an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32e103v_eval + :goals: debug + :compact: + + +Using ROM bootloader +==================== + +The GD32E103 MCU have a ROM bootloader which allow flash programming. User +should install `GD32 ISP Console`_ software at some Linux path. The recommended +is :code:`$HOME/.local/bin`. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: gd32e103v_eval + :goals: build + :compact: + +#. Enable board bootloader: + + - Remove boot-0 jumper + - press reset button + +#. To flash an image: + + .. code-block:: console + + west build -b gd32e103v_eval samples/hello_world + west flash -r gd32isp [--port=/dev/ttyUSB0] + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Press reset button + + You should see "Hello World! gd32e103v_eval" in your terminal. + + +.. _GigaDevice Cortex-M4F High Performance SoC Website: + https://www.gigadevice.com/products/microcontrollers/gd32/arm-cortex-m4/value-line/gd32e103-series/ + +.. _GD32E103 Datasheet: + http://www.gd32mcu.com/download/down/document_id/235/path_type/1 + +.. _GD32E103 Reference Manual: + http://www.gd32mcu.com/download/down/document_id/163/path_type/1 + +.. _GD32E103V Eval Schematics: + http://www.gd32mcu.com/download/down/document_id/178/path_type/1 + +.. _GD32 ISP Console: + http://www.gd32mcu.com/download/down/document_id/175/path_type/1 diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi b/boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi new file mode 100644 index 0000000000000..4be138b4af436 --- /dev/null +++ b/boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group1 { + pinmux = , ; + }; + }; + + pwm0_default: pwm0_default { + group1 { + pinmux = ; + }; + }; + + dac_default: dac_default { + group1 { + pinmux = ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + drive-open-drain; + }; + }; +}; diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.dts b/boards/arm/gd32e103v_eval/gd32e103v_eval.dts new file mode 100644 index 0000000000000..5b78eae6dc86a --- /dev/null +++ b/boards/arm/gd32e103v_eval/gd32e103v_eval.dts @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2021, YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "gd32e103v_eval-pinctrl.dtsi" + +/ { + model = "GigaDevice gd32e103v Evaluation Kit"; + compatible = "gd,gd32e103v"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + }; + + leds { + compatible = "gpio-leds"; + led2: led2 { + gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; + label = "LED2"; + }; + led3: led3 { + gpios = <&gpioc 2 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + led4: led4 { + gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + led5: led5 { + gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>; + label = "LED5"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + wakeup_key: wakeup_key { + label = "WAKEUP_KEY"; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + }; + tamper_key: tamper_key { + label = "TAMPER_KEY"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + user_key: user_key { + label = "USER_KEY1"; + gpios = <&gpiob 14 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + /* NOTE: bridge TIMER0_CH0 (PA8) and LED1 (PC0) */ + pwm_led: pwm_led { + pwms = <&pwm0 0 PWM_POLARITY_NORMAL>; + }; + }; + + aliases { + led0 = &led2; + led1 = &led3; + sw0 = &user_key; + pwm-led0 = &pwm_led; + eeprom-0 = &eeprom0; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&usart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + eeprom0: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + status = "okay"; + label = "EEPROM_AT24C02"; + size = <256>; + pagesize = <8>; + address-width = <8>; + timeout = <5>; + }; +}; + +&dac { + status = "okay"; + pinctrl-0 = <&dac_default>; + pinctrl-names = "default"; +}; diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml b/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml new file mode 100644 index 0000000000000..9d906f8ed29ee --- /dev/null +++ b/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +identifier: gd32e103v_eval +name: GigaDevice GD32E103V Evaluation Kit +type: mcu +arch: arm +ram: 32 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig b/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig new file mode 100644 index 0000000000000..d0da83af86d0c --- /dev/null +++ b/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_GD32E10X=y +CONFIG_SOC_GD32E103=y +CONFIG_BOARD_GD32E103V_EVAL=y + +CONFIG_GD32_HXTAL_8MHZ=y +CONFIG_CORTEX_M_SYSTICK=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32e103v_eval/support/openocd.cfg b/boards/arm/gd32e103v_eval/support/openocd.cfg new file mode 100644 index 0000000000000..5d773bf960089 --- /dev/null +++ b/boards/arm/gd32e103v_eval/support/openocd.cfg @@ -0,0 +1,26 @@ +# Copyright (c) 2021, ATL-Electronics +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME gd32e103vb +set ENDIAN little +set CPUTAPID 0x2ba01477 +set FLASH_SIZE 0x20000 + +source [find target/stm32f1x.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + diff --git a/drivers/pinctrl/pinctrl_gd32_afio.c b/drivers/pinctrl/pinctrl_gd32_afio.c index d413a7f9c9b1a..46f35a4173482 100644 --- a/drivers/pinctrl/pinctrl_gd32_afio.c +++ b/drivers/pinctrl/pinctrl_gd32_afio.c @@ -5,6 +5,7 @@ */ #include +#include /** AFIO DT node */ #define AFIO_NODE DT_NODELABEL(afio) diff --git a/dts/arm/gigadevice/gd32e10x/gd32e103vbt6.dtsi b/dts/arm/gigadevice/gd32e10x/gd32e103vbt6.dtsi new file mode 100644 index 0000000000000..f285034aea13c --- /dev/null +++ b/dts/arm/gigadevice/gd32e10x/gd32e103vbt6.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi b/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi new file mode 100644 index 0000000000000..7d8de3594b73b --- /dev/null +++ b/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2021 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + clock-frequency = <120000000>; + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + FMC: flash-controller@40022000 { + compatible = "gd,gd32-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40022000 0x400>; + peripheral-id = <6>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + }; + + usart0: usart@40013800 { + compatible = "gd,gd32-usart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + rcu-periph-clock = <0x60e>; + status = "disabled"; + label = "USART_0"; + }; + + usart1: usart@40004400 { + compatible = "gd,gd32-usart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + rcu-periph-clock = <0x711>; + status = "disabled"; + label = "USART_1"; + }; + + usart2: usart@40004800 { + compatible = "gd,gd32-usart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + rcu-periph-clock = <0x712>; + status = "disabled"; + label = "USART_2"; + }; + + uart3: usart@40004c00 { + compatible = "gd,gd32-usart"; + reg = <0x40004c00 0x400>; + interrupts = <52 0>; + rcu-periph-clock = <0x713>; + status = "disabled"; + label = "USART_3"; + }; + + uart4: usart@40005000 { + compatible = "gd,gd32-usart"; + reg = <0x40005000 0x400>; + interrupts = <53 0>; + rcu-periph-clock = <0x714>; + status = "disabled"; + label = "USART_4"; + }; + + dac: dac@40007400 { + compatible = "gd,gd32-dac"; + reg = <0x40007400 0x400>; + rcu-periph-clock = <0x71d>; + num-channels = <2>; + label = "DAC"; + status = "disabled"; + #io-channel-cells = <1>; + }; + + i2c0: i2c@40005400 { + compatible = "gd,gd32-i2c"; + reg = <0x40005400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <31 0>, <32 0>; + interrupt-names = "event", "error"; + rcu-periph-clock = <0x715>; + status = "disabled"; + label = "I2C_0"; + }; + + i2c1: i2c@40005800 { + compatible = "gd,gd32-i2c"; + reg = <0x40005800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <33 0>, <34 0>; + interrupt-names = "event", "error"; + rcu-periph-clock = <0x716>; + status = "disabled"; + label = "I2C_1"; + }; + + afio: afio@40010000 { + compatible = "gd,gd32-afio"; + reg = <0x40010000 0x400>; + rcu-periph-clock = <0x600>; + status = "okay"; + label = "AFIO"; + }; + + exti: interrupt-controller@40010400 { + compatible = "gd,gd32-exti"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x40010400 0x400>; + num-lines = <19>; + interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>, + <40 0>; + interrupt-names = "line0", "line1", "line2", "line3", + "line4", "line5-9", "line10-15"; + status = "okay"; + label = "EXTI"; + }; + + pinctrl: pin-controller@40010800 { + compatible = "gd,gd32-pinctrl-afio"; + reg = <0x40010800 0x1c00>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + label = "PINCTRL"; + + gpioa: gpio@40010800 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40010800 0x400>; + rcu-periph-clock = <0x602>; + status = "disabled"; + label = "GPIOA"; + }; + + gpiob: gpio@40010c00 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40010c00 0x400>; + rcu-periph-clock = <0x603>; + status = "disabled"; + label = "GPIOB"; + }; + + gpioc: gpio@40011000 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40011000 0x400>; + rcu-periph-clock = <0x604>; + status = "disabled"; + label = "GPIOC"; + }; + + gpiod: gpio@40011400 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40011400 0x400>; + rcu-periph-clock = <0x605>; + status = "disabled"; + label = "GPIOD"; + }; + + gpioe: gpio@40011800 { + compatible = "gd,gd32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40011800 0x400>; + rcu-periph-clock = <0x606>; + status = "disabled"; + label = "GPIOE"; + }; + }; + + timer0: timer@40012c00 { + compatible = "gd,gd32-timer"; + reg = <0x40012c00 0x400>; + interrupts = <24 0>, <25 0>, <26 0>, <27 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + rcu-periph-clock = <0x60b>; + rcu-periph-reset = <0x30b>; + is-advanced; + channels = <4>; + status = "disabled"; + label = "TIMER_0"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_0"; + #pwm-cells = <2>; + }; + }; + + timer1: timer@40000000 { + compatible = "gd,gd32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x700>; + rcu-periph-reset = <0x400>; + channels = <4>; + status = "disabled"; + label = "TIMER_1"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_1"; + #pwm-cells = <2>; + }; + }; + + timer2: timer@40000400 { + compatible = "gd,gd32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x701>; + rcu-periph-reset = <0x401>; + channels = <4>; + status = "disabled"; + label = "TIMER_2"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_2"; + #pwm-cells = <2>; + }; + }; + + timer3: timer@40000800 { + compatible = "gd,gd32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x702>; + rcu-periph-reset = <0x402>; + channels = <4>; + status = "disabled"; + label = "TIMER_3"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_3"; + #pwm-cells = <2>; + }; + }; + + timer4: timer@40000c00 { + compatible = "gd,gd32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x703>; + rcu-periph-reset = <0x403>; + channels = <4>; + status = "disabled"; + label = "TIMER_4"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_4"; + #pwm-cells = <2>; + }; + }; + + timer5: timer@40001000 { + compatible = "gd,gd32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x704>; + rcu-periph-reset = <0x404>; + channels = <0>; + status = "disabled"; + label = "TIMER_5"; + }; + + timer6: timer@40001400 { + compatible = "gd,gd32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x705>; + rcu-periph-reset = <0x405>; + channels = <0>; + status = "disabled"; + label = "TIMER_6"; + }; + + timer7: timer@40013400 { + compatible = "gd,gd32-timer"; + reg = <0x40013400 0x400>; + interrupts = <43 0>, <44 0>, <45 0>, <46 0>; + interrupt-names = "brk", "up", "trgcom", "cc"; + rcu-periph-clock = <0x60d>; + rcu-periph-reset = <0x30d>; + is-advanced; + channels = <4>; + status = "disabled"; + label = "TIMER_7"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_7"; + #pwm-cells = <2>; + }; + }; + + timer8: timer@40014c00 { + compatible = "gd,gd32-timer"; + reg = <0x40014c00 0x400>; + interrupts = <24 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x613>; + rcu-periph-reset = <0x313>; + channels = <2>; + status = "disabled"; + label = "TIMER_8"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_8"; + #pwm-cells = <2>; + }; + }; + + timer9: timer@40015000 { + compatible = "gd,gd32-timer"; + reg = <0x40015000 0x400>; + interrupts = <25 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x614>; + rcu-periph-reset = <0x314>; + channels = <1>; + status = "disabled"; + label = "TIMER_9"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_9"; + #pwm-cells = <2>; + }; + }; + + timer10: timer@40015400 { + compatible = "gd,gd32-timer"; + reg = <0x40015400 0x400>; + interrupts = <26 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x615>; + rcu-periph-reset = <0x315>; + channels = <1>; + status = "disabled"; + label = "TIMER_10"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_10"; + #pwm-cells = <2>; + }; + }; + + timer11: timer@40001800 { + compatible = "gd,gd32-timer"; + reg = <0x40001800 0x400>; + interrupts = <43 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x706>; + rcu-periph-reset = <0x406>; + channels = <2>; + status = "disabled"; + label = "TIMER_11"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_11"; + #pwm-cells = <2>; + }; + }; + + timer12: timer@40001c00 { + compatible = "gd,gd32-timer"; + reg = <0x40001c00 0x400>; + interrupts = <44 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x707>; + rcu-periph-reset = <0x402>; + channels = <1>; + status = "disabled"; + label = "TIMER_12"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_12"; + #pwm-cells = <2>; + }; + }; + + timer13: timer@40002000 { + compatible = "gd,gd32-timer"; + reg = <0x40002000 0x400>; + interrupts = <45 0>; + interrupt-names = "global"; + rcu-periph-clock = <0x708>; + rcu-periph-reset = <0x408>; + channels = <1>; + status = "disabled"; + label = "TIMER_13"; + + pwm { + compatible = "gd,gd32-pwm"; + status = "disabled"; + label = "PWM_13"; + #pwm-cells = <2>; + }; + }; + + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/modules/hal_gigadevice/Kconfig b/modules/hal_gigadevice/Kconfig index a26c03b044746..9e892d1aeaf8f 100644 --- a/modules/hal_gigadevice/Kconfig +++ b/modules/hal_gigadevice/Kconfig @@ -24,6 +24,7 @@ choice GD32_HXTAL_FREQUENCY prompt "High speed external oscillator clock frequency" default GD32_HXTAL_FIRMWARE_DEFINED if !SOC_SERIES_GD32VF103 default GD32_HXTAL_25MHZ if SOC_SERIES_GD32VF103 + default GD32_HXTAL_8MHZ if SOC_SERIES_GD32E10X help Define value of high speed crystal oscillator (HXTAL) in Hz This value sets the frequency of the oscillator. @@ -31,6 +32,7 @@ choice GD32_HXTAL_FREQUENCY config GD32_HXTAL_FIRMWARE_DEFINED bool "Firmware defined" depends on !SOC_SERIES_GD32VF103 + depends on !SOC_SERIES_GD32E10X help Use default frequency defined in firmware for HXTAL This is using for SoCs (e.g. gd32f4xx, gd32f3x0, etc ...) @@ -38,13 +40,13 @@ config GD32_HXTAL_FIRMWARE_DEFINED config GD32_HXTAL_8MHZ bool "8MHz" - depends on SOC_SERIES_GD32VF103 + depends on SOC_SERIES_GD32VF103 || SOC_SERIES_GD32E10X help Use 8MHz oscillator for HXTAL config GD32_HXTAL_25MHZ bool "25MHz" - depends on SOC_SERIES_GD32VF103 + depends on SOC_SERIES_GD32VF103 || SOC_SERIES_GD32E10X help Use 25MHz oscillator for HXTAL diff --git a/samples/drivers/dac/boards/gd32e103v_eval.overlay b/samples/drivers/dac/boards/gd32e103v_eval.overlay new file mode 100644 index 0000000000000..38aa2ea304da2 --- /dev/null +++ b/samples/drivers/dac/boards/gd32e103v_eval.overlay @@ -0,0 +1,13 @@ +/* + * Copyright 2021 BrainCo Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; diff --git a/samples/drivers/eeprom/boards/gd32e103v_eval.conf b/samples/drivers/eeprom/boards/gd32e103v_eval.conf new file mode 100644 index 0000000000000..f6a16047dec98 --- /dev/null +++ b/samples/drivers/eeprom/boards/gd32e103v_eval.conf @@ -0,0 +1,3 @@ +CONFIG_I2C=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_INIT_PRIORITY=75 diff --git a/soc/arm/gigadevice/gd32e10x/CMakeLists.txt b/soc/arm/gigadevice/gd32e10x/CMakeLists.txt new file mode 100644 index 0000000000000..58df401dc74f3 --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) diff --git a/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32e103 b/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32e103 new file mode 100644 index 0000000000000..38dfedb9cd05c --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32e103 @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC + default "gd32e103" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config NUM_IRQS + default 83 diff --git a/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.series new file mode 100644 index 0000000000000..5a17c08d86471 --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32E10X + +source "soc/arm/gigadevice/gd32e10x/Kconfig.defconfig.gd32*" + +config SOC_SERIES + default "gd32e10x" + +endif # SOC_SERIES_GD32E10X diff --git a/soc/arm/gigadevice/gd32e10x/Kconfig.series b/soc/arm/gigadevice/gd32e10x/Kconfig.series new file mode 100644 index 0000000000000..ac0a5059fca88 --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/Kconfig.series @@ -0,0 +1,14 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E10X + bool "GigaDevice GD32E10X series Cortex-M4F MCU" + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select SOC_FAMILY_GD32_ARM + select GD32_HAS_AFIO_PINMUX + help + Enable support for GigaDevice GD32E10X MCU series diff --git a/soc/arm/gigadevice/gd32e10x/Kconfig.soc b/soc/arm/gigadevice/gd32e10x/Kconfig.soc new file mode 100644 index 0000000000000..42e6cd14d9908 --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "GigaDevice GD32E103 MCU Selection" + depends on SOC_SERIES_GD32E10X + + config SOC_GD32E103 + bool "gd32e103" +endchoice diff --git a/soc/arm/gigadevice/gd32e10x/linker.ld b/soc/arm/gigadevice/gd32e10x/linker.ld new file mode 100644 index 0000000000000..697d7e351236a --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/linker.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/gigadevice/gd32e10x/soc.c b/soc/arm/gigadevice/gd32e10x/soc.c new file mode 100644 index 0000000000000..80cf3bada588e --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/soc.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static int gd32e10x_soc_init(const struct device *dev) +{ + uint32_t key; + + ARG_UNUSED(dev); + + key = irq_lock(); + + SystemInit(); + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(gd32e10x_soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/gigadevice/gd32e10x/soc.h b/soc/arm/gigadevice/gd32e10x/soc.h new file mode 100644 index 0000000000000..b4c105337312b --- /dev/null +++ b/soc/arm/gigadevice/gd32e10x/soc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 YuLong Yao + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_ +#define _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ARM_GIGADEVICE_GD32E10X_SOC_H_ */ diff --git a/west.yml b/west.yml index 0c6360b99db6b..aaf8581f2ffc5 100644 --- a/west.yml +++ b/west.yml @@ -73,7 +73,7 @@ manifest: groups: - hal - name: hal_gigadevice - revision: 242a7f4be7a3136606c7a65169775f7ef85ad444 + revision: cc85acbd635f02122c54df11fa55458269ce1bdd path: modules/hal/gigadevice groups: - hal