diff --git a/boards/arm/mimxrt685_evk/Kconfig.defconfig b/boards/arm/mimxrt685_evk/Kconfig.defconfig index 6b2f51008d0f0..13b5e7e5323c8 100644 --- a/boards/arm/mimxrt685_evk/Kconfig.defconfig +++ b/boards/arm/mimxrt685_evk/Kconfig.defconfig @@ -38,4 +38,7 @@ config HEAP_MEM_POOL_SIZE endif # DMA_MCUX_LPC +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + endif # BOARD_MIMXRT685_EVK diff --git a/boards/arm/mimxrt685_evk/doc/index.rst b/boards/arm/mimxrt685_evk/doc/index.rst index 0ea84b42ec4ec..01df1de6997ff 100644 --- a/boards/arm/mimxrt685_evk/doc/index.rst +++ b/boards/arm/mimxrt685_evk/doc/index.rst @@ -91,6 +91,8 @@ features: +-----------+------------+-------------------------------------+ | WDT | on-chip | watchdog | +-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: @@ -165,6 +167,24 @@ functionality of a pin. +---------+-----------------+----------------------------+ | PIO0_27 | SCT0_OUT7 | PWM | +---------+-----------------+----------------------------+ +| PIO1_30 | SD0_CLK | SD card | ++---------+-----------------+----------------------------+ +| PIO1_31 | SD0_CMD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_0 | SD0_D0 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_1 | SD0_D1 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_2 | SD0_D2 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_3 | SD0_D3 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_4 | SD0_WR_PRT | SD card | ++---------+-----------------+----------------------------+ +| PIO2_9 | SD0_CD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_10 | SD0_RST | SD card | ++---------+-----------------+----------------------------+ System Clock ============ diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts index d5e8aa5e87ad9..91cb63cd75c5f 100644 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts +++ b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts @@ -253,6 +253,10 @@ i2s1: &flexcomm3 { status = "okay"; }; +&gpio2 { + status = "okay"; +}; + &dma0 { /* * The total number of dma channels available is defined by @@ -293,3 +297,8 @@ i2s1: &flexcomm3 { &sc_timer { status = "okay"; }; + +&usdhc1 { + status = "okay"; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml index 37375da331149..dcea7dca48be9 100644 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml +++ b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml @@ -25,5 +25,6 @@ supported: - hwinfo - i2c - i2s + - sdhc - spi - watchdog diff --git a/boards/arm/mimxrt685_evk/pinmux.c b/boards/arm/mimxrt685_evk/pinmux.c index 165d9e646f32d..a5df9a469de27 100644 --- a/boards/arm/mimxrt685_evk/pinmux.c +++ b/boards/arm/mimxrt685_evk/pinmux.c @@ -768,6 +768,197 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev) IOPCTL_PinMuxSet(IOPCTL, 0U, 31U, port0_pin31_config); #endif +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC + uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */ + IOPCTL_PIO_FUNC1 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */ + IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config); + + uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */ + IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config); + + uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config); + + uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config); + + uint32_t port2_pin10_config = (/* Pin is configured as PIO2_10 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 10U, port2_pin10_config); + + uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config); + + uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config); + + uint32_t port2_pin4_config = (/* Pin is configured as PIO2_4 */ + IOPCTL_PIO_FUNC0 | + /* Disable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_DI | + /* Enable pull-down function */ + IOPCTL_PIO_PULLDOWN_EN | + /* Disable input buffer function */ + IOPCTL_PIO_INBUF_DI | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN4 (coords: T13) is configured as PIO2_4 */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 4U, port2_pin4_config); + + uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */ + IOPCTL_PIO_FUNC1 | + /* Enable pull-up / pull-down function */ + IOPCTL_PIO_PUPD_EN | + /* Enable pull-up function */ + IOPCTL_PIO_PULLUP_EN | + /* Enables input buffer function */ + IOPCTL_PIO_INBUF_EN | + /* Normal mode */ + IOPCTL_PIO_SLEW_RATE_NORMAL | + /* Normal drive */ + IOPCTL_PIO_FULLDRIVE_DI | + /* Analog mux is disabled */ + IOPCTL_PIO_ANAMUX_DI | + /* Pseudo Output Drain is disabled */ + IOPCTL_PIO_PSEDRAIN_DI | + /* Input function is not inverted */ + IOPCTL_PIO_INV_DI); + /* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */ + IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config); #endif return 0; diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 6eb278d191287..b879d1f03042b 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -72,6 +72,14 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( LOG_ERR("Missing feature define for HS_SPI clock!"); #endif break; +#if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT) + case MCUX_USDHC1_CLK: + *rate = CLOCK_GetSdioClkFreq(0); + break; + case MCUX_USDHC2_CLK: + *rate = CLOCK_GetSdioClkFreq(1); + break; +#endif } #endif diff --git a/drivers/disk/usdhc.c b/drivers/disk/usdhc.c index debce3d0a9588..e92598d427392 100644 --- a/drivers/disk/usdhc.c +++ b/drivers/disk/usdhc.c @@ -2256,7 +2256,6 @@ static void usdhc_host_reset(struct usdhc_priv *priv) usdhc_enable_ddr_mode(base, false, 0); usdhc_tuning(base, SDHC_STANDARD_TUNING_START, SDHC_TUINIG_STEP, false); #if FSL_FEATURE_USDHC_HAS_HS400_MODE -#error Not implemented! /* Disable HS400 mode */ /* Disable DLL */ #endif @@ -2600,8 +2599,9 @@ static K_MUTEX_DEFINE(z_usdhc_init_lock); static int usdhc_board_access_init(struct usdhc_priv *priv) { const struct usdhc_config *config = priv->config; - int ret; + int ret = 0; uint32_t gpio_level; + USDHC_Type *base = config->base; if (config->pwr_name) { priv->pwr_gpio = device_get_binding(config->pwr_name); @@ -2634,35 +2634,41 @@ static int usdhc_board_access_init(struct usdhc_priv *priv) } if (!priv->detect_gpio) { - LOG_INF("USDHC detection other than GPIO not implemented!"); - return 0; - } + LOG_INF("USDHC detection other than GPIO"); + /* DATA3 does not monitor card insertion */ + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + if ((base->PRES_STATE & USDHC_PRES_STATE_CINST_MASK) != 0) { + priv->inserted = true; + } else { + priv->inserted = false; + ret = -ENODEV; + } + } else { + ret = usdhc_cd_gpio_init(priv->detect_gpio, + config->detect_pin, + config->detect_flags, + &priv->detect_cb); + if (ret) { + return ret; + } + ret = gpio_pin_get(priv->detect_gpio, config->detect_pin); + if (ret < 0) { + return ret; + } - ret = usdhc_cd_gpio_init(priv->detect_gpio, - config->detect_pin, - config->detect_flags, - &priv->detect_cb); - if (ret) { - return ret; - } - ret = gpio_pin_get(priv->detect_gpio, config->detect_pin); - if (ret < 0) { - return ret; - } + gpio_level = ret; - gpio_level = ret; + if (gpio_level == 0) { + priv->inserted = false; + LOG_ERR("NO SD inserted!"); - if (gpio_level == 0) { - priv->inserted = false; - LOG_ERR("NO SD inserted!"); + return -ENODEV; + } - return -ENODEV; + priv->inserted = true; + LOG_INF("SD inserted!"); } - - priv->inserted = true; - LOG_INF("SD inserted!"); - - return 0; + return ret; } static int usdhc_access_init(const struct device *dev) diff --git a/drivers/gpio/gpio_mcux_lpc.c b/drivers/gpio/gpio_mcux_lpc.c index 1db2296417846..91e76685a69a2 100644 --- a/drivers/gpio/gpio_mcux_lpc.c +++ b/drivers/gpio/gpio_mcux_lpc.c @@ -364,6 +364,7 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS; #define GPIO_MCUX_LPC_IRQ_CONNECT(n, m) \ do { \ + struct gpio_mcux_lpc_data *data = dev->data; \ IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \ DT_INST_IRQ_BY_IDX(n, m, priority), \ gpio_mcux_lpc_port_isr, DEVICE_DT_INST_GET(n), 0); \ @@ -374,6 +375,7 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS; #define GPIO_MCUX_LPC_IRQ(n, m) \ COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, m), (GPIO_MCUX_LPC_IRQ_CONNECT(n, m)), ()) + #define GPIO_MCUX_LPC(n) \ static int lpc_gpio_init_##n(const struct device *dev); \ \ @@ -398,8 +400,6 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS; \ static int lpc_gpio_init_##n(const struct device *dev) \ { \ - struct gpio_mcux_lpc_data *data = dev->data; \ - \ gpio_mcux_lpc_init(dev); \ \ GPIO_MCUX_LPC_IRQ(n, 0); \ diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index 6fcc003e52842..92a531a07c946 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -101,6 +101,15 @@ port = <1>; }; + gpio2: gpio@2 { + compatible = "nxp,lpc-gpio"; + reg = <0x100000 0x4000>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + port = <2>; + }; + flexspi: spi@134000 { compatible = "nxp,imx-flexspi"; reg = <0x134000 0x1000>; @@ -268,6 +277,24 @@ clk-divider = <1>; label = "WWDT_1"; }; + + usdhc1: usdhc@136000 { + compatible = "nxp,imx-usdhc"; + reg = <0x136000 0x4000>; + status = "disabled"; + interrupts = <45 0>; + clocks = <&clkctl1 MCUX_USDHC1_CLK>; + label = "USDHC_1"; + }; + + usdhc2: usdhc@137000 { + compatible = "nxp,imx-usdhc"; + reg = <0x137000 0x4000>; + status = "disabled"; + interrupts = <46 0>; + clocks = <&clkctl1 MCUX_USDHC2_CLK>; + label = "USDHC_2"; + }; }; &nvic { diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml index e7f17fb09e5d7..6f161fa92057f 100644 --- a/dts/bindings/gpio/nxp,lpc-gpio.yaml +++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml @@ -24,6 +24,7 @@ properties: enum: - 0 - 1 + - 2 gpio-cells: - pin diff --git a/include/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/dt-bindings/clock/mcux_lpc_syscon_clock.h index 5528fff2e7550..756e195678411 100644 --- a/include/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -16,5 +16,7 @@ #define MCUX_FLEXCOMM6_CLK 6 #define MCUX_FLEXCOMM7_CLK 7 #define MCUX_HS_SPI_CLK 8 +#define MCUX_USDHC1_CLK 9 +#define MCUX_USDHC2_CLK 10 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ diff --git a/soc/arm/nxp_imx/rt/soc.h b/soc/arm/nxp_imx/rt/soc.h index 968e17b7f5cab..826def7bce518 100644 --- a/soc/arm/nxp_imx/rt/soc.h +++ b/soc/arm/nxp_imx/rt/soc.h @@ -22,7 +22,7 @@ extern "C" { #if CONFIG_DISK_DRIVER_SDMMC && \ (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) || \ - DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay)) + DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay)) typedef void (*usdhc_pin_cfg_cb)(uint16_t nusdhc, bool init, uint32_t speed, uint32_t strength); diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.soc b/soc/arm/nxp_imx/rt6xx/Kconfig.soc index 1e009ed51b200..faf66d56eb085 100644 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.soc +++ b/soc/arm/nxp_imx/rt6xx/Kconfig.soc @@ -25,6 +25,8 @@ config SOC_MIMXRT685S_CM33 select HAS_MCUX_LPC_RTC select HAS_MCUX_TRNG select HAS_MCUX_SCTIMER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 select INIT_SYS_PLL endchoice diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c index c2e1c933c43d9..ec68860e855fb 100644 --- a/soc/arm/nxp_imx/rt6xx/soc.c +++ b/soc/arm/nxp_imx/rt6xx/soc.c @@ -171,6 +171,7 @@ static ALWAYS_INLINE void clock_init(void) /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); #endif + #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)) CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); #else @@ -179,9 +180,34 @@ static ALWAYS_INLINE void clock_init(void) */ CLOCK_AttachClk(kNONE_to_WDT0_CLK); #endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC + /* Make sure USDHC ram buffer has been power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); + CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + CLOCK_EnableClock(kCLOCK_Sdio0); + RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); +#endif + #endif /* CONFIG_SOC_MIMXRT685S_CM33 */ } +#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC) + +void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, + uint32_t speed, uint32_t strength) +{ + +} +#endif + /** * * @brief Perform basic hardware initialization diff --git a/soc/arm/nxp_imx/rt6xx/soc.h b/soc/arm/nxp_imx/rt6xx/soc.h index d6307c5161e0f..d2476dece1898 100644 --- a/soc/arm/nxp_imx/rt6xx/soc.h +++ b/soc/arm/nxp_imx/rt6xx/soc.h @@ -75,4 +75,21 @@ /*!<@brief Slow mode */ #define IOPCTL_PIO_SLEW_RATE_SLOW 0x80u +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_DISK_DRIVER_SDMMC && \ + (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) || \ + DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay)) + +void imxrt_usdhc_pinmux(uint16_t nusdhc, + bool init, uint32_t speed, uint32_t strength); + +#endif + +#ifdef __cplusplus +} +#endif + #endif /* _SOC__H_ */